File: /usr/src/linux/arch/ppc/8260_io/fcc_enet.c
1 /*
2 * BK Id: SCCS/s.fcc_enet.c 1.7 05/17/01 18:14:20 cort
3 */
4 /*
5 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
6 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
7 *
8 * This version of the driver is a combination of the 8xx fec and
9 * 8260 SCC Ethernet drivers. People seem to be choosing common I/O
10 * configurations, so this driver will work on the EST8260 boards and
11 * others yet to be announced.
12 *
13 * Right now, I am very watseful with the buffers. I allocate memory
14 * pages and then divide them into 2K frame buffers. This way I know I
15 * have buffers large enough to hold one frame within one buffer descriptor.
16 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
17 * will be much more memory efficient and will easily handle lots of
18 * small packets.
19 *
20 */
21
22 #include <linux/config.h>
23 #include <linux/kernel.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/ptrace.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38
39 #include <asm/immap_8260.h>
40 #include <asm/pgtable.h>
41 #include <asm/mpc8260.h>
42 #include <asm/irq.h>
43 #include <asm/bitops.h>
44 #include <asm/uaccess.h>
45 #include <asm/cpm_8260.h>
46
47 /* The transmitter timeout
48 */
49 #define TX_TIMEOUT (2*HZ)
50
51 /* The number of Tx and Rx buffers. These are allocated from the page
52 * pool. The code may assume these are power of two, so it is best
53 * to keep them that size.
54 * We don't need to allocate pages for the transmitter. We just use
55 * the skbuffer directly.
56 */
57 #define FCC_ENET_RX_PAGES 16
58 #define FCC_ENET_RX_FRSIZE 2048
59 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
60 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
61 #define TX_RING_SIZE 16 /* Must be power of two */
62 #define TX_RING_MOD_MASK 15 /* for this to work */
63
64 /* The FCC stores dest/src/type, data, and checksum for receive packets.
65 */
66 #define PKT_MAXBUF_SIZE 1518
67 #define PKT_MINBUF_SIZE 64
68
69 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
70 */
71 #define PKT_MAXDMA_SIZE 1520
72
73 /* Maximum input buffer size. Must be a multiple of 32.
74 */
75 #define PKT_MAXBLR_SIZE 1536
76
77 static int fcc_enet_open(struct net_device *dev);
78 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
79 static int fcc_enet_rx(struct net_device *dev);
80 static void fcc_enet_mii(struct net_device *dev);
81 static void fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
82 static int fcc_enet_close(struct net_device *dev);
83 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
84 static void set_multicast_list(struct net_device *dev);
85 static void restart_fcc(struct net_device *dev);
86
87 /* These will be configurable for the FCC choice.
88 * Multiple ports can be configured. There is little choice among the
89 * I/O pins to the PHY, except the clocks. We will need some board
90 * dependent clock selection.
91 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
92 * help show what pins are used for each device.
93 */
94
95 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
96 * but there is little variation among the choices.
97 */
98 #define PA1_COL ((uint)0x00000001)
99 #define PA1_CRS ((uint)0x00000002)
100 #define PA1_TXER ((uint)0x00000004)
101 #define PA1_TXEN ((uint)0x00000008)
102 #define PA1_RXDV ((uint)0x00000010)
103 #define PA1_RXER ((uint)0x00000020)
104 #define PA1_TXDAT ((uint)0x00003c00)
105 #define PA1_RXDAT ((uint)0x0003c000)
106 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
107 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
108 PA1_RXDV | PA1_RXER)
109 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
110 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
111
112 /* CLK12 is receive, CLK11 is transmit. These are board specific.
113 */
114 #define PC_F1RXCLK ((uint)0x00000800)
115 #define PC_F1TXCLK ((uint)0x00000400)
116 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
117 #define CMX1_CLK_MASK ((uint)0xff000000)
118
119 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
120 * but there is little variation among the choices.
121 */
122 #define PB2_TXER ((uint)0x00000001)
123 #define PB2_RXDV ((uint)0x00000002)
124 #define PB2_TXEN ((uint)0x00000004)
125 #define PB2_RXER ((uint)0x00000008)
126 #define PB2_COL ((uint)0x00000010)
127 #define PB2_CRS ((uint)0x00000020)
128 #define PB2_TXDAT ((uint)0x000003c0)
129 #define PB2_RXDAT ((uint)0x00003c00)
130 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
131 PB2_RXER | PB2_RXDV | PB2_TXER)
132 #define PB2_PSORB1 (PB2_TXEN)
133 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
134 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
135
136 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
137 */
138 #define PC_F2RXCLK ((uint)0x00001000)
139 #define PC_F2TXCLK ((uint)0x00002000)
140 #define CMX2_CLK_ROUTE ((uint)0x00250000)
141 #define CMX2_CLK_MASK ((uint)0x00ff0000)
142
143 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
144 * but there is little variation among the choices.
145 */
146 #define PB3_RXDV ((uint)0x00004000)
147 #define PB3_RXER ((uint)0x00008000)
148 #define PB3_TXER ((uint)0x00010000)
149 #define PB3_TXEN ((uint)0x00020000)
150 #define PB3_COL ((uint)0x00040000)
151 #define PB3_CRS ((uint)0x00080000)
152 #define PB3_TXDAT ((uint)0x0f000000)
153 #define PB3_RXDAT ((uint)0x00f00000)
154 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
155 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
156 #define PB3_PSORB1 (0)
157 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
158 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
159
160 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
161 */
162 #define PC_F3RXCLK ((uint)0x00004000)
163 #define PC_F3TXCLK ((uint)0x00008000)
164 #define CMX3_CLK_ROUTE ((uint)0x00003700)
165 #define CMX3_CLK_MASK ((uint)0x0000ff00)
166
167 /* MII status/control serial interface.
168 */
169 #define PC_MDIO ((uint)0x00400000)
170 #define PC_MDCK ((uint)0x00200000)
171
172 /* A table of information for supporting FCCs. This does two things.
173 * First, we know how many FCCs we have and they are always externally
174 * numbered from zero. Second, it holds control register and I/O
175 * information that could be different among board designs.
176 */
177 typedef struct fcc_info {
178 uint fc_fccnum;
179 uint fc_cpmblock;
180 uint fc_cpmpage;
181 uint fc_proff;
182 uint fc_interrupt;
183 uint fc_trxclocks;
184 uint fc_clockroute;
185 uint fc_clockmask;
186 uint fc_mdio;
187 uint fc_mdck;
188 } fcc_info_t;
189
190 static fcc_info_t fcc_ports[] = {
191 #ifdef CONFIG_FCC1_ENET
192 { 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
193 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
194 PC_MDIO, PC_MDCK },
195 #endif
196 #ifdef CONFIG_FCC2_ENET
197 { 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
198 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
199 PC_MDIO, PC_MDCK },
200 #endif
201 #ifdef CONFIG_FCC3_ENET
202 { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
203 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
204 PC_MDIO, PC_MDCK },
205 #endif
206 };
207
208 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
209 * tx_bd_base always point to the base of the buffer descriptors. The
210 * cur_rx and cur_tx point to the currently available buffer.
211 * The dirty_tx tracks the current buffer that is being sent by the
212 * controller. The cur_tx and dirty_tx are equal under both completely
213 * empty and completely full conditions. The empty/ready indicator in
214 * the buffer descriptor determines the actual condition.
215 */
216 struct fcc_enet_private {
217 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
218 struct sk_buff* tx_skbuff[TX_RING_SIZE];
219 ushort skb_cur;
220 ushort skb_dirty;
221
222 /* CPM dual port RAM relative addresses.
223 */
224 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
225 cbd_t *tx_bd_base;
226 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
227 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
228 volatile fcc_t *fccp;
229 volatile fcc_enet_t *ep;
230 struct net_device_stats stats;
231 uint tx_full;
232 spinlock_t lock;
233 uint phy_address;
234 uint phy_type;
235 uint phy_duplex;
236 fcc_info_t *fip;
237 };
238
239 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
240 volatile immap_t *immap);
241 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
242 static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
243 volatile immap_t *immap);
244 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
245 volatile immap_t *immap);
246
247 /* MII processing. We keep this as simple as possible. Requests are
248 * placed on the list (if there is room). When the request is finished
249 * by the MII, an optional function may be called.
250 */
251 typedef struct mii_list {
252 uint mii_regval;
253 void (*mii_func)(uint val, struct net_device *dev);
254 struct mii_list *mii_next;
255 } mii_list_t;
256
257 #define NMII 20
258 mii_list_t mii_cmds[NMII];
259 mii_list_t *mii_free;
260 mii_list_t *mii_head;
261 mii_list_t *mii_tail;
262
263 static int phyaddr;
264 static uint phytype;
265
266 static int mii_queue(int request, void (*func)(uint, struct net_device *));
267 static void mii_startup_cmds(void);
268 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
269
270 /* Make MII read/write commands for the FCC.
271 */
272
273 #define mk_mii_phyaddr(ADDR) (0x60020000 | ((ADDR) << 23) | (2 << 18))
274
275 #define mk_mii_read(REG) (0x60020000 | ((phyaddr << 23) | \
276 (REG & 0x1f) << 18))
277
278 #define mk_mii_write(REG, VAL) (0x50020000 | ((phyaddr << 23) | \
279 (REG & 0x1f) << 18) | \
280 (VAL & 0xffff))
281
282
283 static int
284 fcc_enet_open(struct net_device *dev)
285 {
286 netif_start_queue(dev);
287 return 0; /* Always succeed */
288 }
289
290 static int
291 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
292 {
293 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
294 volatile cbd_t *bdp;
295
296
297 /* Fill in a Tx ring entry */
298 bdp = cep->cur_tx;
299
300 #ifndef final_version
301 if (bdp->cbd_sc & BD_ENET_TX_READY) {
302 /* Ooops. All transmit buffers are full. Bail out.
303 * This should not happen, since cep->tx_full should be set.
304 */
305 printk("%s: tx queue full!.\n", dev->name);
306 return 1;
307 }
308 #endif
309
310 /* Clear all of the status flags.
311 */
312 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
313
314 /* If the frame is short, tell CPM to pad it.
315 */
316 if (skb->len <= ETH_ZLEN)
317 bdp->cbd_sc |= BD_ENET_TX_PAD;
318 else
319 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
320
321 /* Set buffer length and buffer pointer.
322 */
323 bdp->cbd_datlen = skb->len;
324 bdp->cbd_bufaddr = __pa(skb->data);
325
326 /* Save skb pointer.
327 */
328 cep->tx_skbuff[cep->skb_cur] = skb;
329
330 cep->stats.tx_bytes += skb->len;
331 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
332
333 spin_lock_irq(&cep->lock);
334
335 /* Send it on its way. Tell CPM its ready, interrupt when done,
336 * its the last BD of the frame, and to put the CRC on the end.
337 */
338 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
339
340 #if 0
341 /* Errata says don't do this.
342 */
343 cep->fccp->fcc_ftodr = 0x8000;
344 #endif
345 dev->trans_start = jiffies;
346
347 /* If this was the last BD in the ring, start at the beginning again.
348 */
349 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
350 bdp = cep->tx_bd_base;
351 else
352 bdp++;
353
354 if (bdp->cbd_sc & BD_ENET_TX_READY) {
355 netif_stop_queue(dev);
356 cep->tx_full = 1;
357 }
358
359 cep->cur_tx = (cbd_t *)bdp;
360
361 spin_unlock_irq(&cep->lock);
362
363 return 0;
364 }
365
366
367 static void
368 fcc_enet_timeout(struct net_device *dev)
369 {
370 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
371
372 printk("%s: transmit timed out.\n", dev->name);
373 cep->stats.tx_errors++;
374 #ifndef final_version
375 {
376 int i;
377 cbd_t *bdp;
378 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
379 cep->cur_tx, cep->tx_full ? " (full)" : "",
380 cep->cur_rx);
381 bdp = cep->tx_bd_base;
382 printk(" Tx @base %p :\n", bdp);
383 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
384 printk("%04x %04x %08x\n",
385 bdp->cbd_sc,
386 bdp->cbd_datlen,
387 bdp->cbd_bufaddr);
388 bdp = cep->rx_bd_base;
389 printk(" Rx @base %p :\n", bdp);
390 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
391 printk("%04x %04x %08x\n",
392 bdp->cbd_sc,
393 bdp->cbd_datlen,
394 bdp->cbd_bufaddr);
395 }
396 #endif
397 if (!cep->tx_full)
398 netif_wake_queue(dev);
399 }
400
401 /* The interrupt handler.
402 */
403 static void
404 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
405 {
406 struct net_device *dev = dev_id;
407 volatile struct fcc_enet_private *cep;
408 volatile cbd_t *bdp;
409 ushort int_events;
410 int must_restart;
411
412 cep = (struct fcc_enet_private *)dev->priv;
413
414 /* Get the interrupt events that caused us to be here.
415 */
416 int_events = cep->fccp->fcc_fcce;
417 cep->fccp->fcc_fcce = int_events;
418 must_restart = 0;
419
420 /* Handle receive event in its own function.
421 */
422 if (int_events & FCC_ENET_RXF)
423 fcc_enet_rx(dev_id);
424
425 /* Check for a transmit error. The manual is a little unclear
426 * about this, so the debug code until I get it figured out. It
427 * appears that if TXE is set, then TXB is not set. However,
428 * if carrier sense is lost during frame transmission, the TXE
429 * bit is set, "and continues the buffer transmission normally."
430 * I don't know if "normally" implies TXB is set when the buffer
431 * descriptor is closed.....trial and error :-).
432 */
433
434 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
435 */
436 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
437 spin_lock(&cep->lock);
438 bdp = cep->dirty_tx;
439 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
440 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
441 break;
442
443 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
444 cep->stats.tx_heartbeat_errors++;
445 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
446 cep->stats.tx_window_errors++;
447 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
448 cep->stats.tx_aborted_errors++;
449 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
450 cep->stats.tx_fifo_errors++;
451 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
452 cep->stats.tx_carrier_errors++;
453
454
455 /* No heartbeat or Lost carrier are not really bad errors.
456 * The others require a restart transmit command.
457 */
458 if (bdp->cbd_sc &
459 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
460 must_restart = 1;
461 cep->stats.tx_errors++;
462 }
463
464 cep->stats.tx_packets++;
465
466 /* Deferred means some collisions occurred during transmit,
467 * but we eventually sent the packet OK.
468 */
469 if (bdp->cbd_sc & BD_ENET_TX_DEF)
470 cep->stats.collisions++;
471
472 /* Free the sk buffer associated with this last transmit.
473 */
474 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
475 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
476
477 /* Update pointer to next buffer descriptor to be transmitted.
478 */
479 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
480 bdp = cep->tx_bd_base;
481 else
482 bdp++;
483
484 /* I don't know if we can be held off from processing these
485 * interrupts for more than one frame time. I really hope
486 * not. In such a case, we would now want to check the
487 * currently available BD (cur_tx) and determine if any
488 * buffers between the dirty_tx and cur_tx have also been
489 * sent. We would want to process anything in between that
490 * does not have BD_ENET_TX_READY set.
491 */
492
493 /* Since we have freed up a buffer, the ring is no longer
494 * full.
495 */
496 if (cep->tx_full) {
497 cep->tx_full = 0;
498 if (netif_queue_stopped(dev)) {
499 netif_wake_queue(dev);
500 }
501 }
502
503 cep->dirty_tx = (cbd_t *)bdp;
504 }
505
506 if (must_restart) {
507 volatile cpm8260_t *cp;
508
509 /* Some transmit errors cause the transmitter to shut
510 * down. We now issue a restart transmit. Since the
511 * errors close the BD and update the pointers, the restart
512 * _should_ pick up without having to reset any of our
513 * pointers either.
514 */
515
516 cp = cpmp;
517 cp->cp_cpcr =
518 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
519 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
520 while (cp->cp_cpcr & CPM_CR_FLG);
521 }
522 spin_unlock(&cep->lock);
523 }
524
525 /* Check for receive busy, i.e. packets coming but no place to
526 * put them.
527 */
528 if (int_events & FCC_ENET_BSY) {
529 cep->stats.rx_dropped++;
530 }
531 return;
532 }
533
534 /* During a receive, the cur_rx points to the current incoming buffer.
535 * When we update through the ring, if the next incoming buffer has
536 * not been given to the system, we just set the empty indicator,
537 * effectively tossing the packet.
538 */
539 static int
540 fcc_enet_rx(struct net_device *dev)
541 {
542 struct fcc_enet_private *cep;
543 volatile cbd_t *bdp;
544 struct sk_buff *skb;
545 ushort pkt_len;
546
547 cep = (struct fcc_enet_private *)dev->priv;
548
549 /* First, grab all of the stats for the incoming packet.
550 * These get messed up if we get called due to a busy condition.
551 */
552 bdp = cep->cur_rx;
553
554 for (;;) {
555 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
556 break;
557
558 #ifndef final_version
559 /* Since we have allocated space to hold a complete frame, both
560 * the first and last indicators should be set.
561 */
562 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
563 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
564 printk("CPM ENET: rcv is not first+last\n");
565 #endif
566
567 /* Frame too long or too short.
568 */
569 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
570 cep->stats.rx_length_errors++;
571 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
572 cep->stats.rx_frame_errors++;
573 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
574 cep->stats.rx_crc_errors++;
575 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
576 cep->stats.rx_crc_errors++;
577
578 /* Report late collisions as a frame error.
579 * On this error, the BD is closed, but we don't know what we
580 * have in the buffer. So, just drop this frame on the floor.
581 */
582 if (bdp->cbd_sc & BD_ENET_RX_CL) {
583 cep->stats.rx_frame_errors++;
584 }
585 else {
586
587 /* Process the incoming frame.
588 */
589 cep->stats.rx_packets++;
590 pkt_len = bdp->cbd_datlen;
591 cep->stats.rx_bytes += pkt_len;
592
593 /* This does 16 byte alignment, much more than we need.
594 * The packet length includes FCS, but we don't want to
595 * include that when passing upstream as it messes up
596 * bridging applications.
597 */
598 skb = dev_alloc_skb(pkt_len-4);
599
600 if (skb == NULL) {
601 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
602 cep->stats.rx_dropped++;
603 }
604 else {
605 skb->dev = dev;
606 skb_put(skb,pkt_len-4); /* Make room */
607 eth_copy_and_sum(skb,
608 (unsigned char *)__va(bdp->cbd_bufaddr),
609 pkt_len-4, 0);
610 skb->protocol=eth_type_trans(skb,dev);
611 netif_rx(skb);
612 }
613 }
614
615 /* Clear the status flags for this buffer.
616 */
617 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
618
619 /* Mark the buffer empty.
620 */
621 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
622
623 /* Update BD pointer to next entry.
624 */
625 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
626 bdp = cep->rx_bd_base;
627 else
628 bdp++;
629
630 }
631 cep->cur_rx = (cbd_t *)bdp;
632
633 return 0;
634 }
635
636 static int
637 fcc_enet_close(struct net_device *dev)
638 {
639 /* Don't know what to do yet.
640 */
641 netif_stop_queue(dev);
642
643 return 0;
644 }
645
646 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
647 {
648 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
649
650 return &cep->stats;
651 }
652
653 /* The MII is simulated from the 8xx FEC implementation. The FCC
654 * is not responsible for the MII control/status interface.
655 */
656 static void
657 fcc_enet_mii(struct net_device *dev)
658 {
659 struct fcc_enet_private *fep;
660 mii_list_t *mip;
661 uint mii_reg;
662
663 fep = (struct fcc_enet_private *)dev->priv;
664 #if 0
665 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
666 mii_reg = ep->fec_mii_data;
667 #endif
668
669 if ((mip = mii_head) == NULL) {
670 printk("MII and no head!\n");
671 return;
672 }
673
674 if (mip->mii_func != NULL)
675 (*(mip->mii_func))(mii_reg, dev);
676
677 mii_head = mip->mii_next;
678 mip->mii_next = mii_free;
679 mii_free = mip;
680
681 #if 0
682 if ((mip = mii_head) != NULL)
683 ep->fec_mii_data = mip->mii_regval;
684 #endif
685 }
686
687 static int
688 mii_queue(int regval, void (*func)(uint, struct net_device *))
689 {
690 unsigned long flags;
691 mii_list_t *mip;
692 int retval;
693
694 retval = 0;
695
696 save_flags(flags);
697 cli();
698
699 if ((mip = mii_free) != NULL) {
700 mii_free = mip->mii_next;
701 mip->mii_regval = regval;
702 mip->mii_func = func;
703 mip->mii_next = NULL;
704 if (mii_head) {
705 mii_tail->mii_next = mip;
706 mii_tail = mip;
707 }
708 else {
709 mii_head = mii_tail = mip;
710 #if 0
711 (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
712 #endif
713 }
714 }
715 else {
716 retval = 1;
717 }
718
719 restore_flags(flags);
720
721 return(retval);
722 }
723
724 static volatile uint full_duplex;
725
726 static void
727 mii_status(uint mii_reg, struct net_device *dev)
728 {
729 volatile uint prev_duplex;
730
731 if (((mii_reg >> 18) & 0x1f) == 1) {
732 /* status register.
733 */
734 printk("fec: ");
735 if (mii_reg & 0x0004)
736 printk("link up");
737 else
738 printk("link down");
739
740 if (mii_reg & 0x0010)
741 printk(",remote fault");
742 if (mii_reg & 0x0020)
743 printk(",auto complete");
744 printk("\n");
745 }
746 if (((mii_reg >> 18) & 0x1f) == 0x14) {
747 /* Extended chip status register.
748 */
749 prev_duplex = full_duplex;
750 printk("fec: ");
751 if (mii_reg & 0x0800)
752 printk("100 Mbps");
753 else
754 printk("10 Mbps");
755
756 if (mii_reg & 0x1000) {
757 printk(", Full-Duplex\n");
758 full_duplex = 1;
759 }
760 else {
761 printk(", Half-Duplex\n");
762 full_duplex = 0;
763 }
764 #if 0
765 if (prev_duplex != full_duplex)
766 restart_fec(dev);
767 #endif
768 }
769 if (((mii_reg >> 18) & 0x1f) == 31) {
770 /* QS6612 PHY Control/Status.
771 * OK, now we have it all, so figure out what is going on.
772 */
773 prev_duplex = full_duplex;
774 printk("fec: ");
775
776 mii_reg = (mii_reg >> 2) & 7;
777
778 if (mii_reg & 1)
779 printk("10 Mbps");
780 else
781 printk("100 Mbps");
782
783 if (mii_reg > 4) {
784 printk(", Full-Duplex\n");
785 full_duplex = 1;
786 }
787 else {
788 printk(", Half-Duplex\n");
789 full_duplex = 0;
790 }
791
792 #if 0
793 if (prev_duplex != full_duplex)
794 restart_fec(dev);
795 #endif
796 }
797 }
798
799 static uint phyno;
800
801 static void
802 mii_discover_phy3(uint mii_reg, struct net_device *dev)
803 {
804 phytype <<= 16;
805 phytype |= (mii_reg & 0xffff);
806 printk("fec: Phy @ 0x%x, type 0x%08x\n", phyno, phytype);
807 mii_startup_cmds();
808 }
809
810 static void
811 mii_discover_phy(uint mii_reg, struct net_device *dev)
812 {
813 if (phyno < 32) {
814 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
815 phyaddr = phyno;
816 mii_queue(mk_mii_read(3), mii_discover_phy3);
817 }
818 else {
819 phyno++;
820 mii_queue(mk_mii_phyaddr(phyno), mii_discover_phy);
821 }
822 }
823 else {
824 printk("FEC: No PHY device found.\n");
825 }
826 }
827
828 static void
829 mii_discover_phy_poll(fcc_info_t *fip)
830 {
831 uint rv;
832 int i;
833
834 for (i=0; i<32; i++) {
835 rv = mii_send_receive(fip, mk_mii_phyaddr(i));
836 if ((phytype = (rv & 0xffff)) != 0xffff) {
837 phyaddr = i;
838 rv = mii_send_receive(fip, mk_mii_read(3));
839 phytype <<= 16;
840 phytype |= (rv & 0xffff);
841 printk("fec: Phy @ 0x%x, type 0x%08x\n", phyaddr, phytype);
842 }
843 }
844 }
845
846 static void
847 mii_startup_cmds(void)
848 {
849
850 #if 1
851 /* Level One PHY.
852 */
853
854 /* Read status registers to clear any pending interrupt.
855 */
856 mii_queue(mk_mii_read(1), mii_status);
857 mii_queue(mk_mii_read(18), mii_status);
858
859 /* Read extended chip status register.
860 */
861 mii_queue(mk_mii_read(0x14), mii_status);
862
863 /* Set default operation of 100-TX....for some reason
864 * some of these bits are set on power up, which is wrong.
865 */
866 mii_queue(mk_mii_write(0x13, 0), NULL);
867
868 /* Enable Link status change interrupts.
869 */
870 mii_queue(mk_mii_write(0x11, 0x0002), NULL);
871
872 /* Don't advertize Full duplex.
873 mii_queue(mk_mii_write(0x04, 0x0021), NULL);
874 */
875 #endif
876
877 }
878
879 /* This supports the mii_link interrupt below.
880 * We should get called three times. Once for register 1, once for
881 * register 18, and once for register 20.
882 */
883 static uint mii_saved_reg1;
884
885 static void
886 mii_relink(uint mii_reg, struct net_device *dev)
887 {
888 volatile uint prev_duplex;
889 unsigned long flags;
890
891 if (((mii_reg >> 18) & 0x1f) == 1) {
892 /* Just save the status register and get out.
893 */
894 mii_saved_reg1 = mii_reg;
895 return;
896 }
897 if (((mii_reg >> 18) & 0x1f) == 18) {
898 /* Not much here, but has to be read to clear the
899 * interrupt condition.
900 */
901 if ((mii_reg & 0x8000) == 0)
902 printk("fec: re-link and no IRQ?\n");
903 if ((mii_reg & 0x4000) == 0)
904 printk("fec: no PHY power?\n");
905 }
906 if (((mii_reg >> 18) & 0x1f) == 20) {
907 /* Extended chip status register.
908 * OK, now we have it all, so figure out what is going on.
909 */
910 prev_duplex = full_duplex;
911 printk("fec: ");
912 if (mii_saved_reg1 & 0x0004)
913 printk("link up");
914 else
915 printk("link down");
916
917 if (mii_saved_reg1 & 0x0010)
918 printk(", remote fault");
919 if (mii_saved_reg1 & 0x0020)
920 printk(", auto complete");
921
922 if (mii_reg & 0x0800)
923 printk(", 100 Mbps");
924 else
925 printk(", 10 Mbps");
926
927 if (mii_reg & 0x1000) {
928 printk(", Full-Duplex\n");
929 full_duplex = 1;
930 }
931 else {
932 printk(", Half-Duplex\n");
933 full_duplex = 0;
934 }
935 if (prev_duplex != full_duplex) {
936 save_flags(flags);
937 cli();
938 #if 0
939 restart_fec(dev);
940 #endif
941 restore_flags(flags);
942 }
943 }
944 if (((mii_reg >> 18) & 0x1f) == 31) {
945 /* QS6612 PHY Control/Status.
946 * OK, now we have it all, so figure out what is going on.
947 */
948 prev_duplex = full_duplex;
949 printk("fec: ");
950 if (mii_saved_reg1 & 0x0004)
951 printk("link up");
952 else
953 printk("link down");
954
955 if (mii_saved_reg1 & 0x0010)
956 printk(", remote fault");
957 if (mii_saved_reg1 & 0x0020)
958 printk(", auto complete");
959
960 mii_reg = (mii_reg >> 2) & 7;
961
962 if (mii_reg & 1)
963 printk(", 10 Mbps");
964 else
965 printk(", 100 Mbps");
966
967 if (mii_reg > 4) {
968 printk(", Full-Duplex\n");
969 full_duplex = 1;
970 }
971 else {
972 printk(", Half-Duplex\n");
973 full_duplex = 0;
974 }
975
976 #if 0
977 if (prev_duplex != full_duplex) {
978 save_flags(flags);
979 cli();
980 restart_fec(dev);
981 restore_flags(flags);
982 }
983 #endif
984 }
985 }
986
987 /* Set or clear the multicast filter for this adaptor.
988 * Skeleton taken from sunlance driver.
989 * The CPM Ethernet implementation allows Multicast as well as individual
990 * MAC address filtering. Some of the drivers check to make sure it is
991 * a group multicast address, and discard those that are not. I guess I
992 * will do the same for now, but just remove the test if you want
993 * individual filtering as well (do the upper net layers want or support
994 * this kind of feature?).
995 */
996 static void
997 set_multicast_list(struct net_device *dev)
998 {
999 struct fcc_enet_private *cep;
1000 struct dev_mc_list *dmi;
1001 u_char *mcptr, *tdptr;
1002 volatile fcc_enet_t *ep;
1003 int i, j;
1004
1005 cep = (struct fcc_enet_private *)dev->priv;
1006
1007 return;
1008 /* Get pointer to FCC area in parameter RAM.
1009 */
1010 ep = (fcc_enet_t *)dev->base_addr;
1011
1012 if (dev->flags&IFF_PROMISC) {
1013
1014 /* Log any net taps. */
1015 printk("%s: Promiscuous mode enabled.\n", dev->name);
1016 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1017 } else {
1018
1019 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1020
1021 if (dev->flags & IFF_ALLMULTI) {
1022 /* Catch all multicast addresses, so set the
1023 * filter to all 1's.
1024 */
1025 ep->fen_gaddrh = 0xffffffff;
1026 ep->fen_gaddrl = 0xffffffff;
1027 }
1028 else {
1029 /* Clear filter and add the addresses in the list.
1030 */
1031 ep->fen_gaddrh = 0;
1032 ep->fen_gaddrl = 0;
1033
1034 dmi = dev->mc_list;
1035
1036 for (i=0; i<dev->mc_count; i++) {
1037
1038 /* Only support group multicast for now.
1039 */
1040 if (!(dmi->dmi_addr[0] & 1))
1041 continue;
1042
1043 /* The address in dmi_addr is LSB first,
1044 * and taddr is MSB first. We have to
1045 * copy bytes MSB first from dmi_addr.
1046 */
1047 mcptr = (u_char *)dmi->dmi_addr + 5;
1048 tdptr = (u_char *)&ep->fen_taddrh;
1049 for (j=0; j<6; j++)
1050 *tdptr++ = *mcptr--;
1051
1052 /* Ask CPM to run CRC and set bit in
1053 * filter mask.
1054 */
1055 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1056 cep->fip->fc_cpmblock, 0x0c,
1057 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1058 udelay(10);
1059 while (cpmp->cp_cpcr & CPM_CR_FLG);
1060 }
1061 }
1062 }
1063 }
1064
1065 /* Initialize the CPM Ethernet on FCC.
1066 */
1067 int __init fec_enet_init(void)
1068 {
1069 struct net_device *dev;
1070 struct fcc_enet_private *cep;
1071 fcc_info_t *fip;
1072 int i, np;
1073 volatile immap_t *immap;
1074 volatile iop8260_t *io;
1075
1076 immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
1077 io = &immap->im_ioport;
1078
1079 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1080 fip = fcc_ports;
1081
1082 while (np-- > 0) {
1083
1084 /* Allocate some private information.
1085 */
1086 cep = (struct fcc_enet_private *)
1087 kmalloc(sizeof(*cep), GFP_KERNEL);
1088 if (cep == NULL)
1089 return -ENOMEM;
1090
1091 __clear_user(cep,sizeof(*cep));
1092 spin_lock_init(&cep->lock);
1093 cep->fip = fip;
1094
1095 /* Create an Ethernet device instance.
1096 */
1097 dev = init_etherdev(0, 0);
1098 dev->priv = cep;
1099
1100 init_fcc_shutdown(fip, cep, immap);
1101 init_fcc_ioports(fip, io, immap);
1102 init_fcc_param(fip, dev, immap);
1103
1104 dev->base_addr = (unsigned long)(cep->ep);
1105
1106 /* The CPM Ethernet specific entries in the device
1107 * structure.
1108 */
1109 dev->open = fcc_enet_open;
1110 dev->hard_start_xmit = fcc_enet_start_xmit;
1111 dev->tx_timeout = fcc_enet_timeout;
1112 dev->watchdog_timeo = TX_TIMEOUT;
1113 dev->stop = fcc_enet_close;
1114 dev->get_stats = fcc_enet_get_stats;
1115 dev->set_multicast_list = set_multicast_list;
1116
1117 init_fcc_startup(fip, dev);
1118
1119 printk("%s: FCC ENET Version 0.2, ", dev->name);
1120 for (i=0; i<5; i++)
1121 printk("%02x:", dev->dev_addr[i]);
1122 printk("%02x\n", dev->dev_addr[5]);
1123
1124 /* This is just a hack for now that works only on the EST
1125 * board, or anything else that has MDIO/CK configured.
1126 * It is mainly to test the MII software clocking.
1127 */
1128 mii_discover_phy_poll(fip);
1129
1130 fip++;
1131 }
1132
1133 return 0;
1134 }
1135
1136 /* Make sure the device is shut down during initialization.
1137 */
1138 static void __init
1139 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1140 volatile immap_t *immap)
1141 {
1142 volatile fcc_enet_t *ep;
1143 volatile fcc_t *fccp;
1144
1145 /* Get pointer to FCC area in parameter RAM.
1146 */
1147 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1148
1149 /* And another to the FCC register area.
1150 */
1151 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1152 cep->fccp = fccp; /* Keep the pointers handy */
1153 cep->ep = ep;
1154
1155 /* Disable receive and transmit in case someone left it running.
1156 */
1157 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1158 }
1159
1160 /* Initialize the I/O pins for the FCC Ethernet.
1161 */
1162 static void __init
1163 init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
1164 volatile immap_t *immap)
1165 {
1166
1167 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1168 */
1169 if (fip->fc_proff == PROFF_FCC1) {
1170 /* Configure port A and C pins for FCC1 Ethernet.
1171 */
1172 io->iop_pdira &= ~PA1_DIRA0;
1173 io->iop_pdira |= PA1_DIRA1;
1174 io->iop_psora &= ~PA1_PSORA0;
1175 io->iop_psora |= PA1_PSORA1;
1176 io->iop_ppara |= (PA1_DIRA0 | PA1_DIRA1);
1177 }
1178 if (fip->fc_proff == PROFF_FCC2) {
1179 /* Configure port B and C pins for FCC Ethernet.
1180 */
1181 io->iop_pdirb &= ~PB2_DIRB0;
1182 io->iop_pdirb |= PB2_DIRB1;
1183 io->iop_psorb &= ~PB2_PSORB0;
1184 io->iop_psorb |= PB2_PSORB1;
1185 io->iop_pparb |= (PB2_DIRB0 | PB2_DIRB1);
1186 }
1187 if (fip->fc_proff == PROFF_FCC3) {
1188 /* Configure port B and C pins for FCC Ethernet.
1189 */
1190 io->iop_pdirb &= ~PB3_DIRB0;
1191 io->iop_pdirb |= PB3_DIRB1;
1192 io->iop_psorb &= ~PB3_PSORB0;
1193 io->iop_psorb |= PB3_PSORB1;
1194 io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);
1195 }
1196
1197 /* Port C has clocks......
1198 */
1199 io->iop_psorc &= ~(fip->fc_trxclocks);
1200 io->iop_pdirc &= ~(fip->fc_trxclocks);
1201 io->iop_pparc |= fip->fc_trxclocks;
1202
1203 /* ....and the MII serial clock/data.
1204 */
1205 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1206 io->iop_podrc |= fip->fc_mdio;
1207 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1208 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1209
1210 /* Configure Serial Interface clock routing.
1211 * First, clear all FCC bits to zero,
1212 * then set the ones we want.
1213 */
1214 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1215 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1216 }
1217
1218 static void __init
1219 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1220 volatile immap_t *immap)
1221 {
1222 unsigned char *eap;
1223 unsigned long mem_addr;
1224 bd_t *bd;
1225 int i, j;
1226 struct fcc_enet_private *cep;
1227 volatile fcc_enet_t *ep;
1228 volatile cbd_t *bdp;
1229 volatile cpm8260_t *cp;
1230
1231 cep = (struct fcc_enet_private *)(dev->priv);
1232 ep = cep->ep;
1233 cp = cpmp;
1234
1235 bd = (bd_t *)__res;
1236
1237 /* Zero the whole thing.....I must have missed some individually.
1238 * It works when I do this.
1239 */
1240 memset((char *)ep, 0, sizeof(fcc_enet_t));
1241
1242 /* Allocate space for the buffer descriptors in the DP ram.
1243 * These are relative offsets in the DP ram address space.
1244 * Initialize base addresses for the buffer descriptors.
1245 */
1246 #if 0
1247 /* I really want to do this, but for some reason it doesn't
1248 * work with the data cache enabled, so I allocate from the
1249 * main memory instead.
1250 */
1251 i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1252 ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
1253 cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1254
1255 i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1256 ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
1257 cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1258 #else
1259 cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1260 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1261 cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1262 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1263 #endif
1264
1265 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1266 cep->cur_rx = cep->rx_bd_base;
1267
1268 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1269 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1270
1271 /* Set maximum bytes per receive buffer.
1272 * It must be a multiple of 32.
1273 */
1274 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1275
1276 /* Allocate space in the reserved FCC area of DPRAM for the
1277 * internal buffers. No one uses this space (yet), so we
1278 * can do this. Later, we will add resource management for
1279 * this area.
1280 */
1281 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1282 ep->fen_genfcc.fcc_riptr = mem_addr;
1283 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1284 ep->fen_padptr = mem_addr+64;
1285 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1286
1287 ep->fen_genfcc.fcc_rbptr = 0;
1288 ep->fen_genfcc.fcc_tbptr = 0;
1289 ep->fen_genfcc.fcc_rcrc = 0;
1290 ep->fen_genfcc.fcc_tcrc = 0;
1291 ep->fen_genfcc.fcc_res1 = 0;
1292 ep->fen_genfcc.fcc_res2 = 0;
1293
1294 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1295
1296 /* Set CRC preset and mask.
1297 */
1298 ep->fen_cmask = 0xdebb20e3;
1299 ep->fen_cpres = 0xffffffff;
1300
1301 ep->fen_crcec = 0; /* CRC Error counter */
1302 ep->fen_alec = 0; /* alignment error counter */
1303 ep->fen_disfc = 0; /* discard frame counter */
1304 ep->fen_retlim = 15; /* Retry limit threshold */
1305 ep->fen_pper = 0; /* Normal persistence */
1306
1307 /* Clear hash filter tables.
1308 */
1309 ep->fen_gaddrh = 0;
1310 ep->fen_gaddrl = 0;
1311 ep->fen_iaddrh = 0;
1312 ep->fen_iaddrl = 0;
1313
1314 /* Clear the Out-of-sequence TxBD.
1315 */
1316 ep->fen_tfcstat = 0;
1317 ep->fen_tfclen = 0;
1318 ep->fen_tfcptr = 0;
1319
1320 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1321 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1322
1323 /* Set Ethernet station address.
1324 *
1325 * This is supplied in the board information structure, so we
1326 * copy that into the controller.
1327 * So, far we have only been given one Ethernet address. We make
1328 * it unique by setting a few bits in the upper byte of the
1329 * non-static part of the address.
1330 */
1331 eap = (unsigned char *)&(ep->fen_paddrh);
1332 for (i=5; i>=0; i--) {
1333 if (i == 3) {
1334 dev->dev_addr[i] = bd->bi_enetaddr[i];
1335 dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum));
1336 *eap++ = dev->dev_addr[i];
1337 }
1338 else {
1339 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1340 }
1341 }
1342
1343 ep->fen_taddrh = 0;
1344 ep->fen_taddrm = 0;
1345 ep->fen_taddrl = 0;
1346
1347 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
1348 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
1349
1350 /* Clear stat counters, in case we ever enable RMON.
1351 */
1352 ep->fen_octc = 0;
1353 ep->fen_colc = 0;
1354 ep->fen_broc = 0;
1355 ep->fen_mulc = 0;
1356 ep->fen_uspc = 0;
1357 ep->fen_frgc = 0;
1358 ep->fen_ospc = 0;
1359 ep->fen_jbrc = 0;
1360 ep->fen_p64c = 0;
1361 ep->fen_p65c = 0;
1362 ep->fen_p128c = 0;
1363 ep->fen_p256c = 0;
1364 ep->fen_p512c = 0;
1365 ep->fen_p1024c = 0;
1366
1367 ep->fen_rfthr = 0; /* Suggested by manual */
1368 ep->fen_rfcnt = 0;
1369 ep->fen_cftype = 0;
1370
1371 /* Now allocate the host memory pages and initialize the
1372 * buffer descriptors.
1373 */
1374 bdp = cep->tx_bd_base;
1375 for (i=0; i<TX_RING_SIZE; i++) {
1376
1377 /* Initialize the BD for every fragment in the page.
1378 */
1379 bdp->cbd_sc = 0;
1380 bdp->cbd_datlen = 0;
1381 bdp->cbd_bufaddr = 0;
1382 bdp++;
1383 }
1384
1385 /* Set the last buffer to wrap.
1386 */
1387 bdp--;
1388 bdp->cbd_sc |= BD_SC_WRAP;
1389
1390 bdp = cep->rx_bd_base;
1391 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
1392
1393 /* Allocate a page.
1394 */
1395 mem_addr = __get_free_page(GFP_KERNEL);
1396
1397 /* Initialize the BD for every fragment in the page.
1398 */
1399 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
1400 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
1401 bdp->cbd_datlen = 0;
1402 bdp->cbd_bufaddr = __pa(mem_addr);
1403 mem_addr += FCC_ENET_RX_FRSIZE;
1404 bdp++;
1405 }
1406 }
1407
1408 /* Set the last buffer to wrap.
1409 */
1410 bdp--;
1411 bdp->cbd_sc |= BD_SC_WRAP;
1412
1413 /* Let's re-initialize the channel now. We have to do it later
1414 * than the manual describes because we have just now finished
1415 * the BD initialization.
1416 */
1417 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
1418 CPM_CR_INIT_TRX) | CPM_CR_FLG;
1419 while (cp->cp_cpcr & CPM_CR_FLG);
1420
1421 cep->skb_cur = cep->skb_dirty = 0;
1422 }
1423
1424 /* Let 'er rip.
1425 */
1426 static void __init
1427 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
1428 {
1429 volatile fcc_t *fccp;
1430 struct fcc_enet_private *cep;
1431
1432 cep = (struct fcc_enet_private *)(dev->priv);
1433 fccp = cep->fccp;
1434
1435 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
1436
1437 /* Enable interrupts for transmit error, complete frame
1438 * received, and any transmit buffer we have also set the
1439 * interrupt flag.
1440 */
1441 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
1442
1443 /* Install our interrupt handler.
1444 */
1445 if (request_8xxirq(fip->fc_interrupt, fcc_enet_interrupt, 0,
1446 "fenet", dev) < 0)
1447 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
1448
1449 /* Set GFMR to enable Ethernet operating mode.
1450 */
1451 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
1452
1453 /* Set sync/delimiters.
1454 */
1455 fccp->fcc_fdsr = 0xd555;
1456
1457 /* Set protocol specific processing mode for Ethernet.
1458 * This has to be adjusted for Full Duplex operation after we can
1459 * determine how to detect that.
1460 */
1461 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
1462
1463 /* And last, enable the transmit and receive processing.
1464 */
1465 fccp->fcc_gfmr |= (FCC_GFMR_ENR | FCC_GFMR_ENT);
1466 }
1467
1468 /* MII command/status interface.
1469 * I'm not going to describe all of the details. You can find the
1470 * protocol definition in many other places, including the data sheet
1471 * of most PHY parts.
1472 * I wonder what "they" were thinking (maybe weren't) when they leave
1473 * the I2C in the CPM but I have to toggle these bits......
1474 */
1475 static uint
1476 mii_send_receive(fcc_info_t *fip, uint cmd)
1477 {
1478 unsigned long flags;
1479 uint retval;
1480 int read_op, i;
1481 volatile immap_t *immap;
1482 volatile iop8260_t *io;
1483
1484 immap = (immap_t *)IMAP_ADDR;
1485 io = &immap->im_ioport;
1486
1487 /* When we get here, both clock and data are high, outputs.
1488 * Output is open drain.
1489 * Data transitions on high->low clock, is valid on low->high clock.
1490 * Spec says edge transitions no closer than 160 nSec, minimum clock
1491 * cycle 400 nSec. I could only manage about 500 nSec edges with
1492 * an XOR loop, so I won't worry about delays yet.
1493 * I disable interrupts during bit flipping to ensure atomic
1494 * updates of the registers. I do lots of interrupt disable/enable
1495 * to ensure we don't hang out too long with interrupts disabled.
1496 */
1497
1498 /* First, crank out 32 1-bits as preamble.
1499 * This is 64 transitions to clock the bits, with clock/data
1500 * left high.
1501 */
1502 save_flags(flags);
1503 cli();
1504 for (i=0; i<64; i++) {
1505 io->iop_pdatc ^= fip->fc_mdck;
1506 udelay(0);
1507 }
1508 restore_flags(flags);
1509
1510 read_op = ((cmd & 0xf0000000) == 0x60000000);
1511
1512 /* We return the command word on a write op, or the command portion
1513 * plus the new data on a read op. This is what the 8xx FEC does,
1514 * and it allows the functions to simply look at the returned value
1515 * and know the PHY/register as well.
1516 */
1517 if (read_op)
1518 retval = cmd;
1519 else
1520 retval = (cmd >> 16);
1521
1522 /* Clock out the first 16 MS bits of the command.
1523 */
1524 save_flags(flags);
1525 cli();
1526 for (i=0; i<16; i++) {
1527 io->iop_pdatc &= ~(fip->fc_mdck);
1528 if (cmd & 0x80000000)
1529 io->iop_pdatc |= fip->fc_mdio;
1530 else
1531 io->iop_pdatc &= ~(fip->fc_mdio);
1532 cmd <<= 1;
1533 io->iop_pdatc |= fip->fc_mdck;
1534 udelay(0);
1535 }
1536
1537 /* Do the turn-around. If read op, we make the IO and input.
1538 * If write op, do the 1/0 thing.
1539 */
1540 io->iop_pdatc &= ~(fip->fc_mdck);
1541 if (read_op)
1542 io->iop_pdirc &= ~(fip->fc_mdio);
1543 else
1544 io->iop_pdatc |= fip->fc_mdio;
1545 io->iop_pdatc |= fip->fc_mdck;
1546
1547 /* I do this mainly to get just a little delay.
1548 */
1549 restore_flags(flags);
1550 save_flags(flags);
1551 cli();
1552 io->iop_pdatc &= ~(fip->fc_mdck);
1553 io->iop_pdirc &= ~(fip->fc_mdio);
1554 io->iop_pdatc |= fip->fc_mdck;
1555
1556 restore_flags(flags);
1557 save_flags(flags);
1558 cli();
1559
1560 /* For read, clock in 16 bits. For write, clock out
1561 * rest of command.
1562 */
1563 if (read_op) {
1564 io->iop_pdatc &= ~(fip->fc_mdck);
1565 udelay(0);
1566 for (i=0; i<16; i++) {
1567 io->iop_pdatc |= fip->fc_mdck;
1568 udelay(0);
1569 retval <<= 1;
1570 if (io->iop_pdatc & fip->fc_mdio)
1571 retval |= 1;
1572 io->iop_pdatc &= ~(fip->fc_mdck);
1573 udelay(0);
1574 }
1575 }
1576 else {
1577 for (i=0; i<16; i++) {
1578 io->iop_pdatc &= ~(fip->fc_mdck);
1579 if (cmd & 0x80000000)
1580 io->iop_pdatc |= fip->fc_mdio;
1581 else
1582 io->iop_pdatc &= ~(fip->fc_mdio);
1583 cmd <<= 1;
1584 io->iop_pdatc |= fip->fc_mdck;
1585 udelay(0);
1586 }
1587 io->iop_pdatc &= ~(fip->fc_mdck);
1588 }
1589 restore_flags(flags);
1590
1591 /* Some diagrams show two 1 bits for "idle". I don't know if
1592 * this is really necessary or if it was just to indicate nothing
1593 * is going to happen for a while.
1594 * Make the data pin an output, set the data high, and clock it.
1595 */
1596 save_flags(flags);
1597 cli();
1598 io->iop_pdatc |= fip->fc_mdio;
1599 io->iop_pdirc |= fip->fc_mdio;
1600 for (i=0; i<3; i++)
1601 io->iop_pdatc ^= fip->fc_mdck;
1602 restore_flags(flags);
1603
1604 /* We exit with the same conditions as entry.
1605 */
1606 return(retval);
1607 }
1608