File: /usr/src/linux/arch/ppc/8xx_io/commproc.h
1 /*
2 * BK Id: SCCS/s.commproc.h 1.13 06/15/01 13:00:20 paulus
3 */
4
5 /*
6 * MPC8xx Communication Processor Module.
7 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
8 *
9 * This file contains structures and information for the communication
10 * processor channels. Some CPM control and status is available
11 * throught the MPC8xx internal memory map. See immap.h for details.
12 * This file only contains what I need for the moment, not the total
13 * CPM capabilities. I (or someone else) will add definitions as they
14 * are needed. -- Dan
15 *
16 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
17 * bytes of the DP RAM and relocates the I2C parameter area to the
18 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
19 * or other use.
20 */
21 #ifndef __CPM_8XX__
22 #define __CPM_8XX__
23
24 #include <linux/config.h>
25 #include <asm/8xx_immap.h>
26
27 /* CPM Command register.
28 */
29 #define CPM_CR_RST ((ushort)0x8000)
30 #define CPM_CR_OPCODE ((ushort)0x0f00)
31 #define CPM_CR_CHAN ((ushort)0x00f0)
32 #define CPM_CR_FLG ((ushort)0x0001)
33
34 /* Some commands (there are more...later)
35 */
36 #define CPM_CR_INIT_TRX ((ushort)0x0000)
37 #define CPM_CR_INIT_RX ((ushort)0x0001)
38 #define CPM_CR_INIT_TX ((ushort)0x0002)
39 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
40 #define CPM_CR_STOP_TX ((ushort)0x0004)
41 #define CPM_CR_RESTART_TX ((ushort)0x0006)
42 #define CPM_CR_SET_GADDR ((ushort)0x0008)
43
44 /* Channel numbers.
45 */
46 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
47 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
48 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
49 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
50 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
51 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
52 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
53 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
54
55 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
56
57 /* The dual ported RAM is multi-functional. Some areas can be (and are
58 * being) used for microcode. There is an area that can only be used
59 * as data ram for buffer descriptors, which is all we use right now.
60 * Currently the first 512 and last 256 bytes are used for microcode.
61 */
62 #define CPM_DATAONLY_BASE ((uint)0x0800)
63 #define CPM_DATAONLY_SIZE ((uint)0x0700)
64 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
65
66 /* Export the base address of the communication processor registers
67 * and dual port ram.
68 */
69 extern cpm8xx_t *cpmp; /* Pointer to comm processor */
70 uint m8xx_cpm_dpalloc(uint size);
71 uint m8xx_cpm_hostalloc(uint size);
72 void m8xx_cpm_setbrg(uint brg, uint rate);
73
74 /* Buffer descriptors used by many of the CPM protocols.
75 */
76 typedef struct cpm_buf_desc {
77 ushort cbd_sc; /* Status and Control */
78 ushort cbd_datlen; /* Data length in buffer */
79 uint cbd_bufaddr; /* Buffer address in host memory */
80 } cbd_t;
81
82 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
83 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
84 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
85 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
86 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
87 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
88 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
89 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
90 #define BD_SC_BR ((ushort)0x0020) /* Break received */
91 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
92 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
93 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
94 #define BD_SC_CD ((ushort)0x0001) /* ?? */
95
96 /* Parameter RAM offsets.
97 */
98 #define PROFF_SCC1 ((uint)0x0000)
99 #define PROFF_IIC ((uint)0x0080)
100 #define PROFF_SCC2 ((uint)0x0100)
101 #define PROFF_SCC3 ((uint)0x0200)
102 #define PROFF_SMC1 ((uint)0x0280)
103 #define PROFF_SCC4 ((uint)0x0300)
104 #define PROFF_SMC2 ((uint)0x0380)
105
106 /* Define enough so I can at least use the serial port as a UART.
107 * The MBX uses SMC1 as the host serial port.
108 */
109 typedef struct smc_uart {
110 ushort smc_rbase; /* Rx Buffer descriptor base address */
111 ushort smc_tbase; /* Tx Buffer descriptor base address */
112 u_char smc_rfcr; /* Rx function code */
113 u_char smc_tfcr; /* Tx function code */
114 ushort smc_mrblr; /* Max receive buffer length */
115 uint smc_rstate; /* Internal */
116 uint smc_idp; /* Internal */
117 ushort smc_rbptr; /* Internal */
118 ushort smc_ibc; /* Internal */
119 uint smc_rxtmp; /* Internal */
120 uint smc_tstate; /* Internal */
121 uint smc_tdp; /* Internal */
122 ushort smc_tbptr; /* Internal */
123 ushort smc_tbc; /* Internal */
124 uint smc_txtmp; /* Internal */
125 ushort smc_maxidl; /* Maximum idle characters */
126 ushort smc_tmpidl; /* Temporary idle counter */
127 ushort smc_brklen; /* Last received break length */
128 ushort smc_brkec; /* rcv'd break condition counter */
129 ushort smc_brkcr; /* xmt break count register */
130 ushort smc_rmask; /* Temporary bit mask */
131 } smc_uart_t;
132
133 /* Function code bits.
134 */
135 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
136
137 /* SMC uart mode register.
138 */
139 #define SMCMR_REN ((ushort)0x0001)
140 #define SMCMR_TEN ((ushort)0x0002)
141 #define SMCMR_DM ((ushort)0x000c)
142 #define SMCMR_SM_GCI ((ushort)0x0000)
143 #define SMCMR_SM_UART ((ushort)0x0020)
144 #define SMCMR_SM_TRANS ((ushort)0x0030)
145 #define SMCMR_SM_MASK ((ushort)0x0030)
146 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
147 #define SMCMR_REVD SMCMR_PM_EVEN
148 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
149 #define SMCMR_BS SMCMR_PEN
150 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
151 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
152 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
153
154 /* SMC2 as Centronics parallel printer. It is half duplex, in that
155 * it can only receive or transmit. The parameter ram values for
156 * each direction are either unique or properly overlap, so we can
157 * include them in one structure.
158 */
159 typedef struct smc_centronics {
160 ushort scent_rbase;
161 ushort scent_tbase;
162 u_char scent_cfcr;
163 u_char scent_smask;
164 ushort scent_mrblr;
165 uint scent_rstate;
166 uint scent_r_ptr;
167 ushort scent_rbptr;
168 ushort scent_r_cnt;
169 uint scent_rtemp;
170 uint scent_tstate;
171 uint scent_t_ptr;
172 ushort scent_tbptr;
173 ushort scent_t_cnt;
174 uint scent_ttemp;
175 ushort scent_max_sl;
176 ushort scent_sl_cnt;
177 ushort scent_character1;
178 ushort scent_character2;
179 ushort scent_character3;
180 ushort scent_character4;
181 ushort scent_character5;
182 ushort scent_character6;
183 ushort scent_character7;
184 ushort scent_character8;
185 ushort scent_rccm;
186 ushort scent_rccr;
187 } smc_cent_t;
188
189 /* Centronics Status Mask Register.
190 */
191 #define SMC_CENT_F ((u_char)0x08)
192 #define SMC_CENT_PE ((u_char)0x04)
193 #define SMC_CENT_S ((u_char)0x02)
194
195 /* SMC Event and Mask register.
196 */
197 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
198 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
199 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
200 #define SMCM_BSY ((unsigned char)0x04)
201 #define SMCM_TX ((unsigned char)0x02)
202 #define SMCM_RX ((unsigned char)0x01)
203
204 /* Baud rate generators.
205 */
206 #define CPM_BRG_RST ((uint)0x00020000)
207 #define CPM_BRG_EN ((uint)0x00010000)
208 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
209 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
210 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
211 #define CPM_BRG_ATB ((uint)0x00002000)
212 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
213 #define CPM_BRG_DIV16 ((uint)0x00000001)
214
215 /* SCCs.
216 */
217 #define SCC_GSMRH_IRP ((uint)0x00040000)
218 #define SCC_GSMRH_GDE ((uint)0x00010000)
219 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
220 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
221 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
222 #define SCC_GSMRH_REVD ((uint)0x00002000)
223 #define SCC_GSMRH_TRX ((uint)0x00001000)
224 #define SCC_GSMRH_TTX ((uint)0x00000800)
225 #define SCC_GSMRH_CDP ((uint)0x00000400)
226 #define SCC_GSMRH_CTSP ((uint)0x00000200)
227 #define SCC_GSMRH_CDS ((uint)0x00000100)
228 #define SCC_GSMRH_CTSS ((uint)0x00000080)
229 #define SCC_GSMRH_TFL ((uint)0x00000040)
230 #define SCC_GSMRH_RFW ((uint)0x00000020)
231 #define SCC_GSMRH_TXSY ((uint)0x00000010)
232 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
233 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
234 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
235 #define SCC_GSMRH_RTSM ((uint)0x00000002)
236 #define SCC_GSMRH_RSYN ((uint)0x00000001)
237
238 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
239 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
240 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
241 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
242 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
243 #define SCC_GSMRL_TCI ((uint)0x10000000)
244 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
245 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
246 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
247 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
248 #define SCC_GSMRL_RINV ((uint)0x02000000)
249 #define SCC_GSMRL_TINV ((uint)0x01000000)
250 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
251 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
252 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
253 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
254 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
255 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
256 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
257 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
258 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
259 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
260 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
261 #define SCC_GSMRL_TEND ((uint)0x00040000)
262 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
263 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
264 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
265 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
266 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
267 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
268 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
269 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
270 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
271 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
272 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
273 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
274 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
275 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
276 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
277 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
278 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
279 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
280 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
281 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
282 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
283 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
284 #define SCC_GSMRL_ENR ((uint)0x00000020)
285 #define SCC_GSMRL_ENT ((uint)0x00000010)
286 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
287 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
288 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
289 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
290 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
291 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
292 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
293 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
294 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
295 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
296
297 #define SCC_TODR_TOD ((ushort)0x8000)
298
299 /* SCC Event and Mask register.
300 */
301 #define SCCM_TXE ((unsigned char)0x10)
302 #define SCCM_BSY ((unsigned char)0x04)
303 #define SCCM_TX ((unsigned char)0x02)
304 #define SCCM_RX ((unsigned char)0x01)
305
306 typedef struct scc_param {
307 ushort scc_rbase; /* Rx Buffer descriptor base address */
308 ushort scc_tbase; /* Tx Buffer descriptor base address */
309 u_char scc_rfcr; /* Rx function code */
310 u_char scc_tfcr; /* Tx function code */
311 ushort scc_mrblr; /* Max receive buffer length */
312 uint scc_rstate; /* Internal */
313 uint scc_idp; /* Internal */
314 ushort scc_rbptr; /* Internal */
315 ushort scc_ibc; /* Internal */
316 uint scc_rxtmp; /* Internal */
317 uint scc_tstate; /* Internal */
318 uint scc_tdp; /* Internal */
319 ushort scc_tbptr; /* Internal */
320 ushort scc_tbc; /* Internal */
321 uint scc_txtmp; /* Internal */
322 uint scc_rcrc; /* Internal */
323 uint scc_tcrc; /* Internal */
324 } sccp_t;
325
326 /* Function code bits.
327 */
328 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
329
330 /* CPM Ethernet through SCCx.
331 */
332 typedef struct scc_enet {
333 sccp_t sen_genscc;
334 uint sen_cpres; /* Preset CRC */
335 uint sen_cmask; /* Constant mask for CRC */
336 uint sen_crcec; /* CRC Error counter */
337 uint sen_alec; /* alignment error counter */
338 uint sen_disfc; /* discard frame counter */
339 ushort sen_pads; /* Tx short frame pad character */
340 ushort sen_retlim; /* Retry limit threshold */
341 ushort sen_retcnt; /* Retry limit counter */
342 ushort sen_maxflr; /* maximum frame length register */
343 ushort sen_minflr; /* minimum frame length register */
344 ushort sen_maxd1; /* maximum DMA1 length */
345 ushort sen_maxd2; /* maximum DMA2 length */
346 ushort sen_maxd; /* Rx max DMA */
347 ushort sen_dmacnt; /* Rx DMA counter */
348 ushort sen_maxb; /* Max BD byte count */
349 ushort sen_gaddr1; /* Group address filter */
350 ushort sen_gaddr2;
351 ushort sen_gaddr3;
352 ushort sen_gaddr4;
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
355 uint sen_tbuf0rba; /* Internal */
356 uint sen_tbuf0crc; /* Internal */
357 ushort sen_tbuf0bcnt; /* Internal */
358 ushort sen_paddrh; /* physical address (MSB) */
359 ushort sen_paddrm;
360 ushort sen_paddrl; /* physical address (LSB) */
361 ushort sen_pper; /* persistence */
362 ushort sen_rfbdptr; /* Rx first BD pointer */
363 ushort sen_tfbdptr; /* Tx first BD pointer */
364 ushort sen_tlbdptr; /* Tx last BD pointer */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
366 uint sen_tbuf1data1; /* Save area 1 - current frame */
367 uint sen_tbuf1rba; /* Internal */
368 uint sen_tbuf1crc; /* Internal */
369 ushort sen_tbuf1bcnt; /* Internal */
370 ushort sen_txlen; /* Tx Frame length counter */
371 ushort sen_iaddr1; /* Individual address filter */
372 ushort sen_iaddr2;
373 ushort sen_iaddr3;
374 ushort sen_iaddr4;
375 ushort sen_boffcnt; /* Backoff counter */
376
377 /* NOTE: Some versions of the manual have the following items
378 * incorrectly documented. Below is the proper order.
379 */
380 ushort sen_taddrh; /* temp address (MSB) */
381 ushort sen_taddrm;
382 ushort sen_taddrl; /* temp address (LSB) */
383 } scc_enet_t;
384
385 /*** MBX ************************************************************/
386
387 #ifdef CONFIG_MBX
388 /* Bits in parallel I/O port registers that have to be set/cleared
389 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
390 * to the MBX860 board. Any two of the four available clocks could be
391 * used, and the MPC860 cookbook manual has an example using different
392 * clock pins.
393 */
394 #define PA_ENET_RXD ((ushort)0x0001)
395 #define PA_ENET_TXD ((ushort)0x0002)
396 #define PA_ENET_TCLK ((ushort)0x0200)
397 #define PA_ENET_RCLK ((ushort)0x0800)
398 #define PC_ENET_TENA ((ushort)0x0001)
399 #define PC_ENET_CLSN ((ushort)0x0010)
400 #define PC_ENET_RENA ((ushort)0x0020)
401
402 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
403 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
404 */
405 #define SICR_ENET_MASK ((uint)0x000000ff)
406 #define SICR_ENET_CLKRT ((uint)0x0000003d)
407 #endif /* CONFIG_MBX */
408
409 /*** RPXLITE ********************************************************/
410
411 #ifdef CONFIG_RPXLITE
412 /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
413 * this may be unique to the RPX-Lite configuration.
414 * Note TENA is on Port B.
415 */
416 #define PA_ENET_RXD ((ushort)0x0004)
417 #define PA_ENET_TXD ((ushort)0x0008)
418 #define PA_ENET_TCLK ((ushort)0x0200)
419 #define PA_ENET_RCLK ((ushort)0x0800)
420 #define PB_ENET_TENA ((uint)0x00002000)
421 #define PC_ENET_CLSN ((ushort)0x0040)
422 #define PC_ENET_RENA ((ushort)0x0080)
423
424 #define SICR_ENET_MASK ((uint)0x0000ff00)
425 #define SICR_ENET_CLKRT ((uint)0x00003d00)
426 #endif /* CONFIG_RPXLITE */
427
428 /*** BSEIP **********************************************************/
429
430 #ifdef CONFIG_BSEIP
431 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
432 * This is unique to the BSE ip-Engine board.
433 */
434 #define PA_ENET_RXD ((ushort)0x0004)
435 #define PA_ENET_TXD ((ushort)0x0008)
436 #define PA_ENET_TCLK ((ushort)0x0100)
437 #define PA_ENET_RCLK ((ushort)0x0200)
438 #define PB_ENET_TENA ((uint)0x00002000)
439 #define PC_ENET_CLSN ((ushort)0x0040)
440 #define PC_ENET_RENA ((ushort)0x0080)
441
442 /* BSE uses port B and C bits for PHY control also.
443 */
444 #define PB_BSE_POWERUP ((uint)0x00000004)
445 #define PB_BSE_FDXDIS ((uint)0x00008000)
446 #define PC_BSE_LOOPBACK ((ushort)0x0800)
447
448 #define SICR_ENET_MASK ((uint)0x0000ff00)
449 #define SICR_ENET_CLKRT ((uint)0x00002c00)
450 #endif /* CONFIG_BSEIP */
451
452 /*** RPXCLASSIC *****************************************************/
453
454 #ifdef CONFIG_RPXCLASSIC
455 /* Bits in parallel I/O port registers that have to be set/cleared
456 * to configure the pins for SCC1 use.
457 */
458 #define PA_ENET_RXD ((ushort)0x0001)
459 #define PA_ENET_TXD ((ushort)0x0002)
460 #define PA_ENET_TCLK ((ushort)0x0200)
461 #define PA_ENET_RCLK ((ushort)0x0800)
462 #define PB_ENET_TENA ((uint)0x00001000)
463 #define PC_ENET_CLSN ((ushort)0x0010)
464 #define PC_ENET_RENA ((ushort)0x0020)
465
466 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
467 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
468 */
469 #define SICR_ENET_MASK ((uint)0x000000ff)
470 #define SICR_ENET_CLKRT ((uint)0x0000003d)
471 #endif /* CONFIG_RPXCLASSIC */
472
473 /*** TQM823L, TQM850L ***********************************************/
474
475 #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
476 /* Bits in parallel I/O port registers that have to be set/cleared
477 * to configure the pins for SCC1 use.
478 */
479 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
480 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
481 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
482 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
483
484 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
485
486 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
487 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
488
489 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
490 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
491 */
492 #define SICR_ENET_MASK ((uint)0x0000ff00)
493 #define SICR_ENET_CLKRT ((uint)0x00002600)
494 #endif /* CONFIG_TQM823L, CONFIG_TQM850L */
495
496 /*** FPS850L *********************************************************/
497
498 #ifdef CONFIG_FPS850L
499 /* Bits in parallel I/O port registers that have to be set/cleared
500 * to configure the pins for SCC1 use.
501 */
502 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
503 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
504 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
505 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
506
507 #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
508 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
509 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
510
511 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
512 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
513 */
514 #define SICR_ENET_MASK ((uint)0x0000ff00)
515 #define SICR_ENET_CLKRT ((uint)0x00002600)
516 #endif /* CONFIG_FPS850L */
517
518 /*** TQM860L ********************************************************/
519
520 #ifdef CONFIG_TQM860L
521 /* Bits in parallel I/O port registers that have to be set/cleared
522 * to configure the pins for SCC1 use.
523 */
524 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
525 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
526 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
527 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
528
529 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
530 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
531 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
532
533 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
534 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
535 */
536 #define SICR_ENET_MASK ((uint)0x000000ff)
537 #define SICR_ENET_CLKRT ((uint)0x00000026)
538 #endif /* CONFIG_TQM860L */
539
540 /*** SPD823TS *******************************************************/
541
542 #ifdef CONFIG_SPD823TS
543 /* Bits in parallel I/O port registers that have to be set/cleared
544 * to configure the pins for SCC2 use.
545 */
546 #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
547 #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
548 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
549 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
550 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
551 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
552
553 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
554
555 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
556 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
557 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
558
559 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
560 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
561 */
562 #define SICR_ENET_MASK ((uint)0x0000ff00)
563 #define SICR_ENET_CLKRT ((uint)0x00002E00)
564 #endif /* CONFIG_SPD823TS */
565
566
567 /*** SM850 *********************************************************/
568
569 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
570
571 #ifdef CONFIG_SM850
572 #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
573 #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
574 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
575 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
576
577 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
578 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
579
580 #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
581 #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
582
583 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
584 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
585 */
586 #define SICR_ENET_MASK ((uint)0x00FF0000)
587 #define SICR_ENET_CLKRT ((uint)0x00260000)
588 #endif /* CONFIG_SM850 */
589
590 /*********************************************************************/
591
592 /* SCC Event register as used by Ethernet.
593 */
594 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
595 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
596 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
597 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
598 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
599 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
600
601 /* SCC Mode Register (PMSR) as used by Ethernet.
602 */
603 #define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
604 #define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
605 #define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
606 #define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
607 #define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
608 #define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
609 #define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
610 #define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
611 #define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
612 #define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
613 #define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
614 #define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
615 #define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
616
617 /* Buffer descriptor control/status used by Ethernet receive.
618 */
619 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
620 #define BD_ENET_RX_WRAP ((ushort)0x2000)
621 #define BD_ENET_RX_INTR ((ushort)0x1000)
622 #define BD_ENET_RX_LAST ((ushort)0x0800)
623 #define BD_ENET_RX_FIRST ((ushort)0x0400)
624 #define BD_ENET_RX_MISS ((ushort)0x0100)
625 #define BD_ENET_RX_LG ((ushort)0x0020)
626 #define BD_ENET_RX_NO ((ushort)0x0010)
627 #define BD_ENET_RX_SH ((ushort)0x0008)
628 #define BD_ENET_RX_CR ((ushort)0x0004)
629 #define BD_ENET_RX_OV ((ushort)0x0002)
630 #define BD_ENET_RX_CL ((ushort)0x0001)
631 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
632
633 /* Buffer descriptor control/status used by Ethernet transmit.
634 */
635 #define BD_ENET_TX_READY ((ushort)0x8000)
636 #define BD_ENET_TX_PAD ((ushort)0x4000)
637 #define BD_ENET_TX_WRAP ((ushort)0x2000)
638 #define BD_ENET_TX_INTR ((ushort)0x1000)
639 #define BD_ENET_TX_LAST ((ushort)0x0800)
640 #define BD_ENET_TX_TC ((ushort)0x0400)
641 #define BD_ENET_TX_DEF ((ushort)0x0200)
642 #define BD_ENET_TX_HB ((ushort)0x0100)
643 #define BD_ENET_TX_LC ((ushort)0x0080)
644 #define BD_ENET_TX_RL ((ushort)0x0040)
645 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
646 #define BD_ENET_TX_UN ((ushort)0x0002)
647 #define BD_ENET_TX_CSL ((ushort)0x0001)
648 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
649
650 /* SCC as UART
651 */
652 typedef struct scc_uart {
653 sccp_t scc_genscc;
654 uint scc_res1; /* Reserved */
655 uint scc_res2; /* Reserved */
656 ushort scc_maxidl; /* Maximum idle chars */
657 ushort scc_idlc; /* temp idle counter */
658 ushort scc_brkcr; /* Break count register */
659 ushort scc_parec; /* receive parity error counter */
660 ushort scc_frmec; /* receive framing error counter */
661 ushort scc_nosec; /* receive noise counter */
662 ushort scc_brkec; /* receive break condition counter */
663 ushort scc_brkln; /* last received break length */
664 ushort scc_uaddr1; /* UART address character 1 */
665 ushort scc_uaddr2; /* UART address character 2 */
666 ushort scc_rtemp; /* Temp storage */
667 ushort scc_toseq; /* Transmit out of sequence char */
668 ushort scc_char1; /* control character 1 */
669 ushort scc_char2; /* control character 2 */
670 ushort scc_char3; /* control character 3 */
671 ushort scc_char4; /* control character 4 */
672 ushort scc_char5; /* control character 5 */
673 ushort scc_char6; /* control character 6 */
674 ushort scc_char7; /* control character 7 */
675 ushort scc_char8; /* control character 8 */
676 ushort scc_rccm; /* receive control character mask */
677 ushort scc_rccr; /* receive control character register */
678 ushort scc_rlbc; /* receive last break character */
679 } scc_uart_t;
680
681 /* SCC Event and Mask registers when it is used as a UART.
682 */
683 #define UART_SCCM_GLR ((ushort)0x1000)
684 #define UART_SCCM_GLT ((ushort)0x0800)
685 #define UART_SCCM_AB ((ushort)0x0200)
686 #define UART_SCCM_IDL ((ushort)0x0100)
687 #define UART_SCCM_GRA ((ushort)0x0080)
688 #define UART_SCCM_BRKE ((ushort)0x0040)
689 #define UART_SCCM_BRKS ((ushort)0x0020)
690 #define UART_SCCM_CCR ((ushort)0x0008)
691 #define UART_SCCM_BSY ((ushort)0x0004)
692 #define UART_SCCM_TX ((ushort)0x0002)
693 #define UART_SCCM_RX ((ushort)0x0001)
694
695 /* The SCC PMSR when used as a UART.
696 */
697 #define SCU_PMSR_FLC ((ushort)0x8000)
698 #define SCU_PMSR_SL ((ushort)0x4000)
699 #define SCU_PMSR_CL ((ushort)0x3000)
700 #define SCU_PMSR_UM ((ushort)0x0c00)
701 #define SCU_PMSR_FRZ ((ushort)0x0200)
702 #define SCU_PMSR_RZS ((ushort)0x0100)
703 #define SCU_PMSR_SYN ((ushort)0x0080)
704 #define SCU_PMSR_DRT ((ushort)0x0040)
705 #define SCU_PMSR_PEN ((ushort)0x0010)
706 #define SCU_PMSR_RPM ((ushort)0x000c)
707 #define SCU_PMSR_REVP ((ushort)0x0008)
708 #define SCU_PMSR_TPM ((ushort)0x0003)
709 #define SCU_PMSR_TEVP ((ushort)0x0003)
710
711 /* CPM Transparent mode SCC.
712 */
713 typedef struct scc_trans {
714 sccp_t st_genscc;
715 uint st_cpres; /* Preset CRC */
716 uint st_cmask; /* Constant mask for CRC */
717 } scc_trans_t;
718
719 #define BD_SCC_TX_LAST ((ushort)0x0800)
720
721 /* IIC parameter RAM.
722 */
723 typedef struct iic {
724 ushort iic_rbase; /* Rx Buffer descriptor base address */
725 ushort iic_tbase; /* Tx Buffer descriptor base address */
726 u_char iic_rfcr; /* Rx function code */
727 u_char iic_tfcr; /* Tx function code */
728 ushort iic_mrblr; /* Max receive buffer length */
729 uint iic_rstate; /* Internal */
730 uint iic_rdp; /* Internal */
731 ushort iic_rbptr; /* Internal */
732 ushort iic_rbc; /* Internal */
733 uint iic_rxtmp; /* Internal */
734 uint iic_tstate; /* Internal */
735 uint iic_tdp; /* Internal */
736 ushort iic_tbptr; /* Internal */
737 ushort iic_tbc; /* Internal */
738 uint iic_txtmp; /* Internal */
739 } iic_t;
740
741 #define BD_IIC_START ((ushort)0x0400)
742
743 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
744 * channels or devices. All of these are presented to the PPC core
745 * as a single interrupt. The CPM interrupt handler dispatches its
746 * own handlers, in a similar fashion to the PPC core handler. We
747 * use the table as defined in the manuals (i.e. no special high
748 * priority and SCC1 == SCCa, etc...).
749 */
750 #define CPMVEC_NR 32
751 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
752 #define CPMVEC_SCC1 ((ushort)0x1e)
753 #define CPMVEC_SCC2 ((ushort)0x1d)
754 #define CPMVEC_SCC3 ((ushort)0x1c)
755 #define CPMVEC_SCC4 ((ushort)0x1b)
756 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
757 #define CPMVEC_TIMER1 ((ushort)0x19)
758 #define CPMVEC_PIO_PC13 ((ushort)0x18)
759 #define CPMVEC_PIO_PC12 ((ushort)0x17)
760 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
761 #define CPMVEC_IDMA1 ((ushort)0x15)
762 #define CPMVEC_IDMA2 ((ushort)0x14)
763 #define CPMVEC_TIMER2 ((ushort)0x12)
764 #define CPMVEC_RISCTIMER ((ushort)0x11)
765 #define CPMVEC_I2C ((ushort)0x10)
766 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
767 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
768 #define CPMVEC_TIMER3 ((ushort)0x0c)
769 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
770 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
771 #define CPMVEC_PIO_PC7 ((ushort)0x09)
772 #define CPMVEC_TIMER4 ((ushort)0x07)
773 #define CPMVEC_PIO_PC6 ((ushort)0x06)
774 #define CPMVEC_SPI ((ushort)0x05)
775 #define CPMVEC_SMC1 ((ushort)0x04)
776 #define CPMVEC_SMC2 ((ushort)0x03)
777 #define CPMVEC_PIO_PC5 ((ushort)0x02)
778 #define CPMVEC_PIO_PC4 ((ushort)0x01)
779 #define CPMVEC_ERROR ((ushort)0x00)
780
781 /* CPM interrupt configuration vector.
782 */
783 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
784 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
785 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
786 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
787 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
788 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
789 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
790 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
791
792 extern void cpm_install_handler(int vec,
793 void (*handler)(void *, struct pt_regs *regs), void *dev_id);
794 extern void cpm_free_handler(int vec);
795
796 #endif /* __CPM_8XX__ */
797