File: /usr/src/linux/arch/ppc/8xx_io/fec.c
1 /*
2 * BK Id: SCCS/s.fec.c 1.12 05/18/01 07:54:04 patch
3 */
4 /*
5 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
7 *
8 * This version of the driver is specific to the FADS implementation,
9 * since the board contains control registers external to the processor
10 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
11 * describes connections using the internal parallel port I/O, which
12 * is basically all of Port D.
13 *
14 * Includes support for the following PHYs: QS6612, LXT970, LXT971/2.
15 *
16 * Right now, I am very wasteful with the buffers. I allocate memory
17 * pages and then divide them into 2K frame buffers. This way I know I
18 * have buffers large enough to hold one frame within one buffer descriptor.
19 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
20 * will be much more memory efficient and will easily handle lots of
21 * small packets.
22 *
23 * Much better multiple PHY support by Magnus Damm.
24 * Copyright (c) 2000 Ericsson Radio Systems AB.
25 *
26 * Make use of MII for PHY control configurable.
27 * Some fixes.
28 * Copyright (c) 2000 Wolfgang Denk, DENX Software Engineering.
29 */
30
31 /* List of PHYs we wish to support.
32 */
33 #undef CONFIG_FEC_LXT970
34 #define CONFIG_FEC_LXT971
35 #undef CONFIG_FEC_QS6612
36
37 #include <linux/config.h>
38 #include <linux/kernel.h>
39 #include <linux/sched.h>
40 #include <linux/string.h>
41 #include <linux/ptrace.h>
42 #include <linux/errno.h>
43 #include <linux/ioport.h>
44 #include <linux/slab.h>
45 #include <linux/interrupt.h>
46 #include <linux/pci.h>
47 #include <linux/init.h>
48 #include <linux/delay.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #ifdef CONFIG_FEC_PACKETHOOK
54 #include <linux/pkthook.h>
55 #endif
56
57 #include <asm/8xx_immap.h>
58 #include <asm/pgtable.h>
59 #include <asm/mpc8xx.h>
60 #include <asm/irq.h>
61 #include <asm/bitops.h>
62 #include <asm/uaccess.h>
63 #include "commproc.h"
64
65 #ifdef CONFIG_USE_MDIO
66 /* Forward declarations of some structures to support different PHYs
67 */
68
69 typedef struct {
70 uint mii_data;
71 void (*funct)(uint mii_reg, struct net_device *dev);
72 } phy_cmd_t;
73
74 typedef struct {
75 uint id;
76 char *name;
77
78 const phy_cmd_t *config;
79 const phy_cmd_t *startup;
80 const phy_cmd_t *ack_int;
81 const phy_cmd_t *shutdown;
82 } phy_info_t;
83 #endif /* CONFIG_USE_MDIO */
84
85 /* The number of Tx and Rx buffers. These are allocated from the page
86 * pool. The code may assume these are power of two, so it is best
87 * to keep them that size.
88 * We don't need to allocate pages for the transmitter. We just use
89 * the skbuffer directly.
90 */
91 #ifdef CONFIG_ENET_BIG_BUFFERS
92 #define FEC_ENET_RX_PAGES 16
93 #define FEC_ENET_RX_FRSIZE 2048
94 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
95 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
96 #define TX_RING_SIZE 16 /* Must be power of two */
97 #define TX_RING_MOD_MASK 15 /* for this to work */
98 #else
99 #define FEC_ENET_RX_PAGES 4
100 #define FEC_ENET_RX_FRSIZE 2048
101 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
102 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
103 #define TX_RING_SIZE 8 /* Must be power of two */
104 #define TX_RING_MOD_MASK 7 /* for this to work */
105 #endif
106
107 /* Interrupt events/masks.
108 */
109 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
110 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
111 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
112 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
113 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
114 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
115 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
116 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
117 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
118 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
119
120 /*
121 */
122 #define FEC_ECNTRL_PINMUX 0x00000004
123 #define FEC_ECNTRL_ETHER_EN 0x00000002
124 #define FEC_ECNTRL_RESET 0x00000001
125
126 #define FEC_RCNTRL_BC_REJ 0x00000010
127 #define FEC_RCNTRL_PROM 0x00000008
128 #define FEC_RCNTRL_MII_MODE 0x00000004
129 #define FEC_RCNTRL_DRT 0x00000002
130 #define FEC_RCNTRL_LOOP 0x00000001
131
132 #define FEC_TCNTRL_FDEN 0x00000004
133 #define FEC_TCNTRL_HBC 0x00000002
134 #define FEC_TCNTRL_GTS 0x00000001
135
136 /* Delay to wait for FEC reset command to complete (in us)
137 */
138 #define FEC_RESET_DELAY 50
139
140 /* The FEC stores dest/src/type, data, and checksum for receive packets.
141 */
142 #define PKT_MAXBUF_SIZE 1518
143 #define PKT_MINBUF_SIZE 64
144 #define PKT_MAXBLR_SIZE 1520
145
146 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
147 * tx_bd_base always point to the base of the buffer descriptors. The
148 * cur_rx and cur_tx point to the currently available buffer.
149 * The dirty_tx tracks the current buffer that is being sent by the
150 * controller. The cur_tx and dirty_tx are equal under both completely
151 * empty and completely full conditions. The empty/ready indicator in
152 * the buffer descriptor determines the actual condition.
153 */
154 struct fec_enet_private {
155 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
156 struct sk_buff* tx_skbuff[TX_RING_SIZE];
157 ushort skb_cur;
158 ushort skb_dirty;
159
160 /* CPM dual port RAM relative addresses.
161 */
162 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
163 cbd_t *tx_bd_base;
164 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
165 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
166 scc_t *sccp;
167 struct net_device_stats stats;
168 uint tx_full;
169 spinlock_t lock;
170
171 #ifdef CONFIG_USE_MDIO
172 uint phy_id;
173 uint phy_id_done;
174 uint phy_status;
175 uint phy_speed;
176 phy_info_t *phy;
177 struct tq_struct phy_task;
178
179 uint sequence_done;
180
181 uint phy_addr;
182 #endif /* CONFIG_USE_MDIO */
183
184 int link;
185 int old_link;
186 int full_duplex;
187
188 #ifdef CONFIG_FEC_PACKETHOOK
189 unsigned long ph_lock;
190 fec_ph_func *ph_rxhandler;
191 fec_ph_func *ph_txhandler;
192 __u16 ph_proto;
193 volatile __u32 *ph_regaddr;
194 void *ph_priv;
195 #endif
196 };
197
198 static int fec_enet_open(struct net_device *dev);
199 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
200 #ifdef CONFIG_USE_MDIO
201 static void fec_enet_mii(struct net_device *dev);
202 #endif /* CONFIG_USE_MDIO */
203 static void fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
204 #ifdef CONFIG_FEC_PACKETHOOK
205 static void fec_enet_tx(struct net_device *dev, __u32 regval);
206 static void fec_enet_rx(struct net_device *dev, __u32 regval);
207 #else
208 static void fec_enet_tx(struct net_device *dev);
209 static void fec_enet_rx(struct net_device *dev);
210 #endif
211 static int fec_enet_close(struct net_device *dev);
212 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
213 static void set_multicast_list(struct net_device *dev);
214 static void fec_restart(struct net_device *dev, int duplex);
215 static void fec_stop(struct net_device *dev);
216 static ushort my_enet_addr[3];
217
218 #ifdef CONFIG_USE_MDIO
219 /* MII processing. We keep this as simple as possible. Requests are
220 * placed on the list (if there is room). When the request is finished
221 * by the MII, an optional function may be called.
222 */
223 typedef struct mii_list {
224 uint mii_regval;
225 void (*mii_func)(uint val, struct net_device *dev);
226 struct mii_list *mii_next;
227 } mii_list_t;
228
229 #define NMII 20
230 mii_list_t mii_cmds[NMII];
231 mii_list_t *mii_free;
232 mii_list_t *mii_head;
233 mii_list_t *mii_tail;
234
235 static int mii_queue(struct net_device *dev, int request,
236 void (*func)(uint, struct net_device *));
237
238 /* Make MII read/write commands for the FEC.
239 */
240 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
241 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
242 (VAL & 0xffff))
243 #define mk_mii_end 0
244 #endif /* CONFIG_USE_MDIO */
245
246 /* Transmitter timeout.
247 */
248 #define TX_TIMEOUT (2*HZ)
249
250 #ifdef CONFIG_USE_MDIO
251 /* Register definitions for the PHY.
252 */
253
254 #define MII_REG_CR 0 /* Control Register */
255 #define MII_REG_SR 1 /* Status Register */
256 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
257 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
258 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
259 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
260 #define MII_REG_ANER 6 /* A-N Expansion Register */
261 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
262 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
263
264 /* values for phy_status */
265
266 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
267 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
268 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
269 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
270 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
271 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
272 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
273
274 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
275 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
276 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
277 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
278 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
279 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
280 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
281 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
282 #endif /* CONFIG_USE_MDIO */
283
284 #ifdef CONFIG_FEC_PACKETHOOK
285 int
286 fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun,
287 __u16 proto, volatile __u32 *regaddr, void *priv)
288 {
289 struct fec_enet_private *fep;
290 int retval = 0;
291
292 fep = dev->priv;
293
294 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
295 /* Someone is messing with the packet hook */
296 return -EAGAIN;
297 }
298 if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) {
299 retval = -EBUSY;
300 goto out;
301 }
302 fep->ph_rxhandler = rxfun;
303 fep->ph_txhandler = txfun;
304 fep->ph_proto = proto;
305 fep->ph_regaddr = regaddr;
306 fep->ph_priv = priv;
307
308 out:
309 fep->ph_lock = 0;
310
311 return retval;
312 }
313
314
315 int
316 fec_unregister_ph(struct net_device *dev)
317 {
318 struct fec_enet_private *fep;
319 int retval = 0;
320
321 fep = dev->priv;
322
323 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
324 /* Someone is messing with the packet hook */
325 return -EAGAIN;
326 }
327
328 fep->ph_rxhandler = fep->ph_txhandler = NULL;
329 fep->ph_proto = 0;
330 fep->ph_regaddr = NULL;
331 fep->ph_priv = NULL;
332
333 fep->ph_lock = 0;
334
335 return retval;
336 }
337
338 EXPORT_SYMBOL(fec_register_ph);
339 EXPORT_SYMBOL(fec_unregister_ph);
340
341 #endif /* CONFIG_FEC_PACKETHOOK */
342
343 static int
344 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
345 {
346 struct fec_enet_private *fep;
347 volatile fec_t *fecp;
348 volatile cbd_t *bdp;
349
350 fep = dev->priv;
351 fecp = (volatile fec_t*)dev->base_addr;
352
353 if (!fep->link) {
354 /* Link is down or autonegotiation is in progress. */
355 return 1;
356 }
357
358 /* Fill in a Tx ring entry */
359 bdp = fep->cur_tx;
360
361 #ifndef final_version
362 if (bdp->cbd_sc & BD_ENET_TX_READY) {
363 /* Ooops. All transmit buffers are full. Bail out.
364 * This should not happen, since dev->tbusy should be set.
365 */
366 printk("%s: tx queue full!.\n", dev->name);
367 return 1;
368 }
369 #endif
370
371 /* Clear all of the status flags.
372 */
373 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
374
375 /* Set buffer length and buffer pointer.
376 */
377 bdp->cbd_bufaddr = __pa(skb->data);
378 bdp->cbd_datlen = skb->len;
379
380 /* Save skb pointer.
381 */
382 fep->tx_skbuff[fep->skb_cur] = skb;
383
384 fep->stats.tx_bytes += skb->len;
385 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
386
387 /* Push the data cache so the CPM does not get stale memory
388 * data.
389 */
390 flush_dcache_range((unsigned long)skb->data,
391 (unsigned long)skb->data + skb->len);
392
393 spin_lock_irq(&fep->lock);
394
395 /* Send it on its way. Tell FEC its ready, interrupt when done,
396 * its the last BD of the frame, and to put the CRC on the end.
397 */
398
399 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
400 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
401
402 dev->trans_start = jiffies;
403
404 /* Trigger transmission start */
405 fecp->fec_x_des_active = 0x01000000;
406
407 /* If this was the last BD in the ring, start at the beginning again.
408 */
409 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
410 bdp = fep->tx_bd_base;
411 } else {
412 bdp++;
413 }
414
415 if (bdp->cbd_sc & BD_ENET_TX_READY)
416 netif_stop_queue(dev);
417
418 fep->cur_tx = (cbd_t *)bdp;
419
420 spin_unlock_irq(&fep->lock);
421
422 return 0;
423 }
424
425 static void
426 fec_timeout(struct net_device *dev)
427 {
428 struct fec_enet_private *fep = dev->priv;
429
430 printk("%s: transmit timed out.\n", dev->name);
431 fep->stats.tx_errors++;
432 #ifndef final_version
433 {
434 int i;
435 cbd_t *bdp;
436
437 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
438 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
439 (unsigned long)fep->dirty_tx,
440 (unsigned long)fep->cur_rx);
441
442 bdp = fep->tx_bd_base;
443 printk(" tx: %u buffers\n", TX_RING_SIZE);
444 for (i = 0 ; i < TX_RING_SIZE; i++) {
445 printk(" %08x: %04x %04x %08x\n",
446 (uint) bdp,
447 bdp->cbd_sc,
448 bdp->cbd_datlen,
449 bdp->cbd_bufaddr);
450 bdp++;
451 }
452
453 bdp = fep->rx_bd_base;
454 printk(" rx: %lu buffers\n", RX_RING_SIZE);
455 for (i = 0 ; i < RX_RING_SIZE; i++) {
456 printk(" %08x: %04x %04x %08x\n",
457 (uint) bdp,
458 bdp->cbd_sc,
459 bdp->cbd_datlen,
460 bdp->cbd_bufaddr);
461 bdp++;
462 }
463 }
464 #endif
465 if (!fep->tx_full)
466 netif_wake_queue(dev);
467 }
468
469 /* The interrupt handler.
470 * This is called from the MPC core interrupt.
471 */
472 static void
473 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
474 {
475 struct net_device *dev = dev_id;
476 volatile fec_t *fecp;
477 uint int_events;
478 #ifdef CONFIG_FEC_PACKETHOOK
479 struct fec_enet_private *fep = dev->priv;
480 __u32 regval;
481
482 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
483 #endif
484 fecp = (volatile fec_t*)dev->base_addr;
485
486 /* Get the interrupt events that caused us to be here.
487 */
488 while ((int_events = fecp->fec_ievent) != 0) {
489 fecp->fec_ievent = int_events;
490 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
491 FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
492 printk("FEC ERROR %x\n", int_events);
493 }
494
495 /* Handle receive event in its own function.
496 */
497 if (int_events & FEC_ENET_RXF) {
498 #ifdef CONFIG_FEC_PACKETHOOK
499 fec_enet_rx(dev, regval);
500 #else
501 fec_enet_rx(dev);
502 #endif
503 }
504
505 /* Transmit OK, or non-fatal error. Update the buffer
506 descriptors. FEC handles all errors, we just discover
507 them as part of the transmit process.
508 */
509 if (int_events & FEC_ENET_TXF) {
510 #ifdef CONFIG_FEC_PACKETHOOK
511 fec_enet_tx(dev, regval);
512 #else
513 fec_enet_tx(dev);
514 #endif
515 }
516
517 if (int_events & FEC_ENET_MII) {
518 #ifdef CONFIG_USE_MDIO
519 fec_enet_mii(dev);
520 #else
521 printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
522 #endif /* CONFIG_USE_MDIO */
523 }
524
525 }
526 }
527
528
529 static void
530 #ifdef CONFIG_FEC_PACKETHOOK
531 fec_enet_tx(struct net_device *dev, __u32 regval)
532 #else
533 fec_enet_tx(struct net_device *dev)
534 #endif
535 {
536 struct fec_enet_private *fep;
537 volatile cbd_t *bdp;
538 struct sk_buff *skb;
539
540 fep = dev->priv;
541 spin_lock(&fep->lock);
542 bdp = fep->dirty_tx;
543
544 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
545 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
546
547 skb = fep->tx_skbuff[fep->skb_dirty];
548 /* Check for errors. */
549 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
550 BD_ENET_TX_RL | BD_ENET_TX_UN |
551 BD_ENET_TX_CSL)) {
552 fep->stats.tx_errors++;
553 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
554 fep->stats.tx_heartbeat_errors++;
555 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
556 fep->stats.tx_window_errors++;
557 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
558 fep->stats.tx_aborted_errors++;
559 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
560 fep->stats.tx_fifo_errors++;
561 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
562 fep->stats.tx_carrier_errors++;
563 } else {
564 #ifdef CONFIG_FEC_PACKETHOOK
565 /* Packet hook ... */
566 if (fep->ph_txhandler &&
567 ((struct ethhdr *)skb->data)->h_proto
568 == fep->ph_proto) {
569 fep->ph_txhandler((__u8*)skb->data, skb->len,
570 regval, fep->ph_priv);
571 }
572 #endif
573 fep->stats.tx_packets++;
574 }
575
576 #ifndef final_version
577 if (bdp->cbd_sc & BD_ENET_TX_READY)
578 printk("HEY! Enet xmit interrupt and TX_READY.\n");
579 #endif
580 /* Deferred means some collisions occurred during transmit,
581 * but we eventually sent the packet OK.
582 */
583 if (bdp->cbd_sc & BD_ENET_TX_DEF)
584 fep->stats.collisions++;
585
586 /* Free the sk buffer associated with this last transmit.
587 */
588 #if 0
589 printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty);
590 #endif
591 dev_kfree_skb_irq (skb/*, FREE_WRITE*/);
592 fep->tx_skbuff[fep->skb_dirty] = NULL;
593 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
594
595 /* Update pointer to next buffer descriptor to be transmitted.
596 */
597 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
598 bdp = fep->tx_bd_base;
599 else
600 bdp++;
601
602 /* Since we have freed up a buffer, the ring is no longer
603 * full.
604 */
605 if (fep->tx_full) {
606 fep->tx_full = 0;
607 if (netif_queue_stopped(dev))
608 netif_wake_queue(dev);
609 }
610 #ifdef CONFIG_FEC_PACKETHOOK
611 /* Re-read register. Not exactly guaranteed to be correct,
612 but... */
613 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
614 #endif
615 }
616 fep->dirty_tx = (cbd_t *)bdp;
617 spin_unlock(&fep->lock);
618 }
619
620
621 /* During a receive, the cur_rx points to the current incoming buffer.
622 * When we update through the ring, if the next incoming buffer has
623 * not been given to the system, we just set the empty indicator,
624 * effectively tossing the packet.
625 */
626 static void
627 #ifdef CONFIG_FEC_PACKETHOOK
628 fec_enet_rx(struct net_device *dev, __u32 regval)
629 #else
630 fec_enet_rx(struct net_device *dev)
631 #endif
632 {
633 struct fec_enet_private *fep;
634 volatile fec_t *fecp;
635 volatile cbd_t *bdp;
636 struct sk_buff *skb;
637 ushort pkt_len;
638 __u8 *data;
639
640 fep = dev->priv;
641 fecp = (volatile fec_t*)dev->base_addr;
642
643 /* First, grab all of the stats for the incoming packet.
644 * These get messed up if we get called due to a busy condition.
645 */
646 bdp = fep->cur_rx;
647
648 while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
649
650 #ifndef final_version
651 /* Since we have allocated space to hold a complete frame,
652 * the last indicator should be set.
653 */
654 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
655 printk("FEC ENET: rcv is not +last\n");
656 #endif
657
658 /* Check for errors. */
659 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
660 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
661 fep->stats.rx_errors++;
662 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
663 /* Frame too long or too short. */
664 fep->stats.rx_length_errors++;
665 }
666 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
667 fep->stats.rx_frame_errors++;
668 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
669 fep->stats.rx_crc_errors++;
670 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
671 fep->stats.rx_crc_errors++;
672 }
673
674 /* Report late collisions as a frame error.
675 * On this error, the BD is closed, but we don't know what we
676 * have in the buffer. So, just drop this frame on the floor.
677 */
678 if (bdp->cbd_sc & BD_ENET_RX_CL) {
679 fep->stats.rx_errors++;
680 fep->stats.rx_frame_errors++;
681 goto rx_processing_done;
682 }
683
684 /* Process the incoming frame.
685 */
686 fep->stats.rx_packets++;
687 pkt_len = bdp->cbd_datlen;
688 fep->stats.rx_bytes += pkt_len;
689 data = (__u8*)__va(bdp->cbd_bufaddr);
690
691 #ifdef CONFIG_FEC_PACKETHOOK
692 /* Packet hook ... */
693 if (fep->ph_rxhandler) {
694 if (((struct ethhdr *)data)->h_proto == fep->ph_proto) {
695 switch (fep->ph_rxhandler(data, pkt_len, regval,
696 fep->ph_priv)) {
697 case 1:
698 goto rx_processing_done;
699 break;
700 case 0:
701 break;
702 default:
703 fep->stats.rx_errors++;
704 goto rx_processing_done;
705 }
706 }
707 }
708
709 /* If it wasn't filtered - copy it to an sk buffer. */
710 #endif
711
712 /* This does 16 byte alignment, exactly what we need.
713 * The packet length includes FCS, but we don't want to
714 * include that when passing upstream as it messes up
715 * bridging applications.
716 */
717 skb = dev_alloc_skb(pkt_len-4);
718
719 if (skb == NULL) {
720 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
721 fep->stats.rx_dropped++;
722 } else {
723 skb->dev = dev;
724 skb_put(skb,pkt_len-4); /* Make room */
725 eth_copy_and_sum(skb,
726 (unsigned char *)__va(bdp->cbd_bufaddr),
727 pkt_len-4, 0);
728 skb->protocol=eth_type_trans(skb,dev);
729 netif_rx(skb);
730 }
731 rx_processing_done:
732
733 /* Clear the status flags for this buffer.
734 */
735 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
736
737 /* Mark the buffer empty.
738 */
739 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
740
741 /* Update BD pointer to next entry.
742 */
743 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
744 bdp = fep->rx_bd_base;
745 else
746 bdp++;
747
748 #if 1
749 /* Doing this here will keep the FEC running while we process
750 * incoming frames. On a heavily loaded network, we should be
751 * able to keep up at the expense of system resources.
752 */
753 fecp->fec_r_des_active = 0x01000000;
754 #endif
755 #ifdef CONFIG_FEC_PACKETHOOK
756 /* Re-read register. Not exactly guaranteed to be correct,
757 but... */
758 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
759 #endif
760 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
761 fep->cur_rx = (cbd_t *)bdp;
762
763 #if 0
764 /* Doing this here will allow us to process all frames in the
765 * ring before the FEC is allowed to put more there. On a heavily
766 * loaded network, some frames may be lost. Unfortunately, this
767 * increases the interrupt overhead since we can potentially work
768 * our way back to the interrupt return only to come right back
769 * here.
770 */
771 fecp->fec_r_des_active = 0x01000000;
772 #endif
773 }
774
775
776 #ifdef CONFIG_USE_MDIO
777 static void
778 fec_enet_mii(struct net_device *dev)
779 {
780 struct fec_enet_private *fep;
781 volatile fec_t *ep;
782 mii_list_t *mip;
783 uint mii_reg;
784
785 fep = (struct fec_enet_private *)dev->priv;
786 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
787 mii_reg = ep->fec_mii_data;
788
789 if ((mip = mii_head) == NULL) {
790 printk("MII and no head!\n");
791 return;
792 }
793
794 if (mip->mii_func != NULL)
795 (*(mip->mii_func))(mii_reg, dev);
796
797 mii_head = mip->mii_next;
798 mip->mii_next = mii_free;
799 mii_free = mip;
800
801 if ((mip = mii_head) != NULL) {
802 ep->fec_mii_data = mip->mii_regval;
803 }
804 }
805
806 static int
807 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
808 {
809 struct fec_enet_private *fep;
810 unsigned long flags;
811 mii_list_t *mip;
812 int retval;
813
814 /* Add PHY address to register command.
815 */
816 fep = dev->priv;
817 regval |= fep->phy_addr << 23;
818
819 retval = 0;
820
821 save_flags(flags);
822 cli();
823
824 if ((mip = mii_free) != NULL) {
825 mii_free = mip->mii_next;
826 mip->mii_regval = regval;
827 mip->mii_func = func;
828 mip->mii_next = NULL;
829 if (mii_head) {
830 mii_tail->mii_next = mip;
831 mii_tail = mip;
832 } else {
833 mii_head = mii_tail = mip;
834 (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
835 }
836 } else {
837 retval = 1;
838 }
839
840 restore_flags(flags);
841
842 return(retval);
843 }
844
845 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
846 {
847 int k;
848
849 if(!c)
850 return;
851
852 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
853 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
854 }
855
856 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
857 {
858 struct fec_enet_private *fep = dev->priv;
859 volatile uint *s = &(fep->phy_status);
860
861 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
862
863 if (mii_reg & 0x0004)
864 *s |= PHY_STAT_LINK;
865 if (mii_reg & 0x0010)
866 *s |= PHY_STAT_FAULT;
867 if (mii_reg & 0x0020)
868 *s |= PHY_STAT_ANC;
869 }
870
871 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
872 {
873 struct fec_enet_private *fep = dev->priv;
874 volatile uint *s = &(fep->phy_status);
875
876 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
877
878 if (mii_reg & 0x1000)
879 *s |= PHY_CONF_ANE;
880 if (mii_reg & 0x4000)
881 *s |= PHY_CONF_LOOP;
882 }
883
884 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
885 {
886 struct fec_enet_private *fep = dev->priv;
887 volatile uint *s = &(fep->phy_status);
888
889 *s &= ~(PHY_CONF_SPMASK);
890
891 if (mii_reg & 0x0020)
892 *s |= PHY_CONF_10HDX;
893 if (mii_reg & 0x0040)
894 *s |= PHY_CONF_10FDX;
895 if (mii_reg & 0x0080)
896 *s |= PHY_CONF_100HDX;
897 if (mii_reg & 0x00100)
898 *s |= PHY_CONF_100FDX;
899 }
900 #if 0
901 static void mii_disp_reg(uint mii_reg, struct net_device *dev)
902 {
903 printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff);
904 }
905 #endif
906
907 /* ------------------------------------------------------------------------- */
908 /* The Level one LXT970 is used by many boards */
909
910 #ifdef CONFIG_FEC_LXT970
911
912 #define MII_LXT970_MIRROR 16 /* Mirror register */
913 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
914 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
915 #define MII_LXT970_CONFIG 19 /* Configuration Register */
916 #define MII_LXT970_CSR 20 /* Chip Status Register */
917
918 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
919 {
920 struct fec_enet_private *fep = dev->priv;
921 volatile uint *s = &(fep->phy_status);
922
923 *s &= ~(PHY_STAT_SPMASK);
924
925 if (mii_reg & 0x0800) {
926 if (mii_reg & 0x1000)
927 *s |= PHY_STAT_100FDX;
928 else
929 *s |= PHY_STAT_100HDX;
930 }
931 else {
932 if (mii_reg & 0x1000)
933 *s |= PHY_STAT_10FDX;
934 else
935 *s |= PHY_STAT_10HDX;
936 }
937 }
938
939 static phy_info_t phy_info_lxt970 = {
940 0x07810000,
941 "LXT970",
942
943 (const phy_cmd_t []) { /* config */
944 #if 0
945 // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
946
947 /* Set default operation of 100-TX....for some reason
948 * some of these bits are set on power up, which is wrong.
949 */
950 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
951 #endif
952 { mk_mii_read(MII_REG_CR), mii_parse_cr },
953 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
954 { mk_mii_end, }
955 },
956 (const phy_cmd_t []) { /* startup - enable interrupts */
957 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
958 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
959 { mk_mii_end, }
960 },
961 (const phy_cmd_t []) { /* ack_int */
962 /* read SR and ISR to acknowledge */
963
964 { mk_mii_read(MII_REG_SR), mii_parse_sr },
965 { mk_mii_read(MII_LXT970_ISR), NULL },
966
967 /* find out the current status */
968
969 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
970 { mk_mii_end, }
971 },
972 (const phy_cmd_t []) { /* shutdown - disable interrupts */
973 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
974 { mk_mii_end, }
975 },
976 };
977
978 #endif /* CONFIG_FEC_LXT970 */
979
980 /* ------------------------------------------------------------------------- */
981 /* The Level one LXT971 is used on some of my custom boards */
982
983 #ifdef CONFIG_FEC_LXT971
984
985 /* register definitions for the 971 */
986
987 #define MII_LXT971_PCR 16 /* Port Control Register */
988 #define MII_LXT971_SR2 17 /* Status Register 2 */
989 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
990 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
991 #define MII_LXT971_LCR 20 /* LED Control Register */
992 #define MII_LXT971_TCR 30 /* Transmit Control Register */
993
994 /*
995 * I had some nice ideas of running the MDIO faster...
996 * The 971 should support 8MHz and I tried it, but things acted really
997 * weird, so 2.5 MHz ought to be enough for anyone...
998 */
999
1000 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1001 {
1002 struct fec_enet_private *fep = dev->priv;
1003 volatile uint *s = &(fep->phy_status);
1004
1005 *s &= ~(PHY_STAT_SPMASK);
1006
1007 if (mii_reg & 0x4000) {
1008 if (mii_reg & 0x0200)
1009 *s |= PHY_STAT_100FDX;
1010 else
1011 *s |= PHY_STAT_100HDX;
1012 }
1013 else {
1014 if (mii_reg & 0x0200)
1015 *s |= PHY_STAT_10FDX;
1016 else
1017 *s |= PHY_STAT_10HDX;
1018 }
1019 if (mii_reg & 0x0008)
1020 *s |= PHY_STAT_FAULT;
1021 }
1022
1023 static phy_info_t phy_info_lxt971 = {
1024 0x0001378e,
1025 "LXT971",
1026
1027 (const phy_cmd_t []) { /* config */
1028 // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1029 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1030 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1031 { mk_mii_end, }
1032 },
1033 (const phy_cmd_t []) { /* startup - enable interrupts */
1034 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1035 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1036
1037 /* Somehow does the 971 tell me that the link is down
1038 * the first read after power-up.
1039 * read here to get a valid value in ack_int */
1040
1041 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1042 { mk_mii_end, }
1043 },
1044 (const phy_cmd_t []) { /* ack_int */
1045 /* find out the current status */
1046
1047 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1048 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1049
1050 /* we only need to read ISR to acknowledge */
1051
1052 { mk_mii_read(MII_LXT971_ISR), NULL },
1053 { mk_mii_end, }
1054 },
1055 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1056 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1057 { mk_mii_end, }
1058 },
1059 };
1060
1061 #endif /* CONFIG_FEC_LXT970 */
1062
1063
1064 /* ------------------------------------------------------------------------- */
1065 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
1066
1067 #ifdef CONFIG_FEC_QS6612
1068
1069 /* register definitions */
1070
1071 #define MII_QS6612_MCR 17 /* Mode Control Register */
1072 #define MII_QS6612_FTR 27 /* Factory Test Register */
1073 #define MII_QS6612_MCO 28 /* Misc. Control Register */
1074 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
1075 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1076 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1077
1078 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1079 {
1080 struct fec_enet_private *fep = dev->priv;
1081 volatile uint *s = &(fep->phy_status);
1082
1083 *s &= ~(PHY_STAT_SPMASK);
1084
1085 switch((mii_reg >> 2) & 7) {
1086 case 1: *s |= PHY_STAT_10HDX; break;
1087 case 2: *s |= PHY_STAT_100HDX; break;
1088 case 5: *s |= PHY_STAT_10FDX; break;
1089 case 6: *s |= PHY_STAT_100FDX; break;
1090 }
1091 }
1092
1093 static phy_info_t phy_info_qs6612 = {
1094 0x00181440,
1095 "QS6612",
1096
1097 (const phy_cmd_t []) { /* config */
1098 // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1099
1100 /* The PHY powers up isolated on the RPX,
1101 * so send a command to allow operation.
1102 */
1103
1104 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1105
1106 /* parse cr and anar to get some info */
1107
1108 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1109 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1110 { mk_mii_end, }
1111 },
1112 (const phy_cmd_t []) { /* startup - enable interrupts */
1113 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1114 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1115 { mk_mii_end, }
1116 },
1117 (const phy_cmd_t []) { /* ack_int */
1118
1119 /* we need to read ISR, SR and ANER to acknowledge */
1120
1121 { mk_mii_read(MII_QS6612_ISR), NULL },
1122 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1123 { mk_mii_read(MII_REG_ANER), NULL },
1124
1125 /* read pcr to get info */
1126
1127 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1128 { mk_mii_end, }
1129 },
1130 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1131 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1132 { mk_mii_end, }
1133 },
1134 };
1135
1136
1137 #endif /* CONFIG_FEC_QS6612 */
1138
1139
1140 static phy_info_t *phy_info[] = {
1141
1142 #ifdef CONFIG_FEC_LXT970
1143 &phy_info_lxt970,
1144 #endif /* CONFIG_FEC_LXT970 */
1145
1146 #ifdef CONFIG_FEC_LXT971
1147 &phy_info_lxt971,
1148 #endif /* CONFIG_FEC_LXT971 */
1149
1150 #ifdef CONFIG_FEC_QS6612
1151 &phy_info_qs6612,
1152 #endif /* CONFIG_FEC_LXT971 */
1153
1154 NULL
1155 };
1156
1157 static void mii_display_status(struct net_device *dev)
1158 {
1159 struct fec_enet_private *fep = dev->priv;
1160 volatile uint *s = &(fep->phy_status);
1161
1162 if (!fep->link && !fep->old_link) {
1163 /* Link is still down - don't print anything */
1164 return;
1165 }
1166
1167 printk("%s: status: ", dev->name);
1168
1169 if (!fep->link) {
1170 printk("link down");
1171 } else {
1172 printk("link up");
1173
1174 switch(*s & PHY_STAT_SPMASK) {
1175 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1176 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1177 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1178 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1179 default:
1180 printk(", Unknown speed/duplex");
1181 }
1182
1183 if (*s & PHY_STAT_ANC)
1184 printk(", auto-negotiation complete");
1185 }
1186
1187 if (*s & PHY_STAT_FAULT)
1188 printk(", remote fault");
1189
1190 printk(".\n");
1191 }
1192
1193 static void mii_display_config(struct net_device *dev)
1194 {
1195 struct fec_enet_private *fep = dev->priv;
1196 volatile uint *s = &(fep->phy_status);
1197
1198 printk("%s: config: auto-negotiation ", dev->name);
1199
1200 if (*s & PHY_CONF_ANE)
1201 printk("on");
1202 else
1203 printk("off");
1204
1205 if (*s & PHY_CONF_100FDX)
1206 printk(", 100FDX");
1207 if (*s & PHY_CONF_100HDX)
1208 printk(", 100HDX");
1209 if (*s & PHY_CONF_10FDX)
1210 printk(", 10FDX");
1211 if (*s & PHY_CONF_10HDX)
1212 printk(", 10HDX");
1213 if (!(*s & PHY_CONF_SPMASK))
1214 printk(", No speed/duplex selected?");
1215
1216 if (*s & PHY_CONF_LOOP)
1217 printk(", loopback enabled");
1218
1219 printk(".\n");
1220
1221 fep->sequence_done = 1;
1222 }
1223
1224 static void mii_relink(struct net_device *dev)
1225 {
1226 struct fec_enet_private *fep = dev->priv;
1227 int duplex;
1228
1229 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1230 mii_display_status(dev);
1231 fep->old_link = fep->link;
1232
1233 if (fep->link) {
1234 duplex = 0;
1235 if (fep->phy_status
1236 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1237 duplex = 1;
1238 fec_restart(dev, duplex);
1239 }
1240 else
1241 fec_stop(dev);
1242
1243 #if 0
1244 enable_irq(fep->mii_irq);
1245 #endif
1246
1247 }
1248
1249 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1250 {
1251 struct fec_enet_private *fep = dev->priv;
1252
1253 fep->phy_task.routine = (void *)mii_relink;
1254 fep->phy_task.data = dev;
1255 schedule_task(&fep->phy_task);
1256 }
1257
1258 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1259 {
1260 struct fec_enet_private *fep = dev->priv;
1261
1262 fep->phy_task.routine = (void *)mii_display_config;
1263 fep->phy_task.data = dev;
1264 schedule_task(&fep->phy_task);
1265 }
1266
1267
1268
1269 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1270 { mk_mii_end, } };
1271 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1272 { mk_mii_end, } };
1273
1274
1275
1276 /* Read remainder of PHY ID.
1277 */
1278 static void
1279 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1280 {
1281 struct fec_enet_private *fep;
1282 int i;
1283
1284 fep = dev->priv;
1285 fep->phy_id |= (mii_reg & 0xffff);
1286
1287 for(i = 0; phy_info[i]; i++)
1288 if(phy_info[i]->id == (fep->phy_id >> 4))
1289 break;
1290
1291 if(!phy_info[i])
1292 panic("%s: PHY id 0x%08x is not supported!\n",
1293 dev->name, fep->phy_id);
1294
1295 fep->phy = phy_info[i];
1296 fep->phy_id_done = 1;
1297
1298 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1299 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1300 }
1301
1302 /* Scan all of the MII PHY addresses looking for someone to respond
1303 * with a valid ID. This usually happens quickly.
1304 */
1305 static void
1306 mii_discover_phy(uint mii_reg, struct net_device *dev)
1307 {
1308 struct fec_enet_private *fep;
1309 uint phytype;
1310
1311 fep = dev->priv;
1312
1313 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1314
1315 /* Got first part of ID, now get remainder.
1316 */
1317 fep->phy_id = phytype << 16;
1318 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1319 } else {
1320 fep->phy_addr++;
1321 if (fep->phy_addr < 32) {
1322 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1323 mii_discover_phy);
1324 } else {
1325 printk("fec: No PHY device found.\n");
1326 }
1327 }
1328 }
1329 #endif /* CONFIG_USE_MDIO */
1330
1331 /* This interrupt occurs when the PHY detects a link change.
1332 */
1333 static void
1334 #ifdef CONFIG_RPXCLASSIC
1335 mii_link_interrupt(void *dev_id)
1336 #else
1337 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1338 #endif
1339 {
1340 #ifdef CONFIG_USE_MDIO
1341 struct net_device *dev = dev_id;
1342 struct fec_enet_private *fep = dev->priv;
1343 volatile immap_t *immap = (immap_t *)IMAP_ADDR;
1344 volatile fec_t *fecp = &(immap->im_cpm.cp_fec);
1345 unsigned int ecntrl = fecp->fec_ecntrl;
1346
1347 /* We need the FEC enabled to access the MII
1348 */
1349 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1350 fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN;
1351 }
1352 #endif /* CONFIG_USE_MDIO */
1353
1354 #if 0
1355 disable_irq(fep->mii_irq); /* disable now, enable later */
1356 #endif
1357
1358
1359 #ifdef CONFIG_USE_MDIO
1360 mii_do_cmd(dev, fep->phy->ack_int);
1361 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1362
1363 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1364 fecp->fec_ecntrl = ecntrl; /* restore old settings */
1365 }
1366 #else
1367 printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
1368 #endif /* CONFIG_USE_MDIO */
1369
1370 }
1371
1372 static int
1373 fec_enet_open(struct net_device *dev)
1374 {
1375 struct fec_enet_private *fep = dev->priv;
1376
1377 /* I should reset the ring buffers here, but I don't yet know
1378 * a simple way to do that.
1379 */
1380
1381 #ifdef CONFIG_USE_MDIO
1382 fep->sequence_done = 0;
1383 fep->link = 0;
1384
1385 if (fep->phy) {
1386 mii_do_cmd(dev, fep->phy->ack_int);
1387 mii_do_cmd(dev, fep->phy->config);
1388 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1389 while(!fep->sequence_done)
1390 schedule();
1391
1392 mii_do_cmd(dev, fep->phy->startup);
1393 netif_start_queue(dev);
1394 return 0; /* Success */
1395 }
1396 return -ENODEV; /* No PHY we understand */
1397 #else
1398 fep->link = 1;
1399 netif_start_queue(dev);
1400 return 0; /* Success */
1401 #endif /* CONFIG_USE_MDIO */
1402
1403 }
1404
1405 static int
1406 fec_enet_close(struct net_device *dev)
1407 {
1408 /* Don't know what to do yet.
1409 */
1410 netif_stop_queue(dev);
1411 fec_stop(dev);
1412
1413 return 0;
1414 }
1415
1416 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1417 {
1418 struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv;
1419
1420 return &fep->stats;
1421 }
1422
1423 /* Set or clear the multicast filter for this adaptor.
1424 * Skeleton taken from sunlance driver.
1425 * The CPM Ethernet implementation allows Multicast as well as individual
1426 * MAC address filtering. Some of the drivers check to make sure it is
1427 * a group multicast address, and discard those that are not. I guess I
1428 * will do the same for now, but just remove the test if you want
1429 * individual filtering as well (do the upper net layers want or support
1430 * this kind of feature?).
1431 */
1432
1433 static void set_multicast_list(struct net_device *dev)
1434 {
1435 struct fec_enet_private *fep;
1436 volatile fec_t *ep;
1437
1438 fep = (struct fec_enet_private *)dev->priv;
1439 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
1440
1441 if (dev->flags&IFF_PROMISC) {
1442
1443 /* Log any net taps. */
1444 printk("%s: Promiscuous mode enabled.\n", dev->name);
1445 ep->fec_r_cntrl |= FEC_RCNTRL_PROM;
1446 } else {
1447
1448 ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM;
1449
1450 if (dev->flags & IFF_ALLMULTI) {
1451 /* Catch all multicast addresses, so set the
1452 * filter to all 1's.
1453 */
1454 ep->fec_hash_table_high = 0xffffffff;
1455 ep->fec_hash_table_low = 0xffffffff;
1456 }
1457 #if 0
1458 else {
1459 /* Clear filter and add the addresses in the list.
1460 */
1461 ep->sen_gaddr1 = 0;
1462 ep->sen_gaddr2 = 0;
1463 ep->sen_gaddr3 = 0;
1464 ep->sen_gaddr4 = 0;
1465
1466 dmi = dev->mc_list;
1467
1468 for (i=0; i<dev->mc_count; i++) {
1469
1470 /* Only support group multicast for now.
1471 */
1472 if (!(dmi->dmi_addr[0] & 1))
1473 continue;
1474
1475 /* The address in dmi_addr is LSB first,
1476 * and taddr is MSB first. We have to
1477 * copy bytes MSB first from dmi_addr.
1478 */
1479 mcptr = (u_char *)dmi->dmi_addr + 5;
1480 tdptr = (u_char *)&ep->sen_taddrh;
1481 for (j=0; j<6; j++)
1482 *tdptr++ = *mcptr--;
1483
1484 /* Ask CPM to run CRC and set bit in
1485 * filter mask.
1486 */
1487 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG;
1488 /* this delay is necessary here -- Cort */
1489 udelay(10);
1490 while (cpmp->cp_cpcr & CPM_CR_FLG);
1491 }
1492 }
1493 #endif
1494 }
1495 }
1496
1497 /* Initialize the FEC Ethernet on 860T.
1498 */
1499 int __init fec_enet_init(void)
1500 {
1501 struct net_device *dev;
1502 struct fec_enet_private *fep;
1503 int i, j;
1504 unsigned char *eap, *iap;
1505 unsigned long mem_addr;
1506 pte_t *pte;
1507 volatile cbd_t *bdp;
1508 cbd_t *cbd_base;
1509 volatile immap_t *immap;
1510 volatile fec_t *fecp;
1511 bd_t *bd;
1512 #ifdef CONFIG_SCC_ENET
1513 unsigned char tmpaddr[6];
1514 #endif
1515
1516 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1517
1518 bd = (bd_t *)__res;
1519
1520 /* Allocate some private information.
1521 */
1522 fep = (struct fec_enet_private *)kmalloc(sizeof(*fep), GFP_KERNEL);
1523 if (fep == NULL)
1524 return -ENOMEM;
1525
1526 __clear_user(fep,sizeof(*fep));
1527
1528 /* Create an Ethernet device instance.
1529 */
1530 dev = init_etherdev(0, 0);
1531
1532 fecp = &(immap->im_cpm.cp_fec);
1533
1534 /* Whack a reset. We should wait for this.
1535 */
1536 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1537 for (i = 0;
1538 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1539 ++i) {
1540 udelay(1);
1541 }
1542 if (i == FEC_RESET_DELAY) {
1543 printk ("FEC Reset timeout!\n");
1544 }
1545
1546 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1547 * this needs some work to get unique addresses.
1548 */
1549 eap = (unsigned char *)my_enet_addr;
1550 iap = bd->bi_enetaddr;
1551
1552 #ifdef CONFIG_SCC_ENET
1553 /*
1554 * If a board has Ethernet configured both on a SCC and the
1555 * FEC, it needs (at least) 2 MAC addresses (we know that Sun
1556 * disagrees, but anyway). For the FEC port, we create
1557 * another address by setting one of the address bits above
1558 * something that would have (up to now) been allocated.
1559 */
1560 for (i=0; i<6; i++)
1561 tmpaddr[i] = *iap++;
1562 tmpaddr[3] |= 0x80;
1563 iap = tmpaddr;
1564 #endif
1565
1566 for (i=0; i<6; i++) {
1567 dev->dev_addr[i] = *eap++ = *iap++;
1568 }
1569
1570 /* Allocate memory for buffer descriptors.
1571 */
1572 if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1573 printk("FEC init error. Need more space.\n");
1574 printk("FEC initialization failed.\n");
1575 return 1;
1576 }
1577 mem_addr = __get_free_page(GFP_KERNEL);
1578 cbd_base = (cbd_t *)mem_addr;
1579
1580 /* Make it uncached.
1581 */
1582 pte = va_to_pte(mem_addr);
1583 pte_val(*pte) |= _PAGE_NO_CACHE;
1584 flush_tlb_page(init_mm.mmap, mem_addr);
1585
1586 /* Set receive and transmit descriptor base.
1587 */
1588 fep->rx_bd_base = cbd_base;
1589 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1590
1591 fep->skb_cur = fep->skb_dirty = 0;
1592
1593 /* Initialize the receive buffer descriptors.
1594 */
1595 bdp = fep->rx_bd_base;
1596 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1597
1598 /* Allocate a page.
1599 */
1600 mem_addr = __get_free_page(GFP_KERNEL);
1601
1602 /* Make it uncached.
1603 */
1604 pte = va_to_pte(mem_addr);
1605 pte_val(*pte) |= _PAGE_NO_CACHE;
1606 flush_tlb_page(init_mm.mmap, mem_addr);
1607
1608 /* Initialize the BD for every fragment in the page.
1609 */
1610 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1611 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1612 bdp->cbd_bufaddr = __pa(mem_addr);
1613 mem_addr += FEC_ENET_RX_FRSIZE;
1614 bdp++;
1615 }
1616 }
1617
1618 /* Set the last buffer to wrap.
1619 */
1620 bdp--;
1621 bdp->cbd_sc |= BD_SC_WRAP;
1622
1623 #ifdef CONFIG_FEC_PACKETHOOK
1624 fep->ph_lock = 0;
1625 fep->ph_rxhandler = fep->ph_txhandler = NULL;
1626 fep->ph_proto = 0;
1627 fep->ph_regaddr = NULL;
1628 fep->ph_priv = NULL;
1629 #endif
1630
1631 /* Install our interrupt handler.
1632 */
1633 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1634 panic("Could not allocate FEC IRQ!");
1635
1636 #ifdef CONFIG_RPXCLASSIC
1637 /* Make Port C, bit 15 an input that causes interrupts.
1638 */
1639 immap->im_ioport.iop_pcpar &= ~0x0001;
1640 immap->im_ioport.iop_pcdir &= ~0x0001;
1641 immap->im_ioport.iop_pcso &= ~0x0001;
1642 immap->im_ioport.iop_pcint |= 0x0001;
1643 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1644
1645 /* Make LEDS reflect Link status.
1646 */
1647 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1648 #endif
1649
1650 #ifdef PHY_INTERRUPT
1651 if (request_8xxirq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0)
1652 panic("Could not allocate MII IRQ!");
1653
1654 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
1655 (0x80000000 >> PHY_INTERRUPT);
1656 #endif
1657
1658 dev->base_addr = (unsigned long)fecp;
1659 dev->priv = fep;
1660
1661 /* The FEC Ethernet specific entries in the device structure. */
1662 dev->open = fec_enet_open;
1663 dev->hard_start_xmit = fec_enet_start_xmit;
1664 dev->tx_timeout = fec_timeout;
1665 dev->watchdog_timeo = TX_TIMEOUT;
1666 dev->stop = fec_enet_close;
1667 dev->get_stats = fec_enet_get_stats;
1668 dev->set_multicast_list = set_multicast_list;
1669
1670 #ifdef CONFIG_USE_MDIO
1671 for (i=0; i<NMII-1; i++)
1672 mii_cmds[i].mii_next = &mii_cmds[i+1];
1673 mii_free = mii_cmds;
1674 #endif /* CONFIG_USE_MDIO */
1675
1676 /* Configure all of port D for MII.
1677 */
1678 immap->im_ioport.iop_pdpar = 0x1fff;
1679
1680 /* Bits moved from Rev. D onward.
1681 */
1682 if ((mfspr(IMMR) & 0xffff) < 0x0501)
1683 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1684 else
1685 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1686
1687 #ifdef CONFIG_USE_MDIO
1688 /* Set MII speed to 2.5 MHz
1689 */
1690 fecp->fec_mii_speed = fep->phy_speed =
1691 (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1;
1692 #else
1693 fecp->fec_mii_speed = 0; /* turn off MDIO */
1694 #endif /* CONFIG_USE_MDIO */
1695
1696 printk ("%s: FEC ENET Version 0.2, FEC irq %d"
1697 #ifdef PHY_INTERRUPT
1698 ", MII irq %d"
1699 #endif
1700 ", addr ",
1701 dev->name, FEC_INTERRUPT
1702 #ifdef PHY_INTERRUPT
1703 , PHY_INTERRUPT
1704 #endif
1705 );
1706 for (i=0; i<6; i++)
1707 printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':');
1708
1709 #ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */
1710 fec_restart (dev, 1);
1711 #else /* always use half duplex mode only */
1712 fec_restart (dev, 0);
1713 #endif
1714
1715 #ifdef CONFIG_USE_MDIO
1716 /* Queue up command to detect the PHY and initialize the
1717 * remainder of the interface.
1718 */
1719 fep->phy_id_done = 0;
1720 fep->phy_addr = 0;
1721 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1722 #endif /* CONFIG_USE_MDIO */
1723
1724 return 0;
1725 }
1726
1727 /* This function is called to start or restart the FEC during a link
1728 * change. This only happens when switching between half and full
1729 * duplex.
1730 */
1731 static void
1732 fec_restart(struct net_device *dev, int duplex)
1733 {
1734 struct fec_enet_private *fep;
1735 int i;
1736 volatile cbd_t *bdp;
1737 volatile immap_t *immap;
1738 volatile fec_t *fecp;
1739
1740 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1741
1742 fecp = &(immap->im_cpm.cp_fec);
1743
1744 fep = dev->priv;
1745
1746 /* Whack a reset. We should wait for this.
1747 */
1748 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1749 for (i = 0;
1750 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1751 ++i) {
1752 udelay(1);
1753 }
1754 if (i == FEC_RESET_DELAY) {
1755 printk ("FEC Reset timeout!\n");
1756 }
1757
1758 /* Set station address.
1759 */
1760 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1761 fecp->fec_addr_high = my_enet_addr[2];
1762
1763 /* Reset all multicast.
1764 */
1765 fecp->fec_hash_table_high = 0;
1766 fecp->fec_hash_table_low = 0;
1767
1768 /* Set maximum receive buffer size.
1769 */
1770 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1771 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1772
1773 /* Set receive and transmit descriptor base.
1774 */
1775 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
1776 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
1777
1778 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1779 fep->cur_rx = fep->rx_bd_base;
1780
1781 /* Reset SKB transmit buffers.
1782 */
1783 fep->skb_cur = fep->skb_dirty = 0;
1784 for (i=0; i<=TX_RING_MOD_MASK; i++) {
1785 if (fep->tx_skbuff[i] != NULL) {
1786 dev_kfree_skb(fep->tx_skbuff[i]);
1787 fep->tx_skbuff[i] = NULL;
1788 }
1789 }
1790
1791 /* Initialize the receive buffer descriptors.
1792 */
1793 bdp = fep->rx_bd_base;
1794 for (i=0; i<RX_RING_SIZE; i++) {
1795
1796 /* Initialize the BD for every fragment in the page.
1797 */
1798 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1799 bdp++;
1800 }
1801
1802 /* Set the last buffer to wrap.
1803 */
1804 bdp--;
1805 bdp->cbd_sc |= BD_SC_WRAP;
1806
1807 /* ...and the same for transmmit.
1808 */
1809 bdp = fep->tx_bd_base;
1810 for (i=0; i<TX_RING_SIZE; i++) {
1811
1812 /* Initialize the BD for every fragment in the page.
1813 */
1814 bdp->cbd_sc = 0;
1815 bdp->cbd_bufaddr = 0;
1816 bdp++;
1817 }
1818
1819 /* Set the last buffer to wrap.
1820 */
1821 bdp--;
1822 bdp->cbd_sc |= BD_SC_WRAP;
1823
1824 /* Enable MII mode.
1825 */
1826 if (duplex) {
1827 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */
1828 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */
1829 }
1830 else {
1831 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
1832 fecp->fec_x_cntrl = 0;
1833 }
1834 fep->full_duplex = duplex;
1835
1836 /* Enable big endian and don't care about SDMA FC.
1837 */
1838 fecp->fec_fun_code = 0x78000000;
1839
1840 #ifdef CONFIG_USE_MDIO
1841 /* Set MII speed.
1842 */
1843 fecp->fec_mii_speed = fep->phy_speed;
1844 #endif /* CONFIG_USE_MDIO */
1845
1846 /* Clear any outstanding interrupt.
1847 */
1848 fecp->fec_ievent = 0xffc0;
1849
1850 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1851
1852 /* Enable interrupts we wish to service.
1853 */
1854 fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB |
1855 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII );
1856
1857 /* And last, enable the transmit and receive processing.
1858 */
1859 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
1860 fecp->fec_r_des_active = 0x01000000;
1861 }
1862
1863 static void
1864 fec_stop(struct net_device *dev)
1865 {
1866 volatile immap_t *immap;
1867 volatile fec_t *fecp;
1868 struct fec_enet_private *fep;
1869 int i;
1870
1871 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1872
1873 fecp = &(immap->im_cpm.cp_fec);
1874
1875 if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0)
1876 return; /* already down */
1877
1878 fep = dev->priv;
1879
1880
1881 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
1882
1883 for (i = 0;
1884 ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY);
1885 ++i) {
1886 udelay(1);
1887 }
1888 if (i == FEC_RESET_DELAY) {
1889 printk ("FEC timeout on graceful transmit stop\n");
1890 }
1891
1892 /* Clear outstanding MII command interrupts.
1893 */
1894 fecp->fec_ievent = FEC_ENET_MII;
1895
1896 /* Enable MII command finished interrupt
1897 */
1898 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1899 fecp->fec_imask = FEC_ENET_MII;
1900
1901 #ifdef CONFIG_USE_MDIO
1902 /* Set MII speed.
1903 */
1904 fecp->fec_mii_speed = fep->phy_speed;
1905 #endif /* CONFIG_USE_MDIO */
1906
1907 /* Disable FEC
1908 */
1909 fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN);
1910 }
1911