File: /usr/src/linux/arch/ppc/boot/mbx/pci.c
1 /*
2 * BK Id: SCCS/s.pci.c 1.6 05/18/01 15:17:06 cort
3 */
4 /* Stand alone funtions for QSpan Tundra support.
5 */
6 #include <linux/types.h>
7 #include <linux/kernel.h>
8 #include <linux/pci.h>
9 #include <asm/mpc8xx.h>
10
11 /* To map PCI devices, you first write 0xffffffff into the device
12 * base address registers. When the register is read back, the
13 * number of most significant '1' bits describes the amount of address
14 * space needed for mapping. If the most significant bit is not set,
15 * either the device does not use that address register, or it has
16 * a fixed address that we can't change. After the address is assigned,
17 * the command register has to be written to enable the card.
18 */
19 typedef struct {
20 u_char pci_bus;
21 u_char pci_devfn;
22 ushort pci_command;
23 uint pci_addrs[6];
24 } pci_map_t;
25
26 /* We should probably dynamically allocate these structures.
27 */
28 #define MAX_PCI_DEVS 32
29 int pci_dev_cnt;
30 pci_map_t pci_map[MAX_PCI_DEVS];
31
32 void pci_conf_write(int bus, int device, int func, int reg, uint writeval);
33 void pci_conf_read(int bus, int device, int func, int reg, void *readval);
34 void probe_addresses(int bus, int devfn);
35 void map_pci_addrs(void);
36
37 /* This is a really stripped version of PCI bus scan. All we are
38 * looking for are devices that exist.
39 */
40 pci_scanner(int addr_probe)
41 {
42 unsigned int devfn, l, max, class, bus_number;
43 unsigned char cmd, irq, tmp, hdr_type, is_multi;
44 int reg;
45
46 is_multi = 0;
47 bus_number = 0;
48 for (devfn = 0; devfn < 0xff; ++devfn) {
49 /* The device numbers are comprised of upper 5 bits of
50 * device number and lower 3 bits of multi-function number.
51 */
52 if ((devfn & 7) && !is_multi) {
53 /* Don't scan multifunction addresses if this is
54 * not a multifunction device.
55 */
56 continue;
57 }
58
59 /* Read the header to determine card type.
60 */
61 qs_pci_read_config_byte(bus_number, devfn, PCI_HEADER_TYPE,
62 &hdr_type);
63
64 /* If this is a base device number, check the header to
65 * determine if it is mulifunction.
66 */
67 if ((devfn & 7) == 0)
68 is_multi = hdr_type & 0x80;
69
70 /* Check to see if the board is really in the slot.
71 */
72 qs_pci_read_config_dword(bus_number, devfn, PCI_VENDOR_ID, &l);
73 /* some broken boards return 0 if a slot is empty: */
74 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff ||
75 l == 0xffff0000) {
76 /* Nothing there.
77 */
78 is_multi = 0;
79 continue;
80 }
81
82 /* If we are not performing an address probe,
83 * just simply print out some information.
84 */
85 if (!addr_probe) {
86 qs_pci_read_config_dword(bus_number, devfn,
87 PCI_CLASS_REVISION, &class);
88
89 class >>= 8; /* upper 3 bytes */
90
91 #if 0
92 printf("Found (%3d:%d): vendor 0x%04x, device 0x%04x, class 0x%06x\n",
93 (devfn >> 3), (devfn & 7),
94 (l & 0xffff), (l >> 16) & 0xffff, class);
95 #else
96 puts("Found ("); puthex(devfn >> 3);
97 puts(":"); puthex(devfn & 7);
98 puts("): vendor "); puthex(l & 0xffff);
99 puts(", device "); puthex((l >> 16) & 0xffff);
100 puts(", class "); puthex(class); puts("\n");
101 #endif
102 }
103 else {
104 /* If this is a "normal" device, build address list.
105 */
106 if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL)
107 probe_addresses(bus_number, devfn);
108 }
109 }
110
111 /* Now map the boards.
112 */
113 if (addr_probe)
114 map_pci_addrs();
115 }
116
117 /* Probe addresses for the specified device. This is a destructive
118 * operation because it writes the registers.
119 */
120 void
121 probe_addresses(bus, devfn)
122 {
123 int i;
124 uint pciaddr;
125 ushort pcicmd;
126 pci_map_t *pm;
127
128 if (pci_dev_cnt >= MAX_PCI_DEVS) {
129 puts("Too many PCI devices\n");
130 return;
131 }
132
133 pm = &pci_map[pci_dev_cnt++];
134
135 pm->pci_bus = bus;
136 pm->pci_devfn = devfn;
137
138 for (i=0; i<6; i++) {
139 qs_pci_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4), -1);
140 qs_pci_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4),
141 &pciaddr);
142 pm->pci_addrs[i] = pciaddr;
143 qs_pci_read_config_word(bus, devfn, PCI_COMMAND, &pcicmd);
144 pm->pci_command = pcicmd;
145 }
146 }
147
148 /* Map the cards into the PCI space. The PCI has separate memory
149 * and I/O spaces. In addition, some memory devices require mapping
150 * below 1M. The least significant 4 bits of the address register
151 * provide information. If this is an I/O device, only the LS bit
152 * is used to indicate that, so I/O devices can be mapped to a two byte
153 * boundard. Memory addresses can be mapped to a 32 byte boundary.
154 * The QSpan implementations usually have a 1Gbyte space for each
155 * memory and I/O spaces.
156 *
157 * This isn't a terribly fancy algorithm. I just map the spaces from
158 * the top starting with the largest address space. When finished,
159 * the registers are written and the card enabled.
160 *
161 * While the Tundra can map a large address space on most boards, we
162 * need to be careful because it may overlap other devices (like IMMR).
163 */
164 #define MEMORY_SPACE_SIZE 0x20000000
165 #define IO_SPACE_SIZE 0x20000000
166
167 void
168 map_pci_addrs()
169 {
170 uint pci_mem_top, pci_mem_low;
171 uint pci_io_top;
172 uint addr_mask, reg_addr, space;
173 int i, j;
174 pci_map_t *pm;
175
176 pci_mem_top = MEMORY_SPACE_SIZE;
177 pci_io_top = IO_SPACE_SIZE;
178 pci_mem_low = (1 * 1024 * 1024); /* Below one meg addresses */
179
180 /* We can't map anything more than the maximum space, but test
181 * for it anyway to catch devices out of range.
182 */
183 addr_mask = 0x80000000;
184
185 do {
186 space = (~addr_mask) + 1; /* Size of the space */
187 for (i=0; i<pci_dev_cnt; i++) {
188 pm = &pci_map[i];
189 for (j=0; j<6; j++) {
190 /* If the MS bit is not set, this has either
191 * already been mapped, or is not used.
192 */
193 reg_addr = pm->pci_addrs[j];
194 if ((reg_addr & 0x80000000) == 0)
195 continue;
196 if (reg_addr & PCI_BASE_ADDRESS_SPACE_IO) {
197 if ((reg_addr & PCI_BASE_ADDRESS_IO_MASK) != addr_mask)
198 continue;
199 if (pci_io_top < space) {
200 puts("Out of PCI I/O space\n");
201 }
202 else {
203 pci_io_top -= space;
204 pm->pci_addrs[j] = pci_io_top;
205 pm->pci_command |= PCI_COMMAND_IO;
206 }
207 }
208 else {
209 if ((reg_addr & PCI_BASE_ADDRESS_MEM_MASK) != addr_mask)
210 continue;
211
212 /* Memory space. Test if below 1M.
213 */
214 if (reg_addr & PCI_BASE_ADDRESS_MEM_TYPE_1M) {
215 if (pci_mem_low < space) {
216 puts("Out of PCI 1M space\n");
217 }
218 else {
219 pci_mem_low -= space;
220 pm->pci_addrs[j] = pci_mem_low;
221 }
222 }
223 else {
224 if (pci_mem_top < space) {
225 puts("Out of PCI Mem space\n");
226 }
227 else {
228 pci_mem_top -= space;
229 pm->pci_addrs[j] = pci_mem_top;
230 }
231 }
232 pm->pci_command |= PCI_COMMAND_MEMORY;
233 }
234 }
235 }
236 addr_mask >>= 1;
237 addr_mask |= 0x80000000;
238 } while (addr_mask != 0xfffffffe);
239
240 /* Now, run the list one more time and map everything.
241 */
242 for (i=0; i<pci_dev_cnt; i++) {
243 pm = &pci_map[i];
244 for (j=0; j<6; j++) {
245 qs_pci_write_config_dword(pm->pci_bus, pm->pci_devfn,
246 PCI_BASE_ADDRESS_0 + (j * 4), pm->pci_addrs[j]);
247 }
248
249 /* Enable memory or address mapping.
250 */
251 qs_pci_write_config_word(pm->pci_bus, pm->pci_devfn, PCI_COMMAND,
252 pm->pci_command);
253 }
254 }
255
256