File: /usr/src/linux/arch/ppc/boot/mbx/qspan_pci.c
1 /*
2 * BK Id: SCCS/s.qspan_pci.c 1.6 05/18/01 15:17:06 cort
3 */
4 /*
5 * LinuxPPC arch/ppc/kernel/qspan_pci.c Dan Malek (dmalek@jlc.net)
6 *
7 * QSpan Motorola bus to PCI bridge. The config address register
8 * is located 0x500 from the base of the bridge control/status registers.
9 * The data register is located at 0x504.
10 * This is a two step operation. First, the address register is written,
11 * then the data register is read/written as required.
12 * I don't know what to do about interrupts (yet).
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <asm/mpc8xx.h>
19
20 /*
21 * When reading the configuration space, if something does not respond
22 * the bus times out and we get a machine check interrupt. So, the
23 * good ol' exception tables come to mind to trap it and return some
24 * value.
25 *
26 * On an error we just return a -1, since that is what the caller wants
27 * returned if nothing is present. I copied this from __get_user_asm,
28 * with the only difference of returning -1 instead of EFAULT.
29 * There is an associated hack in the machine check trap code.
30 *
31 * The QSPAN is also a big endian device, that is it makes the PCI
32 * look big endian to us. This presents a problem for the Linux PCI
33 * functions, which assume little endian. For example, we see the
34 * first 32-bit word like this:
35 * ------------------------
36 * | Device ID | Vendor ID |
37 * ------------------------
38 * If we read/write as a double word, that's OK. But in our world,
39 * when read as a word, device ID is at location 0, not location 2 as
40 * the little endian PCI would believe. We have to switch bits in
41 * the PCI addresses given to us to get the data to/from the correct
42 * byte lanes.
43 *
44 * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5.
45 * It always forces the MS bit to zero. Therefore, dev_fn values
46 * greater than 128 are returned as "no device found" errors.
47 *
48 * The QSPAN can only perform long word (32-bit) configuration cycles.
49 * The "offset" must have the two LS bits set to zero. Read operations
50 * require we read the entire word and then sort out what should be
51 * returned. Write operations other than long word require that we
52 * read the long word, update the proper word or byte, then write the
53 * entire long word back.
54 *
55 * PCI Bridge hack. We assume (correctly) that bus 0 is the primary
56 * PCI bus from the QSPAN. If we are called with a bus number other
57 * than zero, we create a Type 1 configuration access that a downstream
58 * PCI bridge will interpret.
59 */
60
61 #define __get_pci_config(x, addr, op) \
62 __asm__ __volatile__( \
63 "1: "op" %0,0(%1)\n" \
64 " eieio\n" \
65 "2:\n" \
66 ".section .fixup,\"ax\"\n" \
67 "3: li %0,-1\n" \
68 " b 2b\n" \
69 ".section __ex_table,\"a\"\n" \
70 " .align 2\n" \
71 " .long 1b,3b\n" \
72 ".text" \
73 : "=r"(x) : "r"(addr))
74
75 #define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500))
76 #define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504))
77
78 #define mk_config_addr(bus, dev, offset) \
79 (((bus)<<16) | ((dev)<<8) | (offset & 0xfc))
80
81 #define mk_config_type1(bus, dev, offset) \
82 mk_config_addr(bus, dev, offset) | 1;
83
84 /* Initialize the QSpan device registers after power up.
85 */
86 qspan_init()
87 {
88 uint *qptr;
89
90
91
92 qptr = (uint *)PCI_CSR_ADDR;
93
94 /* PCI Configuration/status. Upper bits written to clear
95 * pending interrupt or status. Lower bits enable QSPAN as
96 * PCI master, enable memory and I/O cycles, and enable PCI
97 * parity error checking.
98 * IMPORTANT: The last two bits of this word enable PCI
99 * master cycles into the QBus. The QSpan is broken and can't
100 * meet the timing specs of the PQ bus for this to work. Therefore,
101 * if you don't have external bus arbitration, you can't use
102 * this function.
103 */
104 #ifdef EXTERNAL_PQ_ARB
105 qptr[1] = 0xf9000147;
106 #else
107 qptr[1] = 0xf9000144;
108 #endif
109
110 /* PCI Misc configuration. Set PCI latency timer resolution
111 * of 8 cycles, set cache size to 4 x 32.
112 */
113 qptr[3] = 0;
114
115 /* Set up PCI Target address mapping. Enable, Posted writes,
116 * 2Gbyte space (processor memory controller determines actual size).
117 */
118 qptr[64] = 0x8f000080;
119
120 /* Map processor 0x80000000 to PCI 0x00000000.
121 * Processor address bit 1 determines I/O type access (0x80000000)
122 * or memory type access (0xc0000000).
123 */
124 qptr[65] = 0x80000000;
125
126 /* Enable error logging and clear any pending error status.
127 */
128 qptr[80] = 0x90000000;
129
130 qptr[512] = 0x000c0003;
131
132 /* Set up Qbus slave image.
133 */
134 qptr[960] = 0x01000000;
135 qptr[961] = 0x000000d1;
136 qptr[964] = 0x00000000;
137 qptr[965] = 0x000000d1;
138
139 }
140
141 /* Functions to support PCI bios-like features to read/write configuration
142 * space. If the function fails for any reason, a -1 (0xffffffff) value
143 * must be returned.
144 */
145 #define DEVICE_NOT_FOUND (-1)
146 #define SUCCESSFUL 0
147
148 int qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
149 unsigned char offset, unsigned char *val)
150 {
151 uint temp;
152 u_char *cp;
153
154 if ((bus > 7) || (dev_fn > 127)) {
155 *val = 0xff;
156 return DEVICE_NOT_FOUND;
157 }
158
159 if (bus == 0)
160 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
161 else
162 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
163 __get_pci_config(temp, QS_CONFIG_DATA, "lwz");
164
165 offset ^= 0x03;
166 cp = ((u_char *)&temp) + (offset & 0x03);
167 *val = *cp;
168 return SUCCESSFUL;
169 }
170
171 int qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
172 unsigned char offset, unsigned short *val)
173 {
174 uint temp;
175 ushort *sp;
176
177 if ((bus > 7) || (dev_fn > 127)) {
178 *val = 0xffff;
179 return DEVICE_NOT_FOUND;
180 }
181
182 if (bus == 0)
183 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
184 else
185 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
186 __get_pci_config(temp, QS_CONFIG_DATA, "lwz");
187 offset ^= 0x02;
188
189 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
190 *val = *sp;
191 return SUCCESSFUL;
192 }
193
194 int qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
195 unsigned char offset, unsigned int *val)
196 {
197 if ((bus > 7) || (dev_fn > 127)) {
198 *val = 0xffffffff;
199 return DEVICE_NOT_FOUND;
200 }
201 if (bus == 0)
202 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
203 else
204 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
205 __get_pci_config(*val, QS_CONFIG_DATA, "lwz");
206 return SUCCESSFUL;
207 }
208
209 int qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
210 unsigned char offset, unsigned char val)
211 {
212 uint temp;
213 u_char *cp;
214
215 if ((bus > 7) || (dev_fn > 127))
216 return DEVICE_NOT_FOUND;
217
218 qs_pci_read_config_dword(bus, dev_fn, offset, &temp);
219
220 offset ^= 0x03;
221 cp = ((u_char *)&temp) + (offset & 0x03);
222 *cp = val;
223
224 if (bus == 0)
225 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
226 else
227 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
228 *QS_CONFIG_DATA = temp;
229
230 return SUCCESSFUL;
231 }
232
233 int qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
234 unsigned char offset, unsigned short val)
235 {
236 uint temp;
237 ushort *sp;
238
239 if ((bus > 7) || (dev_fn > 127))
240 return DEVICE_NOT_FOUND;
241
242 qs_pci_read_config_dword(bus, dev_fn, offset, &temp);
243
244 offset ^= 0x02;
245 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
246 *sp = val;
247
248 if (bus == 0)
249 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
250 else
251 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
252 *QS_CONFIG_DATA = temp;
253
254 return SUCCESSFUL;
255 }
256
257 int qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
258 unsigned char offset, unsigned int val)
259 {
260 if ((bus > 7) || (dev_fn > 127))
261 return DEVICE_NOT_FOUND;
262
263 if (bus == 0)
264 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
265 else
266 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
267 *(unsigned int *)QS_CONFIG_DATA = val;
268
269 return SUCCESSFUL;
270 }
271
272