File: /usr/src/linux/arch/ppc/kernel/pci.c
1 /*
2 * BK Id: SCCS/s.pci.c 1.28 08/08/01 16:35:43 paulus
3 */
4 /*
5 * Common pmac/prep/chrp pci routines. -- Cort
6 */
7
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/capability.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/bootmem.h>
18
19 #include <asm/processor.h>
20 #include <asm/io.h>
21 #include <asm/prom.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/residual.h>
24 #include <asm/byteorder.h>
25 #include <asm/irq.h>
26 #include <asm/gg2.h>
27 #include <asm/uaccess.h>
28
29 #include "pci.h"
30
31 #define DEBUG
32
33 #ifdef DEBUG
34 #define DBG(x...) printk(x)
35 #else
36 #define DBG(x...)
37 #endif
38
39 unsigned long isa_io_base = 0;
40 unsigned long isa_mem_base = 0;
41 unsigned long pci_dram_offset = 0;
42
43 static void pcibios_fixup_resources(struct pci_dev* dev);
44 static void fixup_broken_pcnet32(struct pci_dev* dev);
45 #ifdef CONFIG_ALL_PPC
46 static void pcibios_fixup_cardbus(struct pci_dev* dev);
47 static u8* pci_to_OF_bus_map;
48 #endif
49
50 /* By default, we don't re-assign bus numbers. We do this only on
51 * some pmacs
52 */
53 int pci_assign_all_busses;
54
55 struct pci_controller* hose_head;
56 struct pci_controller** hose_tail = &hose_head;
57
58 static int pci_bus_count;
59
60 struct pci_fixup pcibios_fixups[] = {
61 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32 },
62 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
63 #ifdef CONFIG_ALL_PPC
64 /* We should add per-machine fixup support in xxx_setup.c or xxx_pci.c */
65 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1211, pcibios_fixup_cardbus },
66 #endif /* CONFIG_ALL_PPC */
67 { 0 }
68 };
69
70 static void
71 fixup_broken_pcnet32(struct pci_dev* dev)
72 {
73 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
74 dev->vendor = PCI_VENDOR_ID_AMD;
75 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
76 pci_name_device(dev);
77 }
78 }
79
80 void
81 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
82 struct resource *res, int resource)
83 {
84 u32 new, check;
85 int reg;
86 struct pci_controller* hose = dev->sysdata;
87 unsigned long io_offset;
88
89 new = res->start;
90 if (hose && res->flags & IORESOURCE_IO) {
91 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
92 new -= io_offset;
93 }
94 if (hose && res->flags & IORESOURCE_MEM)
95 new -= hose->pci_mem_offset;
96 new |= (res->flags & PCI_REGION_FLAG_MASK);
97 if (resource < 6) {
98 reg = PCI_BASE_ADDRESS_0 + 4*resource;
99 } else if (resource == PCI_ROM_RESOURCE) {
100 res->flags |= PCI_ROM_ADDRESS_ENABLE;
101 reg = dev->rom_base_reg;
102 } else {
103 /* Somebody might have asked allocation of a non-standard resource */
104 return;
105 }
106
107 pci_write_config_dword(dev, reg, new);
108 pci_read_config_dword(dev, reg, &check);
109 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
110 printk(KERN_ERR "PCI: Error while updating region "
111 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
112 new, check);
113 }
114 }
115
116 static void
117 pcibios_fixup_resources(struct pci_dev *dev)
118 {
119 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
120 int i;
121 unsigned long offset;
122
123 if (!hose) {
124 printk(KERN_ERR "No hose for PCI dev %s!\n", dev->slot_name);
125 return;
126 }
127 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
128 struct resource *res = dev->resource + i;
129 if (!res->start || !res->flags)
130 continue;
131 if (res->end == 0xffffffff) {
132 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
133 dev->slot_name, i, res->start, res->end);
134 res->end -= res->start;
135 res->start = 0;
136 continue;
137 }
138 offset = 0;
139 if (res->flags & IORESOURCE_MEM) {
140 offset = hose->pci_mem_offset;
141 } else if (res->flags & IORESOURCE_IO) {
142 offset = (unsigned long) hose->io_base_virt
143 - isa_io_base;
144 }
145 if (offset != 0) {
146 res->start += offset;
147 res->end += offset;
148 #ifdef DEBUG
149 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
150 i, res->flags, dev->slot_name,
151 res->start - offset, res->start);
152 #endif
153 }
154 }
155 }
156
157 #ifdef CONFIG_ALL_PPC
158 static void
159 pcibios_fixup_cardbus(struct pci_dev* dev)
160 {
161 /*
162 * Fix the interrupt routing on the TI1211 chip on the 1999
163 * G3 powerbook, which doesn't get initialized properly by OF.
164 */
165 if (dev->vendor == PCI_VENDOR_ID_TI
166 && dev->device == PCI_DEVICE_ID_TI_1211) {
167 u32 val;
168 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
169 signal out the MFUNC0 pin */
170 if (pci_read_config_dword(dev, 0x8c, &val) == 0
171 && val == 0)
172 pci_write_config_dword(dev, 0x8c, 2);
173 }
174 }
175 #endif /* CONFIG_ALL_PPC */
176
177 /*
178 * We need to avoid collisions with `mirrored' VGA ports
179 * and other strange ISA hardware, so we always want the
180 * addresses to be allocated in the 0x000-0x0ff region
181 * modulo 0x400.
182 *
183 * Why? Because some silly external IO cards only decode
184 * the low 10 bits of the IO address. The 0x00-0xff region
185 * is reserved for motherboard devices that decode all 16
186 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
187 * but we want to try to avoid allocating at 0x2900-0x2bff
188 * which might have be mirrored at 0x0100-0x03ff..
189 */
190 void
191 pcibios_align_resource(void *data, struct resource *res, unsigned long size)
192 {
193 struct pci_dev *dev = data;
194
195 if (res->flags & IORESOURCE_IO) {
196 unsigned long start = res->start;
197
198 if (size > 0x100) {
199 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
200 " (%ld bytes)\n", dev->slot_name,
201 dev->resource - res, size);
202 }
203
204 if (start & 0x300) {
205 start = (start + 0x3ff) & ~0x3ff;
206 res->start = start;
207 }
208 }
209 }
210
211
212 /*
213 * Handle resources of PCI devices. If the world were perfect, we could
214 * just allocate all the resource regions and do nothing more. It isn't.
215 * On the other hand, we cannot just re-allocate all devices, as it would
216 * require us to know lots of host bridge internals. So we attempt to
217 * keep as much of the original configuration as possible, but tweak it
218 * when it's found to be wrong.
219 *
220 * Known BIOS problems we have to work around:
221 * - I/O or memory regions not configured
222 * - regions configured, but not enabled in the command register
223 * - bogus I/O addresses above 64K used
224 * - expansion ROMs left enabled (this may sound harmless, but given
225 * the fact the PCI specs explicitly allow address decoders to be
226 * shared between expansion ROMs and other resource regions, it's
227 * at least dangerous)
228 *
229 * Our solution:
230 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
231 * This gives us fixed barriers on where we can allocate.
232 * (2) Allocate resources for all enabled devices. If there is
233 * a collision, just mark the resource as unallocated. Also
234 * disable expansion ROMs during this step.
235 * (3) Try to allocate resources for disabled devices. If the
236 * resources were assigned correctly, everything goes well,
237 * if they weren't, they won't disturb allocation of other
238 * resources.
239 * (4) Assign new addresses to resources which were either
240 * not configured at all or misconfigured. If explicitly
241 * requested by the user, configure expansion ROM address
242 * as well.
243 */
244
245 static void __init
246 pcibios_allocate_bus_resources(struct list_head *bus_list)
247 {
248 struct list_head *ln;
249 struct pci_bus *bus;
250 int i;
251 struct resource *res, *pr;
252
253 /* Depth-First Search on bus tree */
254 for (ln = bus_list->next; ln != bus_list; ln=ln->next) {
255 bus = pci_bus_b(ln);
256 for (i = 0; i < 4; ++i) {
257 if ((res = bus->resource[i]) == NULL || !res->flags)
258 continue;
259 if (bus->parent == NULL)
260 pr = (res->flags & IORESOURCE_IO)?
261 &ioport_resource: &iomem_resource;
262 else
263 pr = pci_find_parent_resource(bus->self, res);
264
265 if (pr && request_resource(pr, res) == 0)
266 continue;
267 printk(KERN_ERR "PCI: Cannot allocate resource region "
268 "%d of PCI bridge %d\n", i, bus->number);
269 DBG("PCI: resource is %lx..%lx (%lx), parent %p\n",
270 res->start, res->end, res->flags, pr);
271 }
272 pcibios_allocate_bus_resources(&bus->children);
273 }
274 }
275
276 static inline void alloc_resource(struct pci_dev *dev, int idx)
277 {
278 struct resource *pr, *r = &dev->resource[idx];
279
280 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
281 dev->slot_name, idx, r->start, r->end, r->flags);
282 pr = pci_find_parent_resource(dev, r);
283 if (!pr || request_resource(pr, r) < 0) {
284 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
285 " of device %s\n", idx, dev->slot_name);
286 if (pr)
287 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
288 pr, pr->start, pr->end, pr->flags);
289 /* We'll assign a new address later */
290 r->end -= r->start;
291 r->start = 0;
292 }
293 }
294
295 static void __init
296 pcibios_allocate_resources(int pass)
297 {
298 struct pci_dev *dev;
299 int idx, disabled;
300 u16 command;
301 struct resource *r;
302
303 pci_for_each_dev(dev) {
304 pci_read_config_word(dev, PCI_COMMAND, &command);
305 for (idx = 0; idx < 6; idx++) {
306 r = &dev->resource[idx];
307 if (r->parent) /* Already allocated */
308 continue;
309 if (!r->start) /* Not assigned at all */
310 continue;
311 if (r->flags & IORESOURCE_IO)
312 disabled = !(command & PCI_COMMAND_IO);
313 else
314 disabled = !(command & PCI_COMMAND_MEMORY);
315 if (pass == disabled)
316 alloc_resource(dev, idx);
317 }
318 if (pass)
319 continue;
320 r = &dev->resource[PCI_ROM_RESOURCE];
321 if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
322 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
323 u32 reg;
324 DBG("PCI: Switching off ROM of %s\n", dev->slot_name);
325 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
326 pci_read_config_dword(dev, dev->rom_base_reg, ®);
327 pci_write_config_dword(dev, dev->rom_base_reg,
328 reg & ~PCI_ROM_ADDRESS_ENABLE);
329 }
330 }
331 }
332
333 static void __init
334 pcibios_assign_resources(void)
335 {
336 struct pci_dev *dev;
337 int idx;
338 struct resource *r;
339
340 pci_for_each_dev(dev) {
341 int class = dev->class >> 8;
342
343 /* Don't touch classless devices and host bridges */
344 if (!class || class == PCI_CLASS_BRIDGE_HOST)
345 continue;
346
347 for (idx = 0; idx < 6; idx++) {
348 r = &dev->resource[idx];
349
350 /*
351 * We shall assign a new address to this resource,
352 * either because the BIOS (sic) forgot to do so
353 * or because we have decided the old address was
354 * unusable for some reason.
355 */
356 if (!r->start && r->end &&
357 (!ppc_md.pcibios_enable_device_hook ||
358 !ppc_md.pcibios_enable_device_hook(dev, 1)))
359 pci_assign_resource(dev, idx);
360 }
361
362 #if 0 /* don't assign ROMs */
363 r = &dev->resource[PCI_ROM_RESOURCE];
364 r->end -= r->start;
365 r->start = 0;
366 if (r->end)
367 pci_assign_resource(dev, PCI_ROM_RESOURCE);
368 #endif
369 }
370 }
371
372
373 int
374 pcibios_enable_resources(struct pci_dev *dev)
375 {
376 u16 cmd, old_cmd;
377 int idx;
378 struct resource *r;
379
380 pci_read_config_word(dev, PCI_COMMAND, &cmd);
381 old_cmd = cmd;
382 for(idx=0; idx<6; idx++) {
383 r = &dev->resource[idx];
384 if (!r->start && r->end) {
385 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
386 return -EINVAL;
387 }
388 if (r->flags & IORESOURCE_IO)
389 cmd |= PCI_COMMAND_IO;
390 if (r->flags & IORESOURCE_MEM)
391 cmd |= PCI_COMMAND_MEMORY;
392 }
393 if (dev->resource[PCI_ROM_RESOURCE].start)
394 cmd |= PCI_COMMAND_MEMORY;
395 if (cmd != old_cmd) {
396 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
397 pci_write_config_word(dev, PCI_COMMAND, cmd);
398 }
399 return 0;
400 }
401
402 static int next_controller_index;
403
404 struct pci_controller * __init
405 pcibios_alloc_controller(void)
406 {
407 struct pci_controller *hose;
408
409 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
410 memset(hose, 0, sizeof(struct pci_controller));
411
412 *hose_tail = hose;
413 hose_tail = &hose->next;
414
415 hose->index = next_controller_index++;
416
417 return hose;
418 }
419
420 #ifdef CONFIG_ALL_PPC
421 /*
422 * Functions below are used on OpenFirmware machines.
423 */
424 static void
425 make_one_node_map(struct device_node* node, u8 pci_bus)
426 {
427 int *bus_range;
428 int len;
429
430 if (pci_bus >= pci_bus_count)
431 return;
432 bus_range = (int *) get_property(node, "bus-range", &len);
433 if (bus_range == NULL || len < 2 * sizeof(int)) {
434 printk(KERN_WARNING "Can't get bus-range for %s\n",
435 node->full_name);
436 return;
437 }
438 pci_to_OF_bus_map[pci_bus] = bus_range[0];
439
440 for (node=node->child; node != 0;node = node->sibling) {
441 struct pci_dev* dev;
442 unsigned int *class_code, *reg;
443
444 class_code = (unsigned int *) get_property(node, "class-code", 0);
445 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
446 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
447 continue;
448 reg = (unsigned int *)get_property(node, "reg", 0);
449 if (!reg)
450 continue;
451 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
452 if (!dev || !dev->subordinate)
453 continue;
454 make_one_node_map(node, dev->subordinate->number);
455 }
456 }
457
458 void
459 pcibios_make_OF_bus_map(void)
460 {
461 int i;
462 struct pci_controller* hose;
463 u8* of_prop_map;
464
465 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
466 if (!pci_to_OF_bus_map) {
467 printk(KERN_ERR "Can't allocate OF bus map !\n");
468 return;
469 }
470
471 /* We fill the bus map with invalid values, that helps
472 * debugging.
473 */
474 for (i=0; i<pci_bus_count; i++)
475 pci_to_OF_bus_map[i] = 0xff;
476
477 /* For each hose, we begin searching bridges */
478 for(hose=hose_head; hose; hose=hose->next) {
479 struct device_node* node;
480 node = (struct device_node *)hose->arch_data;
481 if (!node)
482 continue;
483 make_one_node_map(node, hose->first_busno);
484 }
485 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", 0);
486 if (of_prop_map)
487 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
488 #ifdef DEBUG
489 printk("PCI->OF bus map:\n");
490 for (i=0; i<pci_bus_count; i++) {
491 if (pci_to_OF_bus_map[i] == 0xff)
492 continue;
493 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
494 }
495 #endif
496 }
497
498 static struct device_node*
499 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
500 {
501 struct device_node* sub_node;
502
503 for (; node != 0;node = node->sibling) {
504 unsigned int *class_code, *reg;
505
506 reg = (unsigned int *) get_property(node, "reg", 0);
507 if (reg && ((reg[0] >> 8) & 0xff) == dev_fn
508 && ((reg[0] >> 16) & 0xff) == bus)
509 return node;
510
511 /* For PCI<->PCI bridges or CardBus bridges, we go down
512 * Note: some OFs create a parent node "multifunc-device" as
513 * a fake root for all functions of a multi-function device,
514 * we go down them as well.
515 */
516 class_code = (unsigned int *) get_property(node, "class-code", 0);
517 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
518 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
519 strcmp(node->name, "multifunc-device"))
520 continue;
521 sub_node = scan_OF_childs_for_device(node->child, bus, dev_fn);
522 if (sub_node)
523 return sub_node;
524 }
525 return NULL;
526 }
527
528 /*
529 * Scans the OF tree for a device node matching a PCI device
530 */
531 struct device_node*
532 pci_device_to_OF_node(struct pci_dev *dev)
533 {
534 struct pci_controller *hose;
535 struct device_node *node;
536 int bus;
537
538 if (!have_of)
539 return NULL;
540
541 /* Lookup the hose */
542 bus = dev->bus->number;
543 hose = pci_bus_to_hose(bus);
544 if (!hose)
545 return NULL;
546
547 /* Check it has an OF node associated */
548 node = (struct device_node *) hose->arch_data;
549 if (!node)
550 return NULL;
551
552 /* Fixup bus number according to what OF think it is. */
553 if (pci_to_OF_bus_map)
554 bus = pci_to_OF_bus_map[bus];
555 if (bus == 0xff)
556 return NULL;
557
558 /* Now, lookup childs of the hose */
559 return scan_OF_childs_for_device(node->child, bus, dev->devfn);
560 }
561
562 /* This routine is meant to be used early during boot, when the
563 * PCI bus numbers have not yet been assigned, and you need to
564 * issue PCI config cycles to an OF device.
565 * It could also be used to "fix" RTAS config cycles if you want
566 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
567 * config cycles.
568 */
569 struct pci_controller*
570 pci_find_hose_for_OF_device(struct device_node* node)
571 {
572 if (!have_of)
573 return NULL;
574 while(node) {
575 struct pci_controller* hose;
576 for (hose=hose_head;hose;hose=hose->next)
577 if (hose->arch_data == node)
578 return hose;
579 node=node->parent;
580 }
581 return NULL;
582 }
583
584 /*
585 * Returns the PCI device matching a given OF node
586 */
587 int
588 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
589 {
590 unsigned int *reg;
591 int i;
592
593 if (!have_of)
594 return -ENODEV;
595 reg = (unsigned int *) get_property(node, "reg", 0);
596 if (!reg)
597 return -ENODEV;
598 *bus = (reg[0] >> 16) & 0xff;
599 for (i=0; pci_to_OF_bus_map && i<pci_bus_count; i++)
600 if (pci_to_OF_bus_map[i] == *bus) {
601 *bus = i;
602 break;
603 }
604 *devfn = ((reg[0] >> 8) & 0xff);
605 return 0;
606 }
607
608 void __init
609 pci_process_bridge_OF_ranges(struct pci_controller *hose,
610 struct device_node *dev, int primary)
611 {
612 unsigned int *ranges, *prev;
613 int rlen = 0;
614 int memno = 0;
615 struct resource *res;
616 int np, na = prom_n_addr_cells(dev);
617 np = na + 5;
618
619 /* First we try to merge ranges to fix a problem with some pmacs
620 * that can have more than 3 ranges, fortunately using contiguous
621 * addresses -- BenH
622 */
623 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
624 prev = NULL;
625 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
626 if (prev) {
627 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
628 (prev[2] + prev[na+4]) == ranges[2] &&
629 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
630 prev[na+4] += ranges[na+4];
631 ranges[0] = 0;
632 ranges += np;
633 continue;
634 }
635 }
636 prev = ranges;
637 ranges += np;
638 }
639
640 /*
641 * The ranges property is laid out as an array of elements,
642 * each of which comprises:
643 * cells 0 - 2: a PCI address
644 * cells 3 or 3+4: a CPU physical address
645 * (size depending on dev->n_addr_cells)
646 * cells 4+5 or 5+6: the size of the range
647 */
648 rlen = 0;
649 hose->io_base_phys = 0;
650 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
651 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
652 res = NULL;
653 switch (ranges[0] >> 24) {
654 case 1: /* I/O space */
655 if (ranges[2] != 0)
656 break;
657 hose->io_base_phys = ranges[na+2];
658 hose->io_base_virt = ioremap(ranges[na+2], ranges[na+4]);
659 if (primary)
660 isa_io_base = (unsigned long) hose->io_base_virt;
661 res = &hose->io_resource;
662 res->flags = IORESOURCE_IO;
663 res->start = ranges[2];
664 break;
665 case 2: /* memory space */
666 memno = 0;
667 if (ranges[1] == 0 && ranges[2] == 0
668 && ranges[na+4] <= (16 << 20)) {
669 /* 1st 16MB, i.e. ISA memory area */
670 if (primary)
671 isa_mem_base = ranges[na+2];
672 memno = 1;
673 }
674 while (memno < 3 && hose->mem_resources[memno].flags)
675 ++memno;
676 if (memno == 0)
677 hose->pci_mem_offset = ranges[na+2] - ranges[2];
678 if (memno < 3) {
679 res = &hose->mem_resources[memno];
680 res->flags = IORESOURCE_MEM;
681 res->start = ranges[na+2];
682 }
683 break;
684 }
685 if (res != NULL) {
686 res->name = dev->full_name;
687 res->end = res->start + ranges[na+4] - 1;
688 res->parent = NULL;
689 res->sibling = NULL;
690 res->child = NULL;
691 }
692 ranges += np;
693 }
694 }
695 #endif /* CONFIG_ALL_PPC */
696
697 void __init
698 pcibios_init(void)
699 {
700 struct pci_controller *hose;
701 struct pci_bus *bus;
702 int next_busno;
703
704 printk(KERN_INFO "PCI: Probing PCI hardware\n");
705
706 /* Scan all of the recorded PCI controllers. */
707 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
708 if (pci_assign_all_busses)
709 hose->first_busno = next_busno;
710 hose->last_busno = 0xff;
711 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
712 hose->last_busno = bus->subordinate;
713 if (pci_assign_all_busses || next_busno <= hose->last_busno)
714 next_busno = hose->last_busno+1;
715 }
716 pci_bus_count = next_busno;
717
718 /* OpenFirmware based machines need a map of OF bus
719 * numbers vs. kernel bus numbers since we may have to
720 * remap them.
721 */
722 if (pci_assign_all_busses && have_of)
723 pcibios_make_OF_bus_map();
724
725 /* Call machine dependant fixup */
726 if (ppc_md.pcibios_fixup)
727 ppc_md.pcibios_fixup();
728
729 /* Allocate and assign resources */
730 pcibios_allocate_bus_resources(&pci_root_buses);
731 pcibios_allocate_resources(0);
732 pcibios_allocate_resources(1);
733 pcibios_assign_resources();
734
735 /* Call machine dependent post-init code */
736 if (ppc_md.pcibios_after_init)
737 ppc_md.pcibios_after_init();
738 }
739
740 int __init
741 pcibios_assign_all_busses(void)
742 {
743 return pci_assign_all_busses;
744 }
745
746 void __init
747 pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
748 {
749 ranges->io_start -= bus->resource[0]->start;
750 ranges->io_end -= bus->resource[0]->start;
751 ranges->mem_start -= bus->resource[1]->start;
752 ranges->mem_end -= bus->resource[1]->start;
753 }
754
755 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
756 unsigned long start, unsigned long size)
757 {
758 return start;
759 }
760
761 void __init pcibios_fixup_bus(struct pci_bus *bus)
762 {
763 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
764 unsigned long io_offset;
765 struct resource *res;
766 int i;
767
768 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
769 if (bus->parent == NULL) {
770 /* This is a host bridge - fill in its resources */
771 hose->bus = bus;
772
773 bus->resource[0] = res = &hose->io_resource;
774 if (!res->flags) {
775 if (io_offset)
776 printk(KERN_ERR "I/O resource not set for host"
777 " bridge %d\n", hose->index);
778 res->start = 0;
779 res->end = IO_SPACE_LIMIT;
780 res->flags = IORESOURCE_IO;
781 }
782 res->start += io_offset;
783 res->end += io_offset;
784
785 for (i = 0; i < 3; ++i) {
786 res = &hose->mem_resources[i];
787 if (!res->flags) {
788 if (i > 0)
789 continue;
790 printk(KERN_ERR "Memory resource not set for "
791 "host bridge %d\n", hose->index);
792 res->start = hose->pci_mem_offset;
793 res->end = ~0U;
794 res->flags = IORESOURCE_MEM;
795 }
796 bus->resource[i+1] = res;
797 }
798 } else {
799 /* This is a subordinate bridge */
800 pci_read_bridge_bases(bus);
801
802 for (i = 0; i < 4; ++i) {
803 if ((res = bus->resource[i]) == NULL)
804 continue;
805 if (!res->flags)
806 continue;
807 if (io_offset && (res->flags & IORESOURCE_IO)) {
808 res->start += io_offset;
809 res->end += io_offset;
810 } else if (hose->pci_mem_offset
811 && (res->flags & IORESOURCE_MEM)) {
812 res->start += hose->pci_mem_offset;
813 res->end += hose->pci_mem_offset;
814 }
815 }
816 }
817
818 if (ppc_md.pcibios_fixup_bus)
819 ppc_md.pcibios_fixup_bus(bus);
820 }
821
822 char __init *pcibios_setup(char *str)
823 {
824 return str;
825 }
826
827 /* the next one is stolen from the alpha port... */
828 void __init
829 pcibios_update_irq(struct pci_dev *dev, int irq)
830 {
831 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
832 /* XXX FIXME - update OF device tree node interrupt property */
833 }
834
835 int pcibios_enable_device(struct pci_dev *dev)
836 {
837 u16 cmd, old_cmd;
838 int idx;
839 struct resource *r;
840
841 if (ppc_md.pcibios_enable_device_hook)
842 if (ppc_md.pcibios_enable_device_hook(dev, 0))
843 return -EINVAL;
844
845 pci_read_config_word(dev, PCI_COMMAND, &cmd);
846 old_cmd = cmd;
847 for (idx=0; idx<6; idx++) {
848 r = &dev->resource[idx];
849 if (!r->start && r->end) {
850 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
851 return -EINVAL;
852 }
853 if (r->flags & IORESOURCE_IO)
854 cmd |= PCI_COMMAND_IO;
855 if (r->flags & IORESOURCE_MEM)
856 cmd |= PCI_COMMAND_MEMORY;
857 }
858 if (cmd != old_cmd) {
859 printk("PCI: Enabling device %s (%04x -> %04x)\n",
860 dev->slot_name, old_cmd, cmd);
861 pci_write_config_word(dev, PCI_COMMAND, cmd);
862 }
863 return 0;
864 }
865
866 struct pci_controller*
867 pci_bus_to_hose(int bus)
868 {
869 struct pci_controller* hose = hose_head;
870
871 for (; hose; hose = hose->next)
872 if (bus >= hose->first_busno && bus <= hose->last_busno)
873 return hose;
874 return NULL;
875 }
876
877 void*
878 pci_bus_io_base(unsigned int bus)
879 {
880 struct pci_controller *hose;
881
882 hose = pci_bus_to_hose(bus);
883 if (!hose)
884 return NULL;
885 return hose->io_base_virt;
886 }
887
888 unsigned long
889 pci_bus_io_base_phys(unsigned int bus)
890 {
891 struct pci_controller *hose;
892
893 hose = pci_bus_to_hose(bus);
894 if (!hose)
895 return 0;
896 return hose->io_base_phys;
897 }
898
899 unsigned long
900 pci_bus_mem_base_phys(unsigned int bus)
901 {
902 struct pci_controller *hose;
903
904 hose = pci_bus_to_hose(bus);
905 if (!hose)
906 return 0;
907 return hose->pci_mem_offset;
908 }
909
910 unsigned long
911 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
912 {
913 /* Hack alert again ! See comments in chrp_pci.c
914 */
915 struct pci_controller* hose =
916 (struct pci_controller *)pdev->sysdata;
917 if (hose && res->flags & IORESOURCE_MEM)
918 return res->start - hose->pci_mem_offset;
919 /* We may want to do something with IOs here... */
920 return res->start;
921 }
922
923 /*
924 * Return the index of the PCI controller for device pdev.
925 */
926 int pci_controller_num(struct pci_dev *dev)
927 {
928 struct pci_controller *hose = (struct pci_controller *) dev->sysdata;
929
930 return hose->index;
931 }
932
933 /*
934 * Platform support for /proc/bus/pci/X/Y mmap()s,
935 * modelled on the sparc64 implementation by Dave Miller.
936 * -- paulus.
937 */
938
939 /*
940 * Adjust vm_pgoff of VMA such that it is the physical page offset
941 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
942 *
943 * Basically, the user finds the base address for his device which he wishes
944 * to mmap. They read the 32-bit value from the config space base register,
945 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
946 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
947 *
948 * Returns negative error code on failure, zero on success.
949 */
950 static __inline__ int
951 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
952 enum pci_mmap_state mmap_state)
953 {
954 struct pci_controller *hose = (struct pci_controller *) dev->sysdata;
955 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
956 unsigned long io_offset = 0;
957 int i, res_bit;
958
959 if (hose == 0)
960 return -EINVAL; /* should never happen */
961
962 /* If memory, add on the PCI bridge address offset */
963 if (mmap_state == pci_mmap_mem) {
964 offset += hose->pci_mem_offset;
965 res_bit = IORESOURCE_MEM;
966 } else {
967 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
968 offset += io_offset;
969 res_bit = IORESOURCE_IO;
970 }
971
972 /*
973 * Check that the offset requested corresponds to one of the
974 * resources of the device.
975 */
976 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
977 struct resource *rp = &dev->resource[i];
978 int flags = rp->flags;
979
980 /* treat ROM as memory (should be already) */
981 if (i == PCI_ROM_RESOURCE)
982 flags |= IORESOURCE_MEM;
983
984 /* Active and same type? */
985 if ((flags & res_bit) == 0)
986 continue;
987
988 /* In the range of this resource? */
989 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
990 continue;
991
992 /* found it! construct the final physical address */
993 if (mmap_state == pci_mmap_io)
994 offset += hose->io_base_phys - io_offset;
995
996 vma->vm_pgoff = offset >> PAGE_SHIFT;
997 return 0;
998 }
999
1000 return -EINVAL;
1001 }
1002
1003 /*
1004 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1005 * mapping.
1006 */
1007 static __inline__ void
1008 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1009 enum pci_mmap_state mmap_state)
1010 {
1011 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1012 }
1013
1014 /*
1015 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1016 * device mapping.
1017 */
1018 static __inline__ void
1019 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1020 enum pci_mmap_state mmap_state, int write_combine)
1021 {
1022 int prot = pgprot_val(vma->vm_page_prot);
1023
1024 /* XXX would be nice to have a way to ask for write-through */
1025 prot |= _PAGE_NO_CACHE;
1026 if (!write_combine)
1027 prot |= _PAGE_GUARDED;
1028 vma->vm_page_prot = __pgprot(prot);
1029 }
1030
1031 /*
1032 * Perform the actual remap of the pages for a PCI device mapping, as
1033 * appropriate for this architecture. The region in the process to map
1034 * is described by vm_start and vm_end members of VMA, the base physical
1035 * address is found in vm_pgoff.
1036 * The pci device structure is provided so that architectures may make mapping
1037 * decisions on a per-device or per-bus basis.
1038 *
1039 * Returns a negative error code on failure, zero on success.
1040 */
1041 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1042 enum pci_mmap_state mmap_state,
1043 int write_combine)
1044 {
1045 int ret;
1046
1047 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1048 if (ret < 0)
1049 return ret;
1050
1051 __pci_mmap_set_flags(dev, vma, mmap_state);
1052 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
1053
1054 ret = remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
1055 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1056
1057 return ret;
1058 }
1059
1060 /* Obsolete functions. Should be removed once the symbios driver
1061 * is fixed
1062 */
1063 unsigned long
1064 phys_to_bus(unsigned long pa)
1065 {
1066 struct pci_controller *hose;
1067 int i;
1068
1069 for (hose = hose_head; hose; hose = hose->next) {
1070 for (i = 0; i < 3; ++i) {
1071 if (pa >= hose->mem_resources[i].start
1072 && pa <= hose->mem_resources[i].end) {
1073 /*
1074 * XXX the hose->pci_mem_offset really
1075 * only applies to mem_resources[0].
1076 * We need a way to store an offset for
1077 * the others. -- paulus
1078 */
1079 if (i == 0)
1080 pa -= hose->pci_mem_offset;
1081 return pa;
1082 }
1083 }
1084 }
1085 /* hmmm, didn't find it */
1086 return 0;
1087 }
1088
1089 unsigned long
1090 pci_phys_to_bus(unsigned long pa, int busnr)
1091 {
1092 struct pci_controller* hose = pci_bus_to_hose(busnr);
1093 if (!hose)
1094 return pa;
1095 return pa - hose->pci_mem_offset;
1096 }
1097
1098 unsigned long
1099 pci_bus_to_phys(unsigned int ba, int busnr)
1100 {
1101 struct pci_controller* hose = pci_bus_to_hose(busnr);
1102 if (!hose)
1103 return ba;
1104 return ba + hose->pci_mem_offset;
1105 }
1106
1107 /* Provide information on locations of various I/O regions in physical
1108 * memory. Do this on a per-card basis so that we choose the right
1109 * root bridge.
1110 * Note that the returned IO or memory base is a physical address
1111 */
1112
1113 long
1114 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1115 {
1116 struct pci_controller* hose = pci_bus_to_hose(bus);
1117 long result = -EOPNOTSUPP;
1118
1119 if (!hose)
1120 return -ENODEV;
1121
1122 switch (which) {
1123 case IOBASE_BRIDGE_NUMBER:
1124 return (long)hose->first_busno;
1125 case IOBASE_MEMORY:
1126 return (long)hose->pci_mem_offset;
1127 case IOBASE_IO:
1128 return (long)hose->io_base_phys;
1129 case IOBASE_ISA_IO:
1130 return (long)isa_io_base;
1131 case IOBASE_ISA_MEM:
1132 return (long)isa_mem_base;
1133 }
1134
1135 return result;
1136 }
1137
1138 /*
1139 * Null PCI config access functions, for the case when we can't
1140 * find a hose.
1141 */
1142 #define NULL_PCI_OP(rw, size, type) \
1143 static int \
1144 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1145 { \
1146 return PCIBIOS_DEVICE_NOT_FOUND; \
1147 }
1148
1149 NULL_PCI_OP(read, byte, u8 *)
1150 NULL_PCI_OP(read, word, u16 *)
1151 NULL_PCI_OP(read, dword, u32 *)
1152 NULL_PCI_OP(write, byte, u8)
1153 NULL_PCI_OP(write, word, u16)
1154 NULL_PCI_OP(write, dword, u32)
1155
1156 static struct pci_ops null_pci_ops =
1157 {
1158 null_read_config_byte,
1159 null_read_config_word,
1160 null_read_config_dword,
1161 null_write_config_byte,
1162 null_write_config_word,
1163 null_write_config_dword
1164 };
1165
1166 /*
1167 * These functions are used early on before PCI scanning is done
1168 * and all of the pci_dev and pci_bus structures have been created.
1169 */
1170 static struct pci_dev *
1171 fake_pci_dev(struct pci_controller *hose, int busnr, int devfn)
1172 {
1173 static struct pci_dev dev;
1174 static struct pci_bus bus;
1175
1176 if (hose == 0) {
1177 hose = pci_bus_to_hose(busnr);
1178 if (hose == 0)
1179 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1180 }
1181 dev.bus = &bus;
1182 dev.sysdata = hose;
1183 dev.devfn = devfn;
1184 bus.number = busnr;
1185 bus.ops = hose? hose->ops: &null_pci_ops;
1186 return &dev;
1187 }
1188
1189 #define EARLY_PCI_OP(rw, size, type) \
1190 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1191 int devfn, int offset, type value) \
1192 { \
1193 return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
1194 offset, value); \
1195 }
1196
1197 EARLY_PCI_OP(read, byte, u8 *)
1198 EARLY_PCI_OP(read, word, u16 *)
1199 EARLY_PCI_OP(read, dword, u32 *)
1200 EARLY_PCI_OP(write, byte, u8)
1201 EARLY_PCI_OP(write, word, u16)
1202 EARLY_PCI_OP(write, dword, u32)
1203