File: /usr/src/linux/arch/ppc/kernel/prep_pci.c
1 /*
2 * BK Id: SCCS/s.prep_pci.c 1.26 09/08/01 15:47:42 paulus
3 */
4 /*
5 * PReP pci functions.
6 * Originally by Gary Thomas
7 * rewritten and updated by Cort Dougan (cort@cs.nmt.edu)
8 *
9 * The motherboard routes/maps will disappear shortly. -- Cort
10 */
11
12 #include <linux/config.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17
18 #include <asm/sections.h>
19 #include <asm/byteorder.h>
20 #include <asm/io.h>
21 #include <asm/ptrace.h>
22 #include <asm/prom.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/residual.h>
25 #include <asm/processor.h>
26 #include <asm/irq.h>
27 #include <asm/machdep.h>
28
29 #include "pci.h"
30 #include "open_pic.h"
31
32 #define MAX_DEVNR 22
33
34 /* Which PCI interrupt line does a given device [slot] use? */
35 /* Note: This really should be two dimensional based in slot/pin used */
36 unsigned char *Motherboard_map;
37 unsigned char *Motherboard_map_name;
38
39 /* How is the 82378 PIRQ mapping setup? */
40 unsigned char *Motherboard_routes;
41
42 void (*Motherboard_non0)(struct pci_dev *);
43
44 void Powerplus_Map_Non0(struct pci_dev *);
45
46 /* Used for Motorola to store system config register */
47 static unsigned long *ProcInfo;
48
49 /* Tables for known hardware */
50
51 /* Motorola PowerStackII - Utah */
52 static char Utah_pci_IRQ_map[23] __prepdata =
53 {
54 0, /* Slot 0 - unused */
55 0, /* Slot 1 - unused */
56 5, /* Slot 2 - SCSI - NCR825A */
57 0, /* Slot 3 - unused */
58 1, /* Slot 4 - Ethernet - DEC2114x */
59 0, /* Slot 5 - unused */
60 3, /* Slot 6 - PCI Card slot #1 */
61 4, /* Slot 7 - PCI Card slot #2 */
62 5, /* Slot 8 - PCI Card slot #3 */
63 5, /* Slot 9 - PCI Bridge */
64 /* added here in case we ever support PCI bridges */
65 /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */
66 0, /* Slot 10 - unused */
67 0, /* Slot 11 - unused */
68 5, /* Slot 12 - SCSI - NCR825A */
69 0, /* Slot 13 - unused */
70 3, /* Slot 14 - enet */
71 0, /* Slot 15 - unused */
72 2, /* Slot 16 - unused */
73 3, /* Slot 17 - unused */
74 5, /* Slot 18 - unused */
75 0, /* Slot 19 - unused */
76 0, /* Slot 20 - unused */
77 0, /* Slot 21 - unused */
78 0, /* Slot 22 - unused */
79 };
80
81 static char Utah_pci_IRQ_routes[] __prepdata =
82 {
83 0, /* Line 0 - Unused */
84 9, /* Line 1 */
85 10, /* Line 2 */
86 11, /* Line 3 */
87 14, /* Line 4 */
88 15, /* Line 5 */
89 };
90
91 /* Motorola PowerStackII - Omaha */
92 /* no integrated SCSI or ethernet */
93 static char Omaha_pci_IRQ_map[23] __prepdata =
94 {
95 0, /* Slot 0 - unused */
96 0, /* Slot 1 - unused */
97 3, /* Slot 2 - Winbond EIDE */
98 0, /* Slot 3 - unused */
99 0, /* Slot 4 - unused */
100 0, /* Slot 5 - unused */
101 1, /* Slot 6 - PCI slot 1 */
102 2, /* Slot 7 - PCI slot 2 */
103 3, /* Slot 8 - PCI slot 3 */
104 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */
105 0, /* Slot 10 - unused */
106 0, /* Slot 11 - unused */
107 0, /* Slot 12 - unused */
108 0, /* Slot 13 - unused */
109 0, /* Slot 14 - unused */
110 0, /* Slot 15 - unused */
111 1, /* Slot 16 - PCI slot 1 */
112 2, /* Slot 17 - PCI slot 2 */
113 3, /* Slot 18 - PCI slot 3 */
114 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */
115 0,
116 0,
117 0,
118 };
119
120 static char Omaha_pci_IRQ_routes[] __prepdata =
121 {
122 0, /* Line 0 - Unused */
123 9, /* Line 1 */
124 11, /* Line 2 */
125 14, /* Line 3 */
126 15 /* Line 4 */
127 };
128
129 /* Motorola PowerStack */
130 static char Blackhawk_pci_IRQ_map[19] __prepdata =
131 {
132 0, /* Slot 0 - unused */
133 0, /* Slot 1 - unused */
134 0, /* Slot 2 - unused */
135 0, /* Slot 3 - unused */
136 0, /* Slot 4 - unused */
137 0, /* Slot 5 - unused */
138 0, /* Slot 6 - unused */
139 0, /* Slot 7 - unused */
140 0, /* Slot 8 - unused */
141 0, /* Slot 9 - unused */
142 0, /* Slot 10 - unused */
143 0, /* Slot 11 - unused */
144 3, /* Slot 12 - SCSI */
145 0, /* Slot 13 - unused */
146 1, /* Slot 14 - Ethernet */
147 0, /* Slot 15 - unused */
148 1, /* Slot P7 */
149 2, /* Slot P6 */
150 3, /* Slot P5 */
151 };
152
153 static char Blackhawk_pci_IRQ_routes[] __prepdata =
154 {
155 0, /* Line 0 - Unused */
156 9, /* Line 1 */
157 11, /* Line 2 */
158 15, /* Line 3 */
159 15 /* Line 4 */
160 };
161
162 /* Motorola Mesquite */
163 static char Mesquite_pci_IRQ_map[23] __prepdata =
164 {
165 0, /* Slot 0 - unused */
166 0, /* Slot 1 - unused */
167 0, /* Slot 2 - unused */
168 0, /* Slot 3 - unused */
169 0, /* Slot 4 - unused */
170 0, /* Slot 5 - unused */
171 0, /* Slot 6 - unused */
172 0, /* Slot 7 - unused */
173 0, /* Slot 8 - unused */
174 0, /* Slot 9 - unused */
175 0, /* Slot 10 - unused */
176 0, /* Slot 11 - unused */
177 0, /* Slot 12 - unused */
178 0, /* Slot 13 - unused */
179 2, /* Slot 14 - Ethernet */
180 0, /* Slot 15 - unused */
181 3, /* Slot 16 - PMC */
182 0, /* Slot 17 - unused */
183 0, /* Slot 18 - unused */
184 0, /* Slot 19 - unused */
185 0, /* Slot 20 - unused */
186 0, /* Slot 21 - unused */
187 0, /* Slot 22 - unused */
188 };
189
190 /* Motorola Sitka */
191 static char Sitka_pci_IRQ_map[21] __prepdata =
192 {
193 0, /* Slot 0 - unused */
194 0, /* Slot 1 - unused */
195 0, /* Slot 2 - unused */
196 0, /* Slot 3 - unused */
197 0, /* Slot 4 - unused */
198 0, /* Slot 5 - unused */
199 0, /* Slot 6 - unused */
200 0, /* Slot 7 - unused */
201 0, /* Slot 8 - unused */
202 0, /* Slot 9 - unused */
203 0, /* Slot 10 - unused */
204 0, /* Slot 11 - unused */
205 0, /* Slot 12 - unused */
206 0, /* Slot 13 - unused */
207 2, /* Slot 14 - Ethernet */
208 0, /* Slot 15 - unused */
209 9, /* Slot 16 - PMC 1 */
210 12, /* Slot 17 - PMC 2 */
211 0, /* Slot 18 - unused */
212 0, /* Slot 19 - unused */
213 4, /* Slot 20 - NT P2P bridge */
214 };
215
216 /* Motorola MTX */
217 static char MTX_pci_IRQ_map[23] __prepdata =
218 {
219 0, /* Slot 0 - unused */
220 0, /* Slot 1 - unused */
221 0, /* Slot 2 - unused */
222 0, /* Slot 3 - unused */
223 0, /* Slot 4 - unused */
224 0, /* Slot 5 - unused */
225 0, /* Slot 6 - unused */
226 0, /* Slot 7 - unused */
227 0, /* Slot 8 - unused */
228 0, /* Slot 9 - unused */
229 0, /* Slot 10 - unused */
230 0, /* Slot 11 - unused */
231 3, /* Slot 12 - SCSI */
232 0, /* Slot 13 - unused */
233 2, /* Slot 14 - Ethernet */
234 0, /* Slot 15 - unused */
235 9, /* Slot 16 - PCI/PMC slot 1 */
236 10, /* Slot 17 - PCI/PMC slot 2 */
237 11, /* Slot 18 - PCI slot 3 */
238 0, /* Slot 19 - unused */
239 0, /* Slot 20 - unused */
240 0, /* Slot 21 - unused */
241 0, /* Slot 22 - unused */
242 };
243
244 /* Motorola MTX Plus */
245 /* Secondary bus interrupt routing is not supported yet */
246 static char MTXplus_pci_IRQ_map[23] __prepdata =
247 {
248 0, /* Slot 0 - unused */
249 0, /* Slot 1 - unused */
250 0, /* Slot 2 - unused */
251 0, /* Slot 3 - unused */
252 0, /* Slot 4 - unused */
253 0, /* Slot 5 - unused */
254 0, /* Slot 6 - unused */
255 0, /* Slot 7 - unused */
256 0, /* Slot 8 - unused */
257 0, /* Slot 9 - unused */
258 0, /* Slot 10 - unused */
259 0, /* Slot 11 - unused */
260 3, /* Slot 12 - SCSI */
261 0, /* Slot 13 - unused */
262 2, /* Slot 14 - Ethernet 1 */
263 0, /* Slot 15 - unused */
264 9, /* Slot 16 - PCI slot 1P */
265 10, /* Slot 17 - PCI slot 2P */
266 11, /* Slot 18 - PCI slot 3P */
267 10, /* Slot 19 - Ethernet 2 */
268 0, /* Slot 20 - P2P Bridge */
269 0, /* Slot 21 - unused */
270 0, /* Slot 22 - unused */
271 };
272
273 static char Raven_pci_IRQ_routes[] __prepdata =
274 {
275 0, /* This is a dummy structure */
276 };
277
278 /* Motorola MVME16xx */
279 static char Genesis_pci_IRQ_map[16] __prepdata =
280 {
281 0, /* Slot 0 - unused */
282 0, /* Slot 1 - unused */
283 0, /* Slot 2 - unused */
284 0, /* Slot 3 - unused */
285 0, /* Slot 4 - unused */
286 0, /* Slot 5 - unused */
287 0, /* Slot 6 - unused */
288 0, /* Slot 7 - unused */
289 0, /* Slot 8 - unused */
290 0, /* Slot 9 - unused */
291 0, /* Slot 10 - unused */
292 0, /* Slot 11 - unused */
293 3, /* Slot 12 - SCSI */
294 0, /* Slot 13 - unused */
295 1, /* Slot 14 - Ethernet */
296 0, /* Slot 15 - unused */
297 };
298
299 static char Genesis_pci_IRQ_routes[] __prepdata =
300 {
301 0, /* Line 0 - Unused */
302 10, /* Line 1 */
303 11, /* Line 2 */
304 14, /* Line 3 */
305 15 /* Line 4 */
306 };
307
308 static char Genesis2_pci_IRQ_map[23] __prepdata =
309 {
310 0, /* Slot 0 - unused */
311 0, /* Slot 1 - unused */
312 0, /* Slot 2 - unused */
313 0, /* Slot 3 - unused */
314 0, /* Slot 4 - unused */
315 0, /* Slot 5 - unused */
316 0, /* Slot 6 - unused */
317 0, /* Slot 7 - unused */
318 0, /* Slot 8 - unused */
319 0, /* Slot 9 - unused */
320 0, /* Slot 10 - Ethernet */
321 0, /* Slot 11 - Universe PCI - VME Bridge */
322 3, /* Slot 12 - unused */
323 0, /* Slot 13 - unused */
324 2, /* Slot 14 - SCSI */
325 0, /* Slot 15 - unused */
326 9, /* Slot 16 - PMC 1 */
327 12, /* Slot 17 - pci */
328 11, /* Slot 18 - pci */
329 10, /* Slot 19 - pci */
330 0, /* Slot 20 - pci */
331 0, /* Slot 21 - unused */
332 0, /* Slot 22 - unused */
333 };
334
335 /* Motorola Series-E */
336 static char Comet_pci_IRQ_map[23] __prepdata =
337 {
338 0, /* Slot 0 - unused */
339 0, /* Slot 1 - unused */
340 0, /* Slot 2 - unused */
341 0, /* Slot 3 - unused */
342 0, /* Slot 4 - unused */
343 0, /* Slot 5 - unused */
344 0, /* Slot 6 - unused */
345 0, /* Slot 7 - unused */
346 0, /* Slot 8 - unused */
347 0, /* Slot 9 - unused */
348 0, /* Slot 10 - unused */
349 0, /* Slot 11 - unused */
350 3, /* Slot 12 - SCSI */
351 0, /* Slot 13 - unused */
352 1, /* Slot 14 - Ethernet */
353 0, /* Slot 15 - unused */
354 1, /* Slot 16 - PCI slot 1 */
355 2, /* Slot 17 - PCI slot 2 */
356 3, /* Slot 18 - PCI slot 3 */
357 4, /* Slot 19 - PCI bridge */
358 0,
359 0,
360 0,
361 };
362
363 static char Comet_pci_IRQ_routes[] __prepdata =
364 {
365 0, /* Line 0 - Unused */
366 10, /* Line 1 */
367 11, /* Line 2 */
368 14, /* Line 3 */
369 15 /* Line 4 */
370 };
371
372 /* Motorola Series-EX */
373 static char Comet2_pci_IRQ_map[23] __prepdata =
374 {
375 0, /* Slot 0 - unused */
376 0, /* Slot 1 - unused */
377 3, /* Slot 2 - SCSI - NCR825A */
378 0, /* Slot 3 - unused */
379 1, /* Slot 4 - Ethernet - DEC2104X */
380 0, /* Slot 5 - unused */
381 1, /* Slot 6 - PCI slot 1 */
382 2, /* Slot 7 - PCI slot 2 */
383 3, /* Slot 8 - PCI slot 3 */
384 4, /* Slot 9 - PCI bridge */
385 0, /* Slot 10 - unused */
386 0, /* Slot 11 - unused */
387 3, /* Slot 12 - SCSI - NCR825A */
388 0, /* Slot 13 - unused */
389 1, /* Slot 14 - Ethernet - DEC2104X */
390 0, /* Slot 15 - unused */
391 1, /* Slot 16 - PCI slot 1 */
392 2, /* Slot 17 - PCI slot 2 */
393 3, /* Slot 18 - PCI slot 3 */
394 4, /* Slot 19 - PCI bridge */
395 0,
396 0,
397 0,
398 };
399
400 static char Comet2_pci_IRQ_routes[] __prepdata =
401 {
402 0, /* Line 0 - Unused */
403 10, /* Line 1 */
404 11, /* Line 2 */
405 14, /* Line 3 */
406 15, /* Line 4 */
407 };
408
409 /*
410 * ibm 830 (and 850?).
411 * This is actually based on the Carolina motherboard
412 * -- Cort
413 */
414 static char ibm8xx_pci_IRQ_map[23] __prepdata = {
415 0, /* Slot 0 - unused */
416 0, /* Slot 1 - unused */
417 0, /* Slot 2 - unused */
418 0, /* Slot 3 - unused */
419 0, /* Slot 4 - unused */
420 0, /* Slot 5 - unused */
421 0, /* Slot 6 - unused */
422 0, /* Slot 7 - unused */
423 0, /* Slot 8 - unused */
424 0, /* Slot 9 - unused */
425 0, /* Slot 10 - unused */
426 0, /* Slot 11 - FireCoral */
427 4, /* Slot 12 - Ethernet PCIINTD# */
428 2, /* Slot 13 - PCI Slot #2 */
429 2, /* Slot 14 - S3 Video PCIINTD# */
430 0, /* Slot 15 - onboard SCSI (INDI) [1] */
431 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */
432 0, /* Slot 17 - unused */
433 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
434 0, /* Slot 19 - unused */
435 0, /* Slot 20 - unused */
436 0, /* Slot 21 - unused */
437 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
438 };
439
440 static char ibm8xx_pci_IRQ_routes[] __prepdata = {
441 0, /* Line 0 - unused */
442 15, /* Line 1 */
443 15, /* Line 2 */
444 15, /* Line 3 */
445 15, /* Line 4 */
446 };
447
448 /*
449 * a 6015 ibm board
450 * -- Cort
451 */
452 static char ibm6015_pci_IRQ_map[23] __prepdata = {
453 0, /* Slot 0 - unused */
454 0, /* Slot 1 - unused */
455 0, /* Slot 2 - unused */
456 0, /* Slot 3 - unused */
457 0, /* Slot 4 - unused */
458 0, /* Slot 5 - unused */
459 0, /* Slot 6 - unused */
460 0, /* Slot 7 - unused */
461 0, /* Slot 8 - unused */
462 0, /* Slot 9 - unused */
463 0, /* Slot 10 - unused */
464 0, /* Slot 11 - */
465 1, /* Slot 12 - SCSI */
466 2, /* Slot 13 - */
467 2, /* Slot 14 - */
468 1, /* Slot 15 - */
469 1, /* Slot 16 - */
470 0, /* Slot 17 - */
471 2, /* Slot 18 - */
472 0, /* Slot 19 - */
473 0, /* Slot 20 - */
474 0, /* Slot 21 - */
475 2, /* Slot 22 - */
476 };
477 static char ibm6015_pci_IRQ_routes[] __prepdata = {
478 0, /* Line 0 - unused */
479 13, /* Line 1 */
480 10, /* Line 2 */
481 15, /* Line 3 */
482 15, /* Line 4 */
483 };
484
485
486 /* IBM Nobis and 850 */
487 static char Nobis_pci_IRQ_map[23] __prepdata ={
488 0, /* Slot 0 - unused */
489 0, /* Slot 1 - unused */
490 0, /* Slot 2 - unused */
491 0, /* Slot 3 - unused */
492 0, /* Slot 4 - unused */
493 0, /* Slot 5 - unused */
494 0, /* Slot 6 - unused */
495 0, /* Slot 7 - unused */
496 0, /* Slot 8 - unused */
497 0, /* Slot 9 - unused */
498 0, /* Slot 10 - unused */
499 0, /* Slot 11 - unused */
500 3, /* Slot 12 - SCSI */
501 0, /* Slot 13 - unused */
502 0, /* Slot 14 - unused */
503 0, /* Slot 15 - unused */
504 };
505
506 static char Nobis_pci_IRQ_routes[] __prepdata = {
507 0, /* Line 0 - Unused */
508 13, /* Line 1 */
509 13, /* Line 2 */
510 13, /* Line 3 */
511 13 /* Line 4 */
512 };
513
514 /*
515 * IBM RS/6000 43p/140 -- paulus
516 * XXX we should get all this from the residual data
517 */
518 static char ibm43p_pci_IRQ_map[23] __prepdata = {
519 0, /* Slot 0 - unused */
520 0, /* Slot 1 - unused */
521 0, /* Slot 2 - unused */
522 0, /* Slot 3 - unused */
523 0, /* Slot 4 - unused */
524 0, /* Slot 5 - unused */
525 0, /* Slot 6 - unused */
526 0, /* Slot 7 - unused */
527 0, /* Slot 8 - unused */
528 0, /* Slot 9 - unused */
529 0, /* Slot 10 - unused */
530 0, /* Slot 11 - FireCoral ISA bridge */
531 6, /* Slot 12 - Ethernet */
532 0, /* Slot 13 - openpic */
533 0, /* Slot 14 - unused */
534 0, /* Slot 15 - unused */
535 7, /* Slot 16 - NCR58C825a onboard scsi */
536 0, /* Slot 17 - unused */
537 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
538 0, /* Slot 19 - unused */
539 0, /* Slot 20 - unused */
540 0, /* Slot 21 - unused */
541 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
542 };
543
544 static char ibm43p_pci_IRQ_routes[] __prepdata = {
545 0, /* Line 0 - unused */
546 15, /* Line 1 */
547 15, /* Line 2 */
548 15, /* Line 3 */
549 15, /* Line 4 */
550 };
551
552 /* Motorola PowerPlus architecture PCI IRQ tables */
553 /* Interrupt line values for INTA-D on primary/secondary MPIC inputs */
554
555 struct powerplus_irq_list
556 {
557 unsigned char primary[4]; /* INT A-D */
558 unsigned char secondary[4]; /* INT A-D */
559 };
560
561 /*
562 * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to
563 * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge
564 * are routed to OpenPIC inputs 5-8. These values are offset by
565 * 16 in the table to reflect the Linux kernel interrupt value.
566 */
567 struct powerplus_irq_list Powerplus_pci_IRQ_list =
568 {
569 {25, 26, 27, 28},
570 {21, 22, 23, 24}
571 };
572
573 /*
574 * For the MCP750 (system slot board), cPCI INTs A-D are routed to
575 * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC
576 * input 3. On a hot swap MCP750, the companion card PCI INTs A-D
577 * are routed to OpenPIC inputs 12-15. These values are offset by
578 * 16 in the table to reflect the Linux kernel interrupt value.
579 */
580 struct powerplus_irq_list Mesquite_pci_IRQ_list =
581 {
582 {24, 25, 26, 27},
583 {28, 29, 30, 31}
584 };
585
586 /*
587 * This table represents the standard PCI swizzle defined in the
588 * PCI bus specification.
589 */
590 static unsigned char prep_pci_intpins[4][4] =
591 {
592 { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */
593 { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */
594 { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */
595 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */
596 };
597
598 /* We have to turn on LEVEL mode for changed IRQ's */
599 /* All PCI IRQ's need to be level mode, so this should be something
600 * other than hard-coded as well... IRQ's are individually mappable
601 * to either edge or level.
602 */
603 #define CAROLINA_IRQ_EDGE_MASK_LO 0x00 /* IRQ's 0-7 */
604 #define CAROLINA_IRQ_EDGE_MASK_HI 0xA4 /* IRQ's 8-15 [10,13,15] */
605
606 /*
607 * 8259 edge/level control definitions
608 */
609 #define ISA8259_M_ELCR 0x4d0
610 #define ISA8259_S_ELCR 0x4d1
611
612 #define ELCRS_INT15_LVL 0x80
613 #define ELCRS_INT14_LVL 0x40
614 #define ELCRS_INT12_LVL 0x10
615 #define ELCRS_INT11_LVL 0x08
616 #define ELCRS_INT10_LVL 0x04
617 #define ELCRS_INT9_LVL 0x02
618 #define ELCRS_INT8_LVL 0x01
619 #define ELCRM_INT7_LVL 0x80
620 #define ELCRM_INT5_LVL 0x20
621
622 #define CFGPTR(dev) (0x80800000 | (1<<(dev>>3)) | ((dev&7)<<8) | offset)
623 #define DEVNO(dev) (dev>>3)
624
625 #define cfg_read(val, addr, type, op) *val = op((type)(addr))
626 #define cfg_write(val, addr, type, op) op((type *)(addr), (val))
627
628 #define cfg_read_bad(val, size) *val = bad_##size;
629 #define cfg_write_bad(val, size)
630
631 #define bad_byte 0xff
632 #define bad_word 0xffff
633 #define bad_dword 0xffffffffU
634
635 #define PREP_PCI_OP(rw, size, type, op) \
636 static int __prep \
637 prep_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
638 { \
639 if ((dev->bus->number != 0) || (DEVNO(dev->devfn) > MAX_DEVNR)) \
640 { \
641 cfg_##rw##_bad(val, size) \
642 return PCIBIOS_DEVICE_NOT_FOUND; \
643 } \
644 cfg_##rw(val, CFGPTR(dev->devfn), type, op); \
645 return PCIBIOS_SUCCESSFUL; \
646 }
647
648 PREP_PCI_OP(read, byte, u8 *, in_8)
649 PREP_PCI_OP(read, word, u16 *, in_le16)
650 PREP_PCI_OP(read, dword, u32 *, in_le32)
651 PREP_PCI_OP(write, byte, u8, out_8)
652 PREP_PCI_OP(write, word, u16, out_le16)
653 PREP_PCI_OP(write, dword, u32, out_le32)
654
655 static struct pci_ops prep_pci_ops =
656 {
657 prep_read_config_byte,
658 prep_read_config_word,
659 prep_read_config_dword,
660 prep_write_config_byte,
661 prep_write_config_word,
662 prep_write_config_dword
663 };
664
665 #define MOTOROLA_CPUTYPE_REG 0x800
666 #define MOTOROLA_BASETYPE_REG 0x803
667 #define MPIC_RAVEN_ID 0x48010000
668 #define MPIC_HAWK_ID 0x48030000
669 #define MOT_PROC2_BIT 0x800
670
671 static u_char mvme2600_openpic_initsenses[] __initdata = {
672 1, /* MVME2600_INT_SIO */
673 0, /* MVME2600_INT_FALCN_ECC_ERR */
674 1, /* MVME2600_INT_PCI_ETHERNET */
675 1, /* MVME2600_INT_PCI_SCSI */
676 1, /* MVME2600_INT_PCI_GRAPHICS */
677 1, /* MVME2600_INT_PCI_VME0 */
678 1, /* MVME2600_INT_PCI_VME1 */
679 1, /* MVME2600_INT_PCI_VME2 */
680 1, /* MVME2600_INT_PCI_VME3 */
681 1, /* MVME2600_INT_PCI_INTA */
682 1, /* MVME2600_INT_PCI_INTB */
683 1, /* MVME2600_INT_PCI_INTC */
684 1, /* MVME2600_INT_PCI_INTD */
685 1, /* MVME2600_INT_LM_SIG0 */
686 1, /* MVME2600_INT_LM_SIG1 */
687 };
688
689 #define MOT_RAVEN_PRESENT 0x1
690 #define MOT_HAWK_PRESENT 0x2
691
692 int mot_entry = -1;
693 int prep_keybd_present = 1;
694 int MotMPIC;
695 int mot_multi;
696
697 int __init raven_init(void)
698 {
699 unsigned int devid;
700 unsigned int pci_membase;
701 unsigned char base_mod;
702
703 /* Check to see if the Raven chip exists. */
704 if ( _prep_type != _PREP_Motorola) {
705 OpenPIC_Addr = NULL;
706 return 0;
707 }
708
709 /* Check to see if this board is a type that might have a Raven. */
710 if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
711 OpenPIC_Addr = NULL;
712 return 0;
713 }
714
715 /* Check the first PCI device to see if it is a Raven. */
716 early_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &devid);
717
718 switch (devid & 0xffff0000) {
719 case MPIC_RAVEN_ID:
720 MotMPIC = MOT_RAVEN_PRESENT;
721 break;
722 case MPIC_HAWK_ID:
723 MotMPIC = MOT_HAWK_PRESENT;
724 break;
725 default:
726 OpenPIC_Addr = NULL;
727 return 0;
728 }
729
730
731 /* Read the memory base register. */
732 early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
733
734 if (pci_membase == 0) {
735 OpenPIC_Addr = NULL;
736 return 0;
737 }
738
739 /* Map the Raven MPIC registers to virtual memory. */
740 OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000);
741
742 OpenPIC_InitSenses = mvme2600_openpic_initsenses;
743 OpenPIC_NumInitSenses = sizeof(mvme2600_openpic_initsenses);
744
745 ppc_md.get_irq = openpic_get_irq;
746
747 /* If raven is present on Motorola store the system config register
748 * for later use.
749 */
750 ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
751
752 /* Indicate to system if this is a multiprocessor board */
753 if (!(*ProcInfo & MOT_PROC2_BIT)) {
754 mot_multi = 1;
755 }
756
757 /* This is a hack. If this is a 2300 or 2400 mot board then there is
758 * no keyboard controller and we have to indicate that.
759 */
760 base_mod = inb(MOTOROLA_BASETYPE_REG);
761 if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
762 (base_mod == 0xFA) || (base_mod == 0xE1))
763 prep_keybd_present = 0;
764
765 return 1;
766 }
767
768 struct mot_info {
769 int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
770 /* 0x200 if this board has a Hawk chip. */
771 int base_type;
772 int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
773 const char *name;
774 unsigned char *map;
775 unsigned char *routes;
776 void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */
777 struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
778 unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
779 } mot_info[] = {
780 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
781 {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
782 {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00},
783 {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00},
784 {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00},
785 {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00},
786 {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00},
787 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF},
788 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
789 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0},
790 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
791 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
792 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
793 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
794 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
795 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
796 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
797 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
798 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
799 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
800 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
801 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
802 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
803 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
804 {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
805 {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00}
806 };
807
808 void ibm_prep_init(void)
809 {
810 u32 addr;
811 #ifdef CONFIG_PREP_RESIDUAL
812 PPC_DEVICE *mpic;
813 #endif
814
815 if (inb(0x0852) == 0xd5) {
816 /* This is for the 43p-140 */
817 early_read_config_dword(0, 0, PCI_DEVFN(13, 0),
818 PCI_BASE_ADDRESS_0, &addr);
819 if (addr != 0xffffffff
820 && !(addr & PCI_BASE_ADDRESS_SPACE_IO)
821 && (addr &= PCI_BASE_ADDRESS_MEM_MASK) != 0) {
822 addr += PREP_ISA_MEM_BASE;
823 OpenPIC_Addr = ioremap(addr, 0x40000);
824 ppc_md.get_irq = openpic_get_irq;
825 }
826 }
827
828 #ifdef CONFIG_PREP_RESIDUAL
829 mpic = residual_find_device(-1, NULL, SystemPeripheral,
830 ProgrammableInterruptController, MPIC, 0);
831 if (mpic != NULL) {
832 printk("mpic = %p\n", mpic);
833 }
834 #endif
835 }
836
837 void
838 ibm43p_pci_map_non0(struct pci_dev *dev)
839 {
840 unsigned char intpin;
841 static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 };
842
843 if (dev == NULL)
844 return;
845 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
846 if (intpin < 1 || intpin > 4)
847 return;
848 intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3;
849 dev->irq = openpic_to_irq(bridge_intrs[intpin]);
850 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
851 }
852
853 void __init prep_route_pci_interrupts(void)
854 {
855 unsigned char *ibc_pirq = (unsigned char *)0x80800860;
856 unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
857 int i;
858
859 if ( _prep_type == _PREP_Motorola)
860 {
861 unsigned short irq_mode;
862 unsigned char cpu_type;
863 unsigned char base_mod;
864 int entry;
865
866 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
867 base_mod = inb(MOTOROLA_BASETYPE_REG);
868
869 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
870 if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */
871 if (!(MotMPIC & MOT_HAWK_PRESENT))
872 continue;
873 } else { /* Check non hawk boards */
874 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
875 continue;
876
877 if (mot_info[entry].base_type == 0) {
878 mot_entry = entry;
879 break;
880 }
881
882 if (mot_info[entry].base_type != base_mod)
883 continue;
884 }
885
886 if (!(mot_info[entry].max_cpu & 0x80)) {
887 mot_entry = entry;
888 break;
889 }
890
891 /* processor 1 not present and max processor zero indicated */
892 if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
893 mot_entry = entry;
894 break;
895 }
896
897 /* processor 1 present and max processor zero indicated */
898 if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
899 mot_entry = entry;
900 break;
901 }
902 }
903
904 if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */
905 mot_entry = 3;
906
907 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
908 Motherboard_map = mot_info[mot_entry].map;
909 Motherboard_routes = mot_info[mot_entry].routes;
910 Motherboard_non0 = mot_info[mot_entry].map_non0_bus;
911
912 if (!(mot_info[entry].cpu_type & 0x100)) {
913 /* AJF adjust level/edge control according to routes */
914 irq_mode = 0;
915 for (i = 1; i <= 4; i++)
916 {
917 irq_mode |= ( 1 << Motherboard_routes[i] );
918 }
919 outb( irq_mode & 0xff, 0x4d0 );
920 outb( (irq_mode >> 8) & 0xff, 0x4d1 );
921 }
922 } else if ( _prep_type == _PREP_IBM )
923 {
924 unsigned char pl_id;
925 /*
926 * my carolina is 0xf0
927 * 6015 has 0xfc
928 * -- Cort
929 */
930 printk("IBM ID: %08x\n", inb(0x0852));
931 switch(inb(0x0852))
932 {
933 case 0xff:
934 Motherboard_map_name = "IBM 850/860 Portable";
935 Motherboard_map = Nobis_pci_IRQ_map;
936 Motherboard_routes = Nobis_pci_IRQ_routes;
937 break;
938 case 0xfc:
939 Motherboard_map_name = "IBM 6015";
940 Motherboard_map = ibm6015_pci_IRQ_map;
941 Motherboard_routes = ibm6015_pci_IRQ_routes;
942 break;
943 case 0xd5:
944 Motherboard_map_name = "IBM 43p/140";
945 Motherboard_map = ibm43p_pci_IRQ_map;
946 Motherboard_routes = ibm43p_pci_IRQ_routes;
947 Motherboard_non0 = ibm43p_pci_map_non0;
948 break;
949 default:
950 Motherboard_map_name = "IBM 8xx (Carolina)";
951 Motherboard_map = ibm8xx_pci_IRQ_map;
952 Motherboard_routes = ibm8xx_pci_IRQ_routes;
953 break;
954 }
955
956 /*printk("Changing IRQ mode\n");*/
957 pl_id=inb(0x04d0);
958 /*printk("Low mask is %#0x\n", pl_id);*/
959 outb(pl_id|CAROLINA_IRQ_EDGE_MASK_LO, 0x04d0);
960
961 pl_id=inb(0x04d1);
962 /*printk("Hi mask is %#0x\n", pl_id);*/
963 outb(pl_id|CAROLINA_IRQ_EDGE_MASK_HI, 0x04d1);
964 pl_id=inb(0x04d1);
965 /*printk("Hi mask now %#0x\n", pl_id);*/
966 }
967 else
968 {
969 printk("No known machine pci routing!\n");
970 return;
971 }
972
973 /* Set up mapping from slots */
974 for (i = 1; i <= 4; i++)
975 {
976 ibc_pirq[i-1] = Motherboard_routes[i];
977 }
978 /* Enable PCI interrupts */
979 *ibc_pcicon |= 0x20;
980 }
981
982 void __init
983 prep_pib_init(void)
984 {
985 unsigned char reg;
986 unsigned short short_reg;
987
988 struct pci_dev *dev = NULL;
989
990 if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) {
991 /*
992 * Perform specific configuration for the Via Tech or
993 * or Winbond PCI-ISA-Bridge part.
994 */
995 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
996 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
997 /*
998 * PPCBUG does not set the enable bits
999 * for the IDE device. Force them on here.
1000 */
1001 pci_read_config_byte(dev, 0x40, ®);
1002
1003 reg |= 0x03; /* IDE: Chip Enable Bits */
1004 pci_write_config_byte(dev, 0x40, reg);
1005 }
1006 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
1007 PCI_DEVICE_ID_VIA_82C586_2,
1008 dev)) && (dev->devfn = 0x5a)) {
1009 /* Force correct USB interrupt */
1010 dev->irq = 11;
1011 pci_write_config_byte(dev,
1012 PCI_INTERRUPT_LINE,
1013 dev->irq);
1014 }
1015 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1016 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
1017 /* Clear PCI Interrupt Routing Control Register. */
1018 short_reg = 0x0000;
1019 pci_write_config_word(dev, 0x44, short_reg);
1020 if (OpenPIC_Addr){
1021 /* Route IDE interrupts to IRQ 14 */
1022 reg = 0xEE;
1023 pci_write_config_byte(dev, 0x43, reg);
1024 }
1025 }
1026 }
1027
1028 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1029 PCI_DEVICE_ID_WINBOND_82C105, dev))){
1030 if (OpenPIC_Addr){
1031 /*
1032 * Disable LEGIRQ mode so PCI INTS are routed
1033 * directly to the 8259 and enable both channels
1034 */
1035 pci_write_config_dword(dev, 0x40, 0x10ff0033);
1036
1037 /* Force correct IDE interrupt */
1038 dev->irq = 14;
1039 pci_write_config_byte(dev,
1040 PCI_INTERRUPT_LINE,
1041 dev->irq);
1042 }else{
1043 /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */
1044 pci_write_config_dword(dev, 0x40, 0x10ff08a1);
1045 }
1046 }
1047 }
1048
1049 void
1050 Powerplus_Map_Non0(struct pci_dev *dev)
1051 {
1052 struct pci_bus *pbus; /* Parent bus structure pointer */
1053 struct pci_dev *tdev = dev; /* Temporary device structure */
1054 unsigned int devnum; /* Accumulated device number */
1055 unsigned char intline; /* Linux interrupt value */
1056 unsigned char intpin; /* PCI interrupt pin */
1057
1058 /* Check for valid PCI dev pointer */
1059 if (dev == NULL) return;
1060
1061 /* Initialize bridge IDSEL variable */
1062 devnum = PCI_SLOT(tdev->devfn);
1063
1064 /* Read the interrupt pin of the device and adjust for indexing */
1065 pcibios_read_config_byte(dev->bus->number, dev->devfn,
1066 PCI_INTERRUPT_PIN, &intpin);
1067
1068 /* If device doesn't request an interrupt, return */
1069 if ( (intpin < 1) || (intpin > 4) )
1070 return;
1071
1072 intpin--;
1073
1074 /*
1075 * Walk up to bus 0, adjusting the interrupt pin for the standard
1076 * PCI bus swizzle.
1077 */
1078 do {
1079 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1080 pbus = tdev->bus; /* up one level */
1081 tdev = pbus->self;
1082 devnum = PCI_SLOT(tdev->devfn);
1083 } while(tdev->bus->number);
1084
1085 /* Use the primary interrupt inputs by default */
1086 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1087
1088 /*
1089 * If the board has secondary interrupt inputs, walk the bus and
1090 * note the devfn of the bridge from bus 0. If it is the same as
1091 * the devfn of the bus bridge with secondary inputs, use those.
1092 * Otherwise, assume it's a PMC site and get the interrupt line
1093 * value from the interrupt routing table.
1094 */
1095 if (mot_info[mot_entry].secondary_bridge_devfn)
1096 {
1097 pbus = dev->bus;
1098
1099 while (pbus->primary != 0)
1100 pbus = pbus->parent;
1101
1102 if ((pbus->self)->devfn != 0xA0)
1103 {
1104 if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn)
1105 intline = mot_info[mot_entry].pci_irq_list->secondary[intpin];
1106 else
1107 {
1108 if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map)
1109 intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16;
1110 else
1111 {
1112 int i;
1113 for (i=0;i<3;i++)
1114 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1115 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1116 }
1117 }
1118 }
1119 }
1120
1121 /* Write calculated interrupt value to header and device list */
1122 dev->irq = intline;
1123 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq);
1124 }
1125
1126 void __init
1127 prep_pcibios_fixup(void)
1128 {
1129 struct pci_dev *dev;
1130 extern unsigned char *Motherboard_map;
1131 extern unsigned char *Motherboard_routes;
1132 unsigned char i;
1133
1134 prep_route_pci_interrupts();
1135
1136 printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
1137 if (OpenPIC_Addr) {
1138 /* PCI interrupts are controlled by the OpenPIC */
1139 pci_for_each_dev(dev) {
1140 if (dev->bus->number == 0)
1141 {
1142 dev->irq = openpic_to_irq(Motherboard_map[PCI_SLOT(dev->devfn)]);
1143 pcibios_write_config_byte(dev->bus->number, dev->devfn, PCI_INTERRUPT_LINE, dev->irq);
1144 }
1145 else
1146 {
1147 if (Motherboard_non0 != NULL)
1148 Motherboard_non0(dev);
1149 }
1150 }
1151
1152 /* Setup the Winbond or Via PIB */
1153 prep_pib_init();
1154
1155 return;
1156 }
1157
1158 pci_for_each_dev(dev) {
1159 /*
1160 * Use our old hard-coded kludge to figure out what
1161 * irq this device uses. This is necessary on things
1162 * without residual data. -- Cort
1163 */
1164 unsigned char d = PCI_SLOT(dev->devfn);
1165 dev->irq = Motherboard_routes[Motherboard_map[d]];
1166
1167 for ( i = 0 ; i <= 5 ; i++ )
1168 {
1169 /*
1170 * Relocate PCI I/O resources if necessary so the
1171 * standard 256MB BAT covers them.
1172 */
1173 if ( (pci_resource_flags(dev, i) & IORESOURCE_IO) &&
1174 (dev->resource[i].start > 0x10000000) )
1175 {
1176 printk("Relocating PCI address %lx -> %lx\n",
1177 dev->resource[i].start,
1178 (dev->resource[i].start & 0x00FFFFFF)
1179 | 0x01000000);
1180 dev->resource[i].start =
1181 (dev->resource[i].start & 0x00FFFFFF) | 0x01000000;
1182 pci_write_config_dword(dev,
1183 PCI_BASE_ADDRESS_0+(i*0x4),
1184 dev->resource[i].start );
1185 dev->resource[i].end =
1186 (dev->resource[i].end & 0x00FFFFFF) | 0x01000000;
1187 }
1188 }
1189 #if 0
1190 /*
1191 * If we have residual data and if it knows about this
1192 * device ask it what the irq is.
1193 * -- Cort
1194 */
1195 ppcd = residual_find_device_id( ~0L, dev->device,
1196 -1,-1,-1, 0);
1197 #endif
1198 }
1199 }
1200
1201 static void __init
1202 prep_init_resource(struct resource *res, unsigned long start,
1203 unsigned long end, int flags)
1204 {
1205 res->flags = flags;
1206 res->start = start;
1207 res->end = end;
1208 res->name = "PCI host bridge";
1209 res->parent = NULL;
1210 res->sibling = NULL;
1211 res->child = NULL;
1212 }
1213
1214 void __init
1215 prep_find_bridges(void)
1216 {
1217 struct pci_controller* hose;
1218
1219 hose = pcibios_alloc_controller();
1220 if (!hose)
1221 return;
1222
1223 hose->first_busno = 0;
1224 hose->last_busno = 0xff;
1225 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
1226 hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
1227 prep_init_resource(&hose->io_resource, 0, 0x0fffffff, IORESOURCE_IO);
1228 prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff,
1229 IORESOURCE_MEM);
1230
1231 printk("PReP architecture\n");
1232 {
1233 #ifdef CONFIG_PREP_RESIDUAL
1234 PPC_DEVICE *hostbridge;
1235
1236 hostbridge = residual_find_device(PROCESSORDEVICE, NULL,
1237 BridgeController, PCIBridge, -1, 0);
1238 if (hostbridge &&
1239 hostbridge->DeviceId.Interface == PCIBridgeIndirect) {
1240 PnP_TAG_PACKET * pkt;
1241 pkt = PnP_find_large_vendor_packet(
1242 res->DevicePnPHeap+hostbridge->AllocatedOffset,
1243 3, 0);
1244 if(pkt)
1245 {
1246 #define p pkt->L4_Pack.L4_Data.L4_PPCPack
1247 setup_indirect_pci(hose,
1248 ld_le32((unsigned *) (p.PPCData)),
1249 ld_le32((unsigned *) (p.PPCData+8)));
1250 }
1251 else
1252 {
1253 setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
1254 }
1255 }
1256 else
1257 #endif /* CONFIG_PREP_RESIDUAL */
1258 {
1259 hose->ops = &prep_pci_ops;
1260 }
1261 }
1262
1263 ppc_md.pcibios_fixup = prep_pcibios_fixup;
1264 }
1265
1266