File: /usr/src/linux/arch/ppc/mm/mmu_decl.h
1 /*
2 * BK Id: %F% %I% %G% %U% %#%
3 */
4 /*
5 * Declarations of procedures and variables shared between files
6 * in arch/ppc/mm/.
7 *
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
14 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
15 *
16 * Derived from "arch/i386/mm/init.c"
17 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 */
25
26 extern void mapin_ram(void);
27 extern void bat_mapin_ram(void);
28 extern int map_page(unsigned long va, unsigned long pa, int flags);
29 extern void setbat(int index, unsigned long virt, unsigned long phys,
30 unsigned int size, int flags);
31 extern void reserve_phys_mem(unsigned long start, unsigned long size);
32
33 extern int __map_without_bats;
34 extern void *end_of_DRAM;
35 extern unsigned long ioremap_base;
36 extern unsigned long ioremap_bot;
37 extern unsigned int rtas_data, rtas_size;
38
39 extern unsigned long total_memory;
40 extern unsigned long total_lowmem;
41 extern unsigned long ram_phys_base;
42 extern int mem_init_done;
43
44 extern PTE *Hash, *Hash_end;
45 extern unsigned long Hash_size, Hash_mask;
46
47 /* ...and now those things that may be slightly different between processor
48 * architectures. -- Dan
49 */
50 #if defined(CONFIG_8xx)
51 #define flush_HPTE(X, va, pg) _tlbie(va)
52 #define MMU_init_hw() do { } while(0)
53
54 #elif defined(CONFIG_4xx)
55 #define flush_HPTE(X, va, pg) _tlbie(va)
56
57 #else
58 /* anything except 4xx or 8xx */
59 extern void MMU_init_hw(void);
60
61 /* Be careful....this needs to be updated if we ever encounter 603 SMPs,
62 * which includes all new 82xx processors. We need tlbie/tlbsync here
63 * in that case (I think). -- Dan.
64 */
65 static inline void flush_HPTE(unsigned context, unsigned long va, pte_t *pg)
66 {
67 if ((Hash != 0) &&
68 (cur_cpu_spec[0]->cpu_features & CPU_FTR_HPTE_TABLE))
69 flush_hash_page(0, va, pg);
70 else
71 _tlbie(va);
72 }
73 #endif
74