File: /usr/src/linux/arch/ppc/xmon/ppc-opc.c
1 /*
2 * BK Id: SCCS/s.ppc-opc.c 1.5 05/17/01 18:14:23 cort
3 */
4 /* ppc-opc.c -- PowerPC opcode list
5 Copyright 1994 Free Software Foundation, Inc.
6 Written by Ian Lance Taylor, Cygnus Support
7
8 This file is part of GDB, GAS, and the GNU binutils.
9
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version
13 2, or (at your option) any later version.
14
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include <linux/posix_types.h>
25 #include "ansidecl.h"
26 #include "ppc.h"
27
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39 /* Local insertion and extraction functions. */
40
41 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
42 static long extract_bat PARAMS ((unsigned long, int *));
43 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
44 static long extract_bba PARAMS ((unsigned long, int *));
45 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
46 static long extract_bd PARAMS ((unsigned long, int *));
47 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
48 static long extract_bdm PARAMS ((unsigned long, int *));
49 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
50 static long extract_bdp PARAMS ((unsigned long, int *));
51 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
52 static long extract_bo PARAMS ((unsigned long, int *));
53 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
54 static long extract_boe PARAMS ((unsigned long, int *));
55 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
56 static long extract_ds PARAMS ((unsigned long, int *));
57 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
58 static long extract_li PARAMS ((unsigned long, int *));
59 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
60 static long extract_mbe PARAMS ((unsigned long, int *));
61 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
62 static long extract_mb6 PARAMS ((unsigned long, int *));
63 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
64 static long extract_nb PARAMS ((unsigned long, int *));
65 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
66 static long extract_nsi PARAMS ((unsigned long, int *));
67 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
68 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
69 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
70 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
71 static long extract_rbs PARAMS ((unsigned long, int *));
72 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
73 static long extract_sh6 PARAMS ((unsigned long, int *));
74 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
75 static long extract_spr PARAMS ((unsigned long, int *));
76 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
77 static long extract_tbr PARAMS ((unsigned long, int *));
78
79 /* The operands table.
80
81 The fields are bits, shift, signed, insert, extract, flags. */
82
83 const struct powerpc_operand powerpc_operands[] =
84 {
85 /* The zero index is used to indicate the end of the list of
86 operands. */
87 #define UNUSED (0)
88 { 0, 0, 0, 0, 0 },
89
90 /* The BA field in an XL form instruction. */
91 #define BA (1)
92 #define BA_MASK (0x1f << 16)
93 { 5, 16, 0, 0, PPC_OPERAND_CR },
94
95 /* The BA field in an XL form instruction when it must be the same
96 as the BT field in the same instruction. */
97 #define BAT (2)
98 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
99
100 /* The BB field in an XL form instruction. */
101 #define BB (3)
102 #define BB_MASK (0x1f << 11)
103 { 5, 11, 0, 0, PPC_OPERAND_CR },
104
105 /* The BB field in an XL form instruction when it must be the same
106 as the BA field in the same instruction. */
107 #define BBA (4)
108 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
109
110 /* The BD field in a B form instruction. The lower two bits are
111 forced to zero. */
112 #define BD (5)
113 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
114
115 /* The BD field in a B form instruction when absolute addressing is
116 used. */
117 #define BDA (6)
118 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
119
120 /* The BD field in a B form instruction when the - modifier is used.
121 This sets the y bit of the BO field appropriately. */
122 #define BDM (7)
123 { 16, 0, insert_bdm, extract_bdm,
124 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
125
126 /* The BD field in a B form instruction when the - modifier is used
127 and absolute address is used. */
128 #define BDMA (8)
129 { 16, 0, insert_bdm, extract_bdm,
130 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
131
132 /* The BD field in a B form instruction when the + modifier is used.
133 This sets the y bit of the BO field appropriately. */
134 #define BDP (9)
135 { 16, 0, insert_bdp, extract_bdp,
136 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
137
138 /* The BD field in a B form instruction when the + modifier is used
139 and absolute addressing is used. */
140 #define BDPA (10)
141 { 16, 0, insert_bdp, extract_bdp,
142 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
143
144 /* The BF field in an X or XL form instruction. */
145 #define BF (11)
146 { 3, 23, 0, 0, PPC_OPERAND_CR },
147
148 /* An optional BF field. This is used for comparison instructions,
149 in which an omitted BF field is taken as zero. */
150 #define OBF (12)
151 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
152
153 /* The BFA field in an X or XL form instruction. */
154 #define BFA (13)
155 { 3, 18, 0, 0, PPC_OPERAND_CR },
156
157 /* The BI field in a B form or XL form instruction. */
158 #define BI (14)
159 #define BI_MASK (0x1f << 16)
160 { 5, 16, 0, 0, PPC_OPERAND_CR },
161
162 /* The BO field in a B form instruction. Certain values are
163 illegal. */
164 #define BO (15)
165 #define BO_MASK (0x1f << 21)
166 { 5, 21, insert_bo, extract_bo, 0 },
167
168 /* The BO field in a B form instruction when the + or - modifier is
169 used. This is like the BO field, but it must be even. */
170 #define BOE (16)
171 { 5, 21, insert_boe, extract_boe, 0 },
172
173 /* The BT field in an X or XL form instruction. */
174 #define BT (17)
175 { 5, 21, 0, 0, PPC_OPERAND_CR },
176
177 /* The condition register number portion of the BI field in a B form
178 or XL form instruction. This is used for the extended
179 conditional branch mnemonics, which set the lower two bits of the
180 BI field. This field is optional. */
181 #define CR (18)
182 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
183
184 /* The D field in a D form instruction. This is a displacement off
185 a register, and implies that the next operand is a register in
186 parentheses. */
187 #define D (19)
188 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
189
190 /* The DS field in a DS form instruction. This is like D, but the
191 lower two bits are forced to zero. */
192 #define DS (20)
193 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
194
195 /* The FL1 field in a POWER SC form instruction. */
196 #define FL1 (21)
197 { 4, 12, 0, 0, 0 },
198
199 /* The FL2 field in a POWER SC form instruction. */
200 #define FL2 (22)
201 { 3, 2, 0, 0, 0 },
202
203 /* The FLM field in an XFL form instruction. */
204 #define FLM (23)
205 { 8, 17, 0, 0, 0 },
206
207 /* The FRA field in an X or A form instruction. */
208 #define FRA (24)
209 #define FRA_MASK (0x1f << 16)
210 { 5, 16, 0, 0, PPC_OPERAND_FPR },
211
212 /* The FRB field in an X or A form instruction. */
213 #define FRB (25)
214 #define FRB_MASK (0x1f << 11)
215 { 5, 11, 0, 0, PPC_OPERAND_FPR },
216
217 /* The FRC field in an A form instruction. */
218 #define FRC (26)
219 #define FRC_MASK (0x1f << 6)
220 { 5, 6, 0, 0, PPC_OPERAND_FPR },
221
222 /* The FRS field in an X form instruction or the FRT field in a D, X
223 or A form instruction. */
224 #define FRS (27)
225 #define FRT (FRS)
226 { 5, 21, 0, 0, PPC_OPERAND_FPR },
227
228 /* The FXM field in an XFX instruction. */
229 #define FXM (28)
230 #define FXM_MASK (0xff << 12)
231 { 8, 12, 0, 0, 0 },
232
233 /* The L field in a D or X form instruction. */
234 #define L (29)
235 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
236
237 /* The LEV field in a POWER SC form instruction. */
238 #define LEV (30)
239 { 7, 5, 0, 0, 0 },
240
241 /* The LI field in an I form instruction. The lower two bits are
242 forced to zero. */
243 #define LI (31)
244 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
245
246 /* The LI field in an I form instruction when used as an absolute
247 address. */
248 #define LIA (32)
249 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
250
251 /* The MB field in an M form instruction. */
252 #define MB (33)
253 #define MB_MASK (0x1f << 6)
254 { 5, 6, 0, 0, 0 },
255
256 /* The ME field in an M form instruction. */
257 #define ME (34)
258 #define ME_MASK (0x1f << 1)
259 { 5, 1, 0, 0, 0 },
260
261 /* The MB and ME fields in an M form instruction expressed a single
262 operand which is a bitmask indicating which bits to select. This
263 is a two operand form using PPC_OPERAND_NEXT. See the
264 description in opcode/ppc.h for what this means. */
265 #define MBE (35)
266 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
267 { 32, 0, insert_mbe, extract_mbe, 0 },
268
269 /* The MB or ME field in an MD or MDS form instruction. The high
270 bit is wrapped to the low end. */
271 #define MB6 (37)
272 #define ME6 (MB6)
273 #define MB6_MASK (0x3f << 5)
274 { 6, 5, insert_mb6, extract_mb6, 0 },
275
276 /* The NB field in an X form instruction. The value 32 is stored as
277 0. */
278 #define NB (38)
279 { 6, 11, insert_nb, extract_nb, 0 },
280
281 /* The NSI field in a D form instruction. This is the same as the
282 SI field, only negated. */
283 #define NSI (39)
284 { 16, 0, insert_nsi, extract_nsi,
285 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
286
287 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
288 #define RA (40)
289 #define RA_MASK (0x1f << 16)
290 { 5, 16, 0, 0, PPC_OPERAND_GPR },
291
292 /* The RA field in a D or X form instruction which is an updating
293 load, which means that the RA field may not be zero and may not
294 equal the RT field. */
295 #define RAL (41)
296 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
297
298 /* The RA field in an lmw instruction, which has special value
299 restrictions. */
300 #define RAM (42)
301 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
302
303 /* The RA field in a D or X form instruction which is an updating
304 store or an updating floating point load, which means that the RA
305 field may not be zero. */
306 #define RAS (43)
307 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
308
309 /* The RB field in an X, XO, M, or MDS form instruction. */
310 #define RB (44)
311 #define RB_MASK (0x1f << 11)
312 { 5, 11, 0, 0, PPC_OPERAND_GPR },
313
314 /* The RB field in an X form instruction when it must be the same as
315 the RS field in the instruction. This is used for extended
316 mnemonics like mr. */
317 #define RBS (45)
318 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
319
320 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
321 instruction or the RT field in a D, DS, X, XFX or XO form
322 instruction. */
323 #define RS (46)
324 #define RT (RS)
325 #define RT_MASK (0x1f << 21)
326 { 5, 21, 0, 0, PPC_OPERAND_GPR },
327
328 /* The SH field in an X or M form instruction. */
329 #define SH (47)
330 #define SH_MASK (0x1f << 11)
331 { 5, 11, 0, 0, 0 },
332
333 /* The SH field in an MD form instruction. This is split. */
334 #define SH6 (48)
335 #define SH6_MASK ((0x1f << 11) | (1 << 1))
336 { 6, 1, insert_sh6, extract_sh6, 0 },
337
338 /* The SI field in a D form instruction. */
339 #define SI (49)
340 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
341
342 /* The SI field in a D form instruction when we accept a wide range
343 of positive values. */
344 #define SISIGNOPT (50)
345 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
346
347 /* The SPR field in an XFX form instruction. This is flipped--the
348 lower 5 bits are stored in the upper 5 and vice- versa. */
349 #define SPR (51)
350 #define SPR_MASK (0x3ff << 11)
351 { 10, 11, insert_spr, extract_spr, 0 },
352
353 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
354 #define SPRBAT (52)
355 #define SPRBAT_MASK (0x3 << 17)
356 { 2, 17, 0, 0, 0 },
357
358 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
359 #define SPRG (53)
360 #define SPRG_MASK (0x3 << 16)
361 { 2, 16, 0, 0, 0 },
362
363 /* The SR field in an X form instruction. */
364 #define SR (54)
365 { 4, 16, 0, 0, 0 },
366
367 /* The SV field in a POWER SC form instruction. */
368 #define SV (55)
369 { 14, 2, 0, 0, 0 },
370
371 /* The TBR field in an XFX form instruction. This is like the SPR
372 field, but it is optional. */
373 #define TBR (56)
374 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
375
376 /* The TO field in a D or X form instruction. */
377 #define TO (57)
378 #define TO_MASK (0x1f << 21)
379 { 5, 21, 0, 0, 0 },
380
381 /* The U field in an X form instruction. */
382 #define U (58)
383 { 4, 12, 0, 0, 0 },
384
385 /* The UI field in a D form instruction. */
386 #define UI (59)
387 { 16, 0, 0, 0, 0 },
388 };
389
390 /* The functions used to insert and extract complicated operands. */
391
392 /* The BA field in an XL form instruction when it must be the same as
393 the BT field in the same instruction. This operand is marked FAKE.
394 The insertion function just copies the BT field into the BA field,
395 and the extraction function just checks that the fields are the
396 same. */
397
398 /*ARGSUSED*/
399 static unsigned long
400 insert_bat (insn, value, errmsg)
401 unsigned long insn;
402 long value;
403 const char **errmsg;
404 {
405 return insn | (((insn >> 21) & 0x1f) << 16);
406 }
407
408 static long
409 extract_bat (insn, invalid)
410 unsigned long insn;
411 int *invalid;
412 {
413 if (invalid != (int *) NULL
414 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
415 *invalid = 1;
416 return 0;
417 }
418
419 /* The BB field in an XL form instruction when it must be the same as
420 the BA field in the same instruction. This operand is marked FAKE.
421 The insertion function just copies the BA field into the BB field,
422 and the extraction function just checks that the fields are the
423 same. */
424
425 /*ARGSUSED*/
426 static unsigned long
427 insert_bba (insn, value, errmsg)
428 unsigned long insn;
429 long value;
430 const char **errmsg;
431 {
432 return insn | (((insn >> 16) & 0x1f) << 11);
433 }
434
435 static long
436 extract_bba (insn, invalid)
437 unsigned long insn;
438 int *invalid;
439 {
440 if (invalid != (int *) NULL
441 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
442 *invalid = 1;
443 return 0;
444 }
445
446 /* The BD field in a B form instruction. The lower two bits are
447 forced to zero. */
448
449 /*ARGSUSED*/
450 static unsigned long
451 insert_bd (insn, value, errmsg)
452 unsigned long insn;
453 long value;
454 const char **errmsg;
455 {
456 return insn | (value & 0xfffc);
457 }
458
459 /*ARGSUSED*/
460 static long
461 extract_bd (insn, invalid)
462 unsigned long insn;
463 int *invalid;
464 {
465 if ((insn & 0x8000) != 0)
466 return (insn & 0xfffc) - 0x10000;
467 else
468 return insn & 0xfffc;
469 }
470
471 /* The BD field in a B form instruction when the - modifier is used.
472 This modifier means that the branch is not expected to be taken.
473 We must set the y bit of the BO field to 1 if the offset is
474 negative. When extracting, we require that the y bit be 1 and that
475 the offset be positive, since if the y bit is 0 we just want to
476 print the normal form of the instruction. */
477
478 /*ARGSUSED*/
479 static unsigned long
480 insert_bdm (insn, value, errmsg)
481 unsigned long insn;
482 long value;
483 const char **errmsg;
484 {
485 if ((value & 0x8000) != 0)
486 insn |= 1 << 21;
487 return insn | (value & 0xfffc);
488 }
489
490 static long
491 extract_bdm (insn, invalid)
492 unsigned long insn;
493 int *invalid;
494 {
495 if (invalid != (int *) NULL
496 && ((insn & (1 << 21)) == 0
497 || (insn & (1 << 15)) == 0))
498 *invalid = 1;
499 if ((insn & 0x8000) != 0)
500 return (insn & 0xfffc) - 0x10000;
501 else
502 return insn & 0xfffc;
503 }
504
505 /* The BD field in a B form instruction when the + modifier is used.
506 This is like BDM, above, except that the branch is expected to be
507 taken. */
508
509 /*ARGSUSED*/
510 static unsigned long
511 insert_bdp (insn, value, errmsg)
512 unsigned long insn;
513 long value;
514 const char **errmsg;
515 {
516 if ((value & 0x8000) == 0)
517 insn |= 1 << 21;
518 return insn | (value & 0xfffc);
519 }
520
521 static long
522 extract_bdp (insn, invalid)
523 unsigned long insn;
524 int *invalid;
525 {
526 if (invalid != (int *) NULL
527 && ((insn & (1 << 21)) == 0
528 || (insn & (1 << 15)) != 0))
529 *invalid = 1;
530 if ((insn & 0x8000) != 0)
531 return (insn & 0xfffc) - 0x10000;
532 else
533 return insn & 0xfffc;
534 }
535
536 /* Check for legal values of a BO field. */
537
538 static int
539 valid_bo (long value)
540 {
541 /* Certain encodings have bits that are required to be zero. These
542 are (z must be zero, y may be anything):
543 001zy
544 011zy
545 1z00y
546 1z01y
547 1z1zz
548 */
549 switch (value & 0x14)
550 {
551 default:
552 case 0:
553 return 1;
554 case 0x4:
555 return (value & 0x2) == 0;
556 case 0x10:
557 return (value & 0x8) == 0;
558 case 0x14:
559 return value == 0x14;
560 }
561 }
562
563 /* The BO field in a B form instruction. Warn about attempts to set
564 the field to an illegal value. */
565
566 static unsigned long
567 insert_bo (insn, value, errmsg)
568 unsigned long insn;
569 long value;
570 const char **errmsg;
571 {
572 if (errmsg != (const char **) NULL
573 && ! valid_bo (value))
574 *errmsg = "invalid conditional option";
575 return insn | ((value & 0x1f) << 21);
576 }
577
578 static long
579 extract_bo (insn, invalid)
580 unsigned long insn;
581 int *invalid;
582 {
583 long value;
584
585 value = (insn >> 21) & 0x1f;
586 if (invalid != (int *) NULL
587 && ! valid_bo (value))
588 *invalid = 1;
589 return value;
590 }
591
592 /* The BO field in a B form instruction when the + or - modifier is
593 used. This is like the BO field, but it must be even. When
594 extracting it, we force it to be even. */
595
596 static unsigned long
597 insert_boe (insn, value, errmsg)
598 unsigned long insn;
599 long value;
600 const char **errmsg;
601 {
602 if (errmsg != (const char **) NULL)
603 {
604 if (! valid_bo (value))
605 *errmsg = "invalid conditional option";
606 else if ((value & 1) != 0)
607 *errmsg = "attempt to set y bit when using + or - modifier";
608 }
609 return insn | ((value & 0x1f) << 21);
610 }
611
612 static long
613 extract_boe (insn, invalid)
614 unsigned long insn;
615 int *invalid;
616 {
617 long value;
618
619 value = (insn >> 21) & 0x1f;
620 if (invalid != (int *) NULL
621 && ! valid_bo (value))
622 *invalid = 1;
623 return value & 0x1e;
624 }
625
626 /* The DS field in a DS form instruction. This is like D, but the
627 lower two bits are forced to zero. */
628
629 /*ARGSUSED*/
630 static unsigned long
631 insert_ds (insn, value, errmsg)
632 unsigned long insn;
633 long value;
634 const char **errmsg;
635 {
636 return insn | (value & 0xfffc);
637 }
638
639 /*ARGSUSED*/
640 static long
641 extract_ds (insn, invalid)
642 unsigned long insn;
643 int *invalid;
644 {
645 if ((insn & 0x8000) != 0)
646 return (insn & 0xfffc) - 0x10000;
647 else
648 return insn & 0xfffc;
649 }
650
651 /* The LI field in an I form instruction. The lower two bits are
652 forced to zero. */
653
654 /*ARGSUSED*/
655 static unsigned long
656 insert_li (insn, value, errmsg)
657 unsigned long insn;
658 long value;
659 const char **errmsg;
660 {
661 return insn | (value & 0x3fffffc);
662 }
663
664 /*ARGSUSED*/
665 static long
666 extract_li (insn, invalid)
667 unsigned long insn;
668 int *invalid;
669 {
670 if ((insn & 0x2000000) != 0)
671 return (insn & 0x3fffffc) - 0x4000000;
672 else
673 return insn & 0x3fffffc;
674 }
675
676 /* The MB and ME fields in an M form instruction expressed as a single
677 operand which is itself a bitmask. The extraction function always
678 marks it as invalid, since we never want to recognize an
679 instruction which uses a field of this type. */
680
681 static unsigned long
682 insert_mbe (insn, value, errmsg)
683 unsigned long insn;
684 long value;
685 const char **errmsg;
686 {
687 unsigned long uval;
688 int mb, me;
689
690 uval = value;
691
692 if (uval == 0)
693 {
694 if (errmsg != (const char **) NULL)
695 *errmsg = "illegal bitmask";
696 return insn;
697 }
698
699 me = 31;
700 while ((uval & 1) == 0)
701 {
702 uval >>= 1;
703 --me;
704 }
705
706 mb = me;
707 uval >>= 1;
708 while ((uval & 1) != 0)
709 {
710 uval >>= 1;
711 --mb;
712 }
713
714 if (uval != 0)
715 {
716 if (errmsg != (const char **) NULL)
717 *errmsg = "illegal bitmask";
718 }
719
720 return insn | (mb << 6) | (me << 1);
721 }
722
723 static long
724 extract_mbe (insn, invalid)
725 unsigned long insn;
726 int *invalid;
727 {
728 long ret;
729 int mb, me;
730 int i;
731
732 if (invalid != (int *) NULL)
733 *invalid = 1;
734
735 ret = 0;
736 mb = (insn >> 6) & 0x1f;
737 me = (insn >> 1) & 0x1f;
738 for (i = mb; i < me; i++)
739 ret |= 1 << (31 - i);
740 return ret;
741 }
742
743 /* The MB or ME field in an MD or MDS form instruction. The high bit
744 is wrapped to the low end. */
745
746 /*ARGSUSED*/
747 static unsigned long
748 insert_mb6 (insn, value, errmsg)
749 unsigned long insn;
750 long value;
751 const char **errmsg;
752 {
753 return insn | ((value & 0x1f) << 6) | (value & 0x20);
754 }
755
756 /*ARGSUSED*/
757 static long
758 extract_mb6 (insn, invalid)
759 unsigned long insn;
760 int *invalid;
761 {
762 return ((insn >> 6) & 0x1f) | (insn & 0x20);
763 }
764
765 /* The NB field in an X form instruction. The value 32 is stored as
766 0. */
767
768 static unsigned long
769 insert_nb (insn, value, errmsg)
770 unsigned long insn;
771 long value;
772 const char **errmsg;
773 {
774 if (value < 0 || value > 32)
775 *errmsg = "value out of range";
776 if (value == 32)
777 value = 0;
778 return insn | ((value & 0x1f) << 11);
779 }
780
781 /*ARGSUSED*/
782 static long
783 extract_nb (insn, invalid)
784 unsigned long insn;
785 int *invalid;
786 {
787 long ret;
788
789 ret = (insn >> 11) & 0x1f;
790 if (ret == 0)
791 ret = 32;
792 return ret;
793 }
794
795 /* The NSI field in a D form instruction. This is the same as the SI
796 field, only negated. The extraction function always marks it as
797 invalid, since we never want to recognize an instruction which uses
798 a field of this type. */
799
800 /*ARGSUSED*/
801 static unsigned long
802 insert_nsi (insn, value, errmsg)
803 unsigned long insn;
804 long value;
805 const char **errmsg;
806 {
807 return insn | ((- value) & 0xffff);
808 }
809
810 static long
811 extract_nsi (insn, invalid)
812 unsigned long insn;
813 int *invalid;
814 {
815 if (invalid != (int *) NULL)
816 *invalid = 1;
817 if ((insn & 0x8000) != 0)
818 return - ((insn & 0xffff) - 0x10000);
819 else
820 return - (insn & 0xffff);
821 }
822
823 /* The RA field in a D or X form instruction which is an updating
824 load, which means that the RA field may not be zero and may not
825 equal the RT field. */
826
827 static unsigned long
828 insert_ral (insn, value, errmsg)
829 unsigned long insn;
830 long value;
831 const char **errmsg;
832 {
833 if (value == 0
834 || value == ((insn >> 21) & 0x1f))
835 *errmsg = "invalid register operand when updating";
836 return insn | ((value & 0x1f) << 16);
837 }
838
839 /* The RA field in an lmw instruction, which has special value
840 restrictions. */
841
842 static unsigned long
843 insert_ram (insn, value, errmsg)
844 unsigned long insn;
845 long value;
846 const char **errmsg;
847 {
848 if (value >= ((insn >> 21) & 0x1f))
849 *errmsg = "index register in load range";
850 return insn | ((value & 0x1f) << 16);
851 }
852
853 /* The RA field in a D or X form instruction which is an updating
854 store or an updating floating point load, which means that the RA
855 field may not be zero. */
856
857 static unsigned long
858 insert_ras (insn, value, errmsg)
859 unsigned long insn;
860 long value;
861 const char **errmsg;
862 {
863 if (value == 0)
864 *errmsg = "invalid register operand when updating";
865 return insn | ((value & 0x1f) << 16);
866 }
867
868 /* The RB field in an X form instruction when it must be the same as
869 the RS field in the instruction. This is used for extended
870 mnemonics like mr. This operand is marked FAKE. The insertion
871 function just copies the BT field into the BA field, and the
872 extraction function just checks that the fields are the same. */
873
874 /*ARGSUSED*/
875 static unsigned long
876 insert_rbs (insn, value, errmsg)
877 unsigned long insn;
878 long value;
879 const char **errmsg;
880 {
881 return insn | (((insn >> 21) & 0x1f) << 11);
882 }
883
884 static long
885 extract_rbs (insn, invalid)
886 unsigned long insn;
887 int *invalid;
888 {
889 if (invalid != (int *) NULL
890 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
891 *invalid = 1;
892 return 0;
893 }
894
895 /* The SH field in an MD form instruction. This is split. */
896
897 /*ARGSUSED*/
898 static unsigned long
899 insert_sh6 (insn, value, errmsg)
900 unsigned long insn;
901 long value;
902 const char **errmsg;
903 {
904 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
905 }
906
907 /*ARGSUSED*/
908 static long
909 extract_sh6 (insn, invalid)
910 unsigned long insn;
911 int *invalid;
912 {
913 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
914 }
915
916 /* The SPR field in an XFX form instruction. This is flipped--the
917 lower 5 bits are stored in the upper 5 and vice- versa. */
918
919 static unsigned long
920 insert_spr (insn, value, errmsg)
921 unsigned long insn;
922 long value;
923 const char **errmsg;
924 {
925 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
926 }
927
928 static long
929 extract_spr (insn, invalid)
930 unsigned long insn;
931 int *invalid;
932 {
933 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
934 }
935
936 /* The TBR field in an XFX instruction. This is just like SPR, but it
937 is optional. When TBR is omitted, it must be inserted as 268 (the
938 magic number of the TB register). These functions treat 0
939 (indicating an omitted optional operand) as 268. This means that
940 ``mftb 4,0'' is not handled correctly. This does not matter very
941 much, since the architecture manual does not define mftb as
942 accepting any values other than 268 or 269. */
943
944 #define TB (268)
945
946 static unsigned long
947 insert_tbr (insn, value, errmsg)
948 unsigned long insn;
949 long value;
950 const char **errmsg;
951 {
952 if (value == 0)
953 value = TB;
954 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
955 }
956
957 static long
958 extract_tbr (insn, invalid)
959 unsigned long insn;
960 int *invalid;
961 {
962 long ret;
963
964 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
965 if (ret == TB)
966 ret = 0;
967 return ret;
968 }
969
970 /* Macros used to form opcodes. */
971
972 /* The main opcode. */
973 #define OP(x) (((x) & 0x3f) << 26)
974 #define OP_MASK OP (0x3f)
975
976 /* The main opcode combined with a trap code in the TO field of a D
977 form instruction. Used for extended mnemonics for the trap
978 instructions. */
979 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
980 #define OPTO_MASK (OP_MASK | TO_MASK)
981
982 /* The main opcode combined with a comparison size bit in the L field
983 of a D form or X form instruction. Used for extended mnemonics for
984 the comparison instructions. */
985 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
986 #define OPL_MASK OPL (0x3f,1)
987
988 /* An A form instruction. */
989 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
990 #define A_MASK A (0x3f, 0x1f, 1)
991
992 /* An A_MASK with the FRB field fixed. */
993 #define AFRB_MASK (A_MASK | FRB_MASK)
994
995 /* An A_MASK with the FRC field fixed. */
996 #define AFRC_MASK (A_MASK | FRC_MASK)
997
998 /* An A_MASK with the FRA and FRC fields fixed. */
999 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1000
1001 /* A B form instruction. */
1002 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1003 #define B_MASK B (0x3f, 1, 1)
1004
1005 /* A B form instruction setting the BO field. */
1006 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1007 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1008
1009 /* A BBO_MASK with the y bit of the BO field removed. This permits
1010 matching a conditional branch regardless of the setting of the y
1011 bit. */
1012 #define Y_MASK (1 << 21)
1013 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1014
1015 /* A B form instruction setting the BO field and the condition bits of
1016 the BI field. */
1017 #define BBOCB(op, bo, cb, aa, lk) \
1018 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1019 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1020
1021 /* A BBOCB_MASK with the y bit of the BO field removed. */
1022 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1023
1024 /* A BBOYCB_MASK in which the BI field is fixed. */
1025 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1026
1027 /* The main opcode mask with the RA field clear. */
1028 #define DRA_MASK (OP_MASK | RA_MASK)
1029
1030 /* A DS form instruction. */
1031 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1032 #define DS_MASK DSO (0x3f, 3)
1033
1034 /* An M form instruction. */
1035 #define M(op, rc) (OP (op) | ((rc) & 1))
1036 #define M_MASK M (0x3f, 1)
1037
1038 /* An M form instruction with the ME field specified. */
1039 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1040
1041 /* An M_MASK with the MB and ME fields fixed. */
1042 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1043
1044 /* An M_MASK with the SH and ME fields fixed. */
1045 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1046
1047 /* An MD form instruction. */
1048 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1049 #define MD_MASK MD (0x3f, 0x7, 1)
1050
1051 /* An MD_MASK with the MB field fixed. */
1052 #define MDMB_MASK (MD_MASK | MB6_MASK)
1053
1054 /* An MD_MASK with the SH field fixed. */
1055 #define MDSH_MASK (MD_MASK | SH6_MASK)
1056
1057 /* An MDS form instruction. */
1058 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1059 #define MDS_MASK MDS (0x3f, 0xf, 1)
1060
1061 /* An MDS_MASK with the MB field fixed. */
1062 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1063
1064 /* An SC form instruction. */
1065 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1066 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
1067
1068 /* An X form instruction. */
1069 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1070
1071 /* An X form instruction with the RC bit specified. */
1072 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1073
1074 /* The mask for an X form instruction. */
1075 #define X_MASK XRC (0x3f, 0x3ff, 1)
1076
1077 /* An X_MASK with the RA field fixed. */
1078 #define XRA_MASK (X_MASK | RA_MASK)
1079
1080 /* An X_MASK with the RB field fixed. */
1081 #define XRB_MASK (X_MASK | RB_MASK)
1082
1083 /* An X_MASK with the RT field fixed. */
1084 #define XRT_MASK (X_MASK | RT_MASK)
1085
1086 /* An X_MASK with the RA and RB fields fixed. */
1087 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1088
1089 /* An X_MASK with the RT and RA fields fixed. */
1090 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1091
1092 /* An X form comparison instruction. */
1093 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1094
1095 /* The mask for an X form comparison instruction. */
1096 #define XCMP_MASK (X_MASK | (1 << 22))
1097
1098 /* The mask for an X form comparison instruction with the L field
1099 fixed. */
1100 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1101
1102 /* An X form trap instruction with the TO field specified. */
1103 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1104 #define XTO_MASK (X_MASK | TO_MASK)
1105
1106 /* An XFL form instruction. */
1107 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1108 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1109
1110 /* An XL form instruction with the LK field set to 0. */
1111 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1112
1113 /* An XL form instruction which uses the LK field. */
1114 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1115
1116 /* The mask for an XL form instruction. */
1117 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1118
1119 /* An XL form instruction which explicitly sets the BO field. */
1120 #define XLO(op, bo, xop, lk) \
1121 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1122 #define XLO_MASK (XL_MASK | BO_MASK)
1123
1124 /* An XL form instruction which explicitly sets the y bit of the BO
1125 field. */
1126 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1127 #define XLYLK_MASK (XL_MASK | Y_MASK)
1128
1129 /* An XL form instruction which sets the BO field and the condition
1130 bits of the BI field. */
1131 #define XLOCB(op, bo, cb, xop, lk) \
1132 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1133 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1134
1135 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1136 #define XLBB_MASK (XL_MASK | BB_MASK)
1137 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1138 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1139
1140 /* An XL_MASK with the BO and BB fields fixed. */
1141 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1142
1143 /* An XL_MASK with the BO, BI and BB fields fixed. */
1144 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1145
1146 /* An XO form instruction. */
1147 #define XO(op, xop, oe, rc) \
1148 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1149 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1150
1151 /* An XO_MASK with the RB field fixed. */
1152 #define XORB_MASK (XO_MASK | RB_MASK)
1153
1154 /* An XS form instruction. */
1155 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1156 #define XS_MASK XS (0x3f, 0x1ff, 1)
1157
1158 /* A mask for the FXM version of an XFX form instruction. */
1159 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1160
1161 /* An XFX form instruction with the FXM field filled in. */
1162 #define XFXM(op, xop, fxm) \
1163 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1164
1165 /* An XFX form instruction with the SPR field filled in. */
1166 #define XSPR(op, xop, spr) \
1167 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1168 #define XSPR_MASK (X_MASK | SPR_MASK)
1169
1170 /* An XFX form instruction with the SPR field filled in except for the
1171 SPRBAT field. */
1172 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1173
1174 /* An XFX form instruction with the SPR field filled in except for the
1175 SPRG field. */
1176 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1177
1178 /* The BO encodings used in extended conditional branch mnemonics. */
1179 #define BODNZF (0x0)
1180 #define BODNZFP (0x1)
1181 #define BODZF (0x2)
1182 #define BODZFP (0x3)
1183 #define BOF (0x4)
1184 #define BOFP (0x5)
1185 #define BODNZT (0x8)
1186 #define BODNZTP (0x9)
1187 #define BODZT (0xa)
1188 #define BODZTP (0xb)
1189 #define BOT (0xc)
1190 #define BOTP (0xd)
1191 #define BODNZ (0x10)
1192 #define BODNZP (0x11)
1193 #define BODZ (0x12)
1194 #define BODZP (0x13)
1195 #define BOU (0x14)
1196
1197 /* The BI condition bit encodings used in extended conditional branch
1198 mnemonics. */
1199 #define CBLT (0)
1200 #define CBGT (1)
1201 #define CBEQ (2)
1202 #define CBSO (3)
1203
1204 /* The TO encodings used in extended trap mnemonics. */
1205 #define TOLGT (0x1)
1206 #define TOLLT (0x2)
1207 #define TOEQ (0x4)
1208 #define TOLGE (0x5)
1209 #define TOLNL (0x5)
1210 #define TOLLE (0x6)
1211 #define TOLNG (0x6)
1212 #define TOGT (0x8)
1213 #define TOGE (0xc)
1214 #define TONL (0xc)
1215 #define TOLT (0x10)
1216 #define TOLE (0x14)
1217 #define TONG (0x14)
1218 #define TONE (0x18)
1219 #define TOU (0x1f)
1220
1221 /* Smaller names for the flags so each entry in the opcodes table will
1222 fit on a single line. */
1223 #undef PPC
1224 #define PPC PPC_OPCODE_PPC
1225 #define POWER PPC_OPCODE_POWER
1226 #define POWER2 PPC_OPCODE_POWER2
1227 #define B32 PPC_OPCODE_32
1228 #define B64 PPC_OPCODE_64
1229 #define M601 PPC_OPCODE_601
1230
1231 /* The opcode table.
1232
1233 The format of the opcode table is:
1234
1235 NAME OPCODE MASK FLAGS { OPERANDS }
1236
1237 NAME is the name of the instruction.
1238 OPCODE is the instruction opcode.
1239 MASK is the opcode mask; this is used to tell the disassembler
1240 which bits in the actual opcode must match OPCODE.
1241 FLAGS are flags indicated what processors support the instruction.
1242 OPERANDS is the list of operands.
1243
1244 The disassembler reads the table in order and prints the first
1245 instruction which matches, so this table is sorted to put more
1246 specific instructions before more general instructions. It is also
1247 sorted by major opcode. */
1248
1249 const struct powerpc_opcode powerpc_opcodes[] = {
1250 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1251 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1252 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1253 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1254 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1255 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1256 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1257 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1258 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1259 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1260 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1261 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1262 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1263 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1264 { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1265
1266 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1267 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1268 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1269 { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1270 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1271 { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1272 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1273 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1274 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1275 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1276 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1277 { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1278 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1279 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1280 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1281 { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1282 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1283 { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1284 { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1285 { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1286 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1287 { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1288 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1289 { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1290 { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1291 { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1292 { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1293 { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1294 { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1295 { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1296
1297 { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1298 { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1299
1300 { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1301 { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1302
1303 { "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1304
1305 { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1306 { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1307 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1308 { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1309
1310 { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1311 { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1312 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1313 { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1314
1315 { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1316 { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1317 { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1318
1319 { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1320 { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1321 { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1322
1323 { "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1324 { "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1325 { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1326 { "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1327 { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1328 { "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1329
1330 { "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1331 { "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1332 { "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1333 { "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1334 { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1335
1336 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1337 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1338 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1339 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1340 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1341 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1342 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1343 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1344 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1345 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1346 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1347 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1348 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1349 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1350 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1351 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1352 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1353 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1354 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1355 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1356 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1357 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1358 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1359 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1360 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1361 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1362 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1363 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1364 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1365 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1366 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1367 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1368 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1369 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1370 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1371 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1372 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1373 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1374 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1375 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1376 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1377 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1378 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1379 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1380 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1381 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1382 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1383 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1384 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1385 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1386 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1387 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1388 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1389 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1390 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1391 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1392 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1393 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1394 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1395 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1396 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1397 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1398 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1399 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1400 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1401 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1402 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1403 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1404 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1405 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1406 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1407 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1408 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1409 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1410 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1411 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1412 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1413 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1414 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1415 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1416 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1417 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1418 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1419 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1420 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1421 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1422 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1423 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1424 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1425 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1426 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1427 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1428 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1429 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1430 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1431 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1432 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1433 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1434 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1435 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1436 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1437 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1438 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1439 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1440 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1441 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1442 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1443 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1444 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1445 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1446 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1447 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1448 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1449 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1450 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1451 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1452 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1453 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1454 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1455 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1456 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1457 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1458 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1459 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1460 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1461 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1462 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1463 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1464 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1465 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1466 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1467 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1468 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1469 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1470 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1471 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1472 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1473 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1474 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1475 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1476 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1477 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1478 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1479 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1480 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1481 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1482 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1483 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1484 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1485 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1486 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1487 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1488 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1489 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1490 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1491 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1492 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1493 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1494 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1495 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1496 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1497 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1498 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1499 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1500 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1501 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1502 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1503 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1504 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1505 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1506 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1507 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1508 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1509 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1510 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1511 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1512 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1513 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1514 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1515 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1516 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1517 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1518 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1519 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1520 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1521 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1522 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1523 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1524 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1525 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1526 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1527 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1528 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1529 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1530 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1531 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1532 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1533 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1534 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1535 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1536 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1537 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1538 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1539 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1540 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1541 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1542 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1543 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1544 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1545 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1546 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1547 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1548 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1549 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1550 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1551 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1552 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1553 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1554 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1555 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1556 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1557 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1558 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1559 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1560 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1561 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1562 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1563 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1564 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1565 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1566 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1567 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1568 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1569 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1570 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1571 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1572 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1573 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1574 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1575 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1576 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1577 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1578 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1579 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1580 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1581 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1582 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1583 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1584 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1585 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1586 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1587 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1588 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1589 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1590 { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1591 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1592 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1593 { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1594 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1595 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1596 { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1597 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1598 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1599 { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1600
1601 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1602 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1603 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1604 { "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1605 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1606
1607 { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1608 { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1609 { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1610 { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1611
1612 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1613
1614 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1615 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1616 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1617 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1618 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1619 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1620 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1621 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1622 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1623 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1624 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1625 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1626 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1627 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1628 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1629 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1630 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1631 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1632 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1633 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1634 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1635 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1636 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1637 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1638 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1639 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1640 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1641 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1642 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1643 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1644 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1645 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1646 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1647 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1648 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1649 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1650 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1651 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1652 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1653 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1654 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1655 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1656 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1657 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1658 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1659 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1660 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1661 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1662 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1663 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1664 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1665 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1666 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1667 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1668 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1669 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1670 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1671 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1672 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1673 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1674 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1675 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1676 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1677 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1678 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1679 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1680 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1681 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1682 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1683 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1684 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1685 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1686 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1687 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1688 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1689 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1690 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1691 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1692 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1693 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1694 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1695 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1696 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1697 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1698 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1699 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1700 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1701 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1702 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1703 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1704 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1705 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1706 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1707 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1708 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1709 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1710 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1711 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1712 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1713 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1714 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1715 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1716 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1717 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1718 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1719 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1720 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1721 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1722 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1723 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1724 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1725 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1726 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1727 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1728 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1729 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1730 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1731 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1732 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1733 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1734 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1735 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1736 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1737 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1738 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1739 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1740 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1741 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1742 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1743 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1744 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1745 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1746 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1747 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1748 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1749 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1750 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1751 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1752 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1753 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1754 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1755 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1756 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1757 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1758 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1759 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1760 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1761 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1762 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1763 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1764 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1765 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1766 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1767 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1768 { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1769 { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1770
1771 { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1772 { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1773
1774 { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1775 { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
1776
1777 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1778
1779 { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1780
1781 { "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1782 { "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1783
1784 { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1785 { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1786
1787 { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1788
1789 { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1790
1791 { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1792 { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1793
1794 { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1795
1796 { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1797 { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1798
1799 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1800 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1801 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1802 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1803 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1804 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1805 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1806 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1807 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1808 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1809 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1810 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1811 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1812 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1813 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1814 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1815 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1816 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1817 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1818 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1819 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1820 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1821 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1822 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1823 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1824 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1825 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1826 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1827 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1828 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1829 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1830 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1831 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1832 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1833 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1834 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1835 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1836 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1837 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1838 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1839 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1840 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1841 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1842 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1843 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1844 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1845 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1846 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1847 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1848 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1849 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1850 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1851 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1852 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1853 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1854 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1855 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1856 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1857 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1858 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1859 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1860 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1861 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1862 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1863 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1864 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1865 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1866 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1867 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1868 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1869 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1870 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1871 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1872 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1873 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1874 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1875 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1876 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1877 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1878 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1879 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1880 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1881 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1882 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1883 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1884 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1885 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1886 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1887 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1888 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1889 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1890 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1891 { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1892 { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1893
1894 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1895 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1896
1897 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1898 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1899
1900 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1901 { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1902 { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1903 { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1904 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1905 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1906 { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1907 { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1908
1909 { "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1910 { "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1911
1912 { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1913 { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1914 { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1915 { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1916 { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1917 { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1918
1919 { "nop", OP(24), 0xffffffff, PPC, { 0 } },
1920 { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1921 { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1922
1923 { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1924 { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1925
1926 { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1927 { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1928
1929 { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1930 { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1931
1932 { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1933 { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1934
1935 { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1936 { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1937
1938 { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1939 { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1940 { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1941 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1942 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1943 { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1944
1945 { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1946 { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1947
1948 { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1949 { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1950
1951 { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1952 { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1953
1954 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1955 { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1956 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1957 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1958
1959 { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1960 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1961
1962 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1963 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1964 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
1965 { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
1966
1967 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1968 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1969 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1970 { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1971 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1972 { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1973 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1974 { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1975 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1976 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1977 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
1978 { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
1979 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
1980 { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
1981 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
1982 { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
1983 { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
1984 { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
1985 { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
1986 { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
1987 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
1988 { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
1989 { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
1990 { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
1991 { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
1992 { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
1993 { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
1994 { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
1995 { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
1996 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
1997 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
1998
1999 { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
2000 { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
2001 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2002 { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
2003 { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
2004 { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
2005 { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
2006 { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
2007 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2008 { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
2009 { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
2010 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2011
2012 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2013 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2014
2015 { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
2016 { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
2017 { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
2018 { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
2019 { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
2020 { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
2021 { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
2022 { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
2023
2024 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2025 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2026
2027 { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
2028
2029 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2030
2031 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2032
2033 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2034 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2035
2036 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2037 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2038 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2039 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2040
2041 { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
2042 { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
2043 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
2044 { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
2045
2046 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2047 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2048
2049 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2050 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2051
2052 { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2053 { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
2054
2055 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2056 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2057 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
2058 { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
2059
2060 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2061 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2062 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2063 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2064 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2065 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2066 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2067 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2068
2069 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
2070
2071 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2072
2073 { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
2074 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2075
2076 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
2077 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
2078
2079 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2080 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2081
2082 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
2083 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
2084 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
2085 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
2086 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
2087 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
2088 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
2089 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
2090 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
2091 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
2092 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
2093 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
2094 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
2095 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2096 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2097
2098 { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2099 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2100
2101 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2102 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2103
2104 { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2105
2106 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2107
2108 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2109
2110 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2111
2112 { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2113 { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2114 { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2115 { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2116
2117 { "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2118 { "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2119 { "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2120 { "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2121
2122 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2123
2124 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2125
2126 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2127 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2128 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2129 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2130
2131 { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2132 { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2133 { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2134 { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2135 { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2136 { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2137 { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2138 { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2139
2140 { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2141 { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2142 { "adde.", XO(31,138,0,1), <