File: /usr/src/linux/arch/sh/kernel/setup_dc.c
1 /* arch/sh/kernel/setup_dc.c
2 *
3 * Hardware support for the Sega Dreamcast.
4 *
5 * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
6 *
7 * This file is part of the LinuxDC project (www.linuxdc.org)
8 *
9 * Released under the terms of the GNU GPL v2.0.
10 *
11 * This file originally bore the message (with enclosed-$):
12 * Id: setup_dc.c,v 1.5 2001/05/24 05:09:16 mrbrown Exp
13 * SEGA Dreamcast support
14 */
15
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/param.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
22
23 #include <asm/io.h>
24 #include <asm/irq.h>
25 #include <asm/dc_sysasic.h>
26
27 int __init gapspci_init(void);
28
29 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
30
31 /* Dreamcast System ASIC Hardware Events -
32
33 The Dreamcast's System ASIC (located on the PowerVR2 chip) is responsible
34 for receiving hardware events from system peripherals and triggering an
35 SH7750 IRQ. Hardware events can trigger IRQs 13, 11, or 9 depending on
36 which bits are set in the Event Mask Registers (EMRs). When a hardware
37 event is triggered, it's corresponding bit in the Event Status Registers
38 (ESRs) is set, and that bit should be rewritten to the ESR to acknowledge
39 that event.
40
41 There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
42 types can be found in include/asm-sh/dc_sysasic.h. There are three groups
43 of EMRs that parallel the ESRs. Each EMR group corresponds to an IRQ, so
44 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 triggers
45 IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
46
47 In the kernel, these events are mapped to virtual IRQs so that drivers can
48 respond to them as they would a normal interrupt. In order to keep this
49 mapping simple, the events are mapped as:
50
51 6900/6910 - Events 0-31, IRQ 13
52 6904/6924 - Events 32-63, IRQ 11
53 6908/6938 - Events 64-95, IRQ 9
54
55 */
56
57 #define ESR_BASE 0x005f6900 /* Base event status register */
58 #define EMR_BASE 0x005f6910 /* Base event mask register */
59
60 /* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
61 1 = 0x6920, 2 = 0x6930; also determine the event offset */
62 #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
63
64 /* Return the hardware event's bit positon within the EMR/ESR */
65 #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
66
67 /* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
68 (logically mapped to the corresponding bit for the hardware event). */
69
70 /* Disable the hardware event by masking its bit in its EMR */
71 static inline void disable_systemasic_irq(unsigned int irq)
72 {
73 unsigned long flags;
74 __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
75 __u32 mask;
76
77 save_and_cli(flags);
78 mask = inl(emr);
79 mask &= ~(1 << EVENT_BIT(irq));
80 outl(mask, emr);
81 restore_flags(flags);
82 }
83
84 /* Enable the hardware event by setting its bit in its EMR */
85 static inline void enable_systemasic_irq(unsigned int irq)
86 {
87 unsigned long flags;
88 __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
89 __u32 mask;
90
91 save_and_cli(flags);
92 mask = inl(emr);
93 mask |= (1 << EVENT_BIT(irq));
94 outl(mask, emr);
95 restore_flags(flags);
96 }
97
98 /* Acknowledge a hardware event by writing its bit back to its ESR */
99 static void ack_systemasic_irq(unsigned int irq)
100 {
101 __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
102 disable_systemasic_irq(irq);
103 outl((1 << EVENT_BIT(irq)), esr);
104 }
105
106 /* After a IRQ has been ack'd and responded to, it needs to be renabled */
107 static void end_systemasic_irq(unsigned int irq)
108 {
109 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
110 enable_systemasic_irq(irq);
111 }
112
113 static unsigned int startup_systemasic_irq(unsigned int irq)
114 {
115 enable_systemasic_irq(irq);
116
117 return 0;
118 }
119
120 static void shutdown_systemasic_irq(unsigned int irq)
121 {
122 disable_systemasic_irq(irq);
123 }
124
125 static struct hw_interrupt_type systemasic_int = {
126 typename: "System ASIC",
127 startup: startup_systemasic_irq,
128 shutdown: shutdown_systemasic_irq,
129 enable: enable_systemasic_irq,
130 disable: disable_systemasic_irq,
131 ack: ack_systemasic_irq,
132 end: end_systemasic_irq,
133 };
134
135 /*
136 * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
137 */
138 int systemasic_irq_demux(int irq)
139 {
140 __u32 emr, esr, status, level;
141 __u32 j, bit;
142
143 switch (irq) {
144 case 13:
145 level = 0;
146 break;
147 case 11:
148 level = 1;
149 break;
150 case 9:
151 level = 2;
152 break;
153 default:
154 return irq;
155 }
156 emr = EMR_BASE + (level << 4) + (level << 2);
157 esr = ESR_BASE + (level << 2);
158
159 /* Mask the ESR to filter any spurious, unwanted interrtupts */
160 status = inl(esr);
161 status &= inl(emr);
162
163 /* Now scan and find the first set bit as the event to map */
164 for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
165 if (status & bit) {
166 irq = HW_EVENT_IRQ_BASE + j + (level << 5);
167 return irq;
168 }
169 }
170
171 /* Not reached */
172 return irq;
173 }
174
175 int __init setup_dreamcast(void)
176 {
177 int i;
178
179 /* Mask all hardware events */
180 /* XXX */
181
182 /* Acknowledge any previous events */
183 /* XXX */
184
185 /* Assign all virtual IRQs to the System ASIC int. handler */
186 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
187 irq_desc[i].handler = &systemasic_int;
188
189 #ifdef CONFIG_PCI
190 gapspci_init();
191 #endif
192
193 printk(KERN_INFO "SEGA Dreamcast support.\n");
194 #if 0
195 printk(KERN_INFO "BCR1: 0x%08x\n", ctrl_inl(0xff800000));
196 printk(KERN_INFO "BCR2: 0x%08x\n", ctrl_inw(0xff800004));
197 printk(KERN_INFO "WCR1: 0x%08x\n", ctrl_inl(0xff800008));
198 printk(KERN_INFO "WCR2: 0x%08x\n", ctrl_inl(0xff80000c));
199 printk(KERN_INFO "WCR3: 0x%08x\n", ctrl_inl(0xff800010));
200 printk(KERN_INFO "MCR: 0x%08x\n", ctrl_inl(0xff800014));
201 printk(KERN_INFO "PCR: 0x%08x\n", ctrl_inw(0xff800018));
202 /*
203 * BCR1: 0xa3020008
204 * BCR2: 0x0001
205 * WCR1: 0x01110111
206 * WCR2: 0x618066d8
207 * WCR3: 0x07777777
208 * MCR: 0xc00a0e24
209 * PCR: 0x0000
210 */
211 #endif
212 return 0;
213 }
214