File: /usr/src/linux/arch/alpha/kernel/core_irongate.c
1 /*
2 * linux/arch/alpha/kernel/core_irongate.c
3 *
4 * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
5 *
6 * Copyright (C) 1999 Alpha Processor, Inc.,
7 * (David Daniel, Stig Telfer, Soohoon Lee)
8 *
9 * Code common to all IRONGATE core logic chips.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17
18 #include <asm/ptrace.h>
19 #include <asm/system.h>
20 #include <asm/pci.h>
21 #include <asm/hwrpb.h>
22
23 #define __EXTERN_INLINE inline
24 #include <asm/io.h>
25 #include <asm/core_irongate.h>
26 #undef __EXTERN_INLINE
27
28 #include "proto.h"
29 #include "pci_impl.h"
30
31 #undef DEBUG_IRONGATE /* define to enable verbose Irongate debug */
32
33 #define IRONGATE_DEFAULT_AGP_APER_SIZE (256*1024*1024) /* 256MB */
34
35 /*
36 * BIOS32-style PCI interface:
37 */
38
39 #define DEBUG_CONFIG 0
40
41 #if DEBUG_CONFIG
42 # define DBG_CFG(args) printk args
43 #else
44 # define DBG_CFG(args)
45 #endif
46
47
48 /*
49 * Given a bus, device, and function number, compute resulting
50 * configuration space address accordingly. It is therefore not safe
51 * to have concurrent invocations to configuration space access
52 * routines, but there really shouldn't be any need for this.
53 *
54 * addr[31:24] reserved
55 * addr[23:16] bus number (8 bits = 128 possible buses)
56 * addr[15:11] Device number (5 bits)
57 * addr[10: 8] function number
58 * addr[ 7: 2] register number
59 *
60 * For IRONGATE:
61 * if (bus = addr[23:16]) == 0
62 * then
63 * type 0 config cycle:
64 * addr_on_pci[31:11] = id selection for device = addr[15:11]
65 * addr_on_pci[10: 2] = addr[10: 2] ???
66 * addr_on_pci[ 1: 0] = 00
67 * else
68 * type 1 config cycle (pass on with no decoding):
69 * addr_on_pci[31:24] = 0
70 * addr_on_pci[23: 2] = addr[23: 2]
71 * addr_on_pci[ 1: 0] = 01
72 * fi
73 *
74 * Notes:
75 * The function number selects which function of a multi-function device
76 * (e.g., SCSI and Ethernet).
77 *
78 * The register selects a DWORD (32 bit) register offset. Hence it
79 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
80 * bits.
81 */
82
83 static int
84 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
85 unsigned char *type1)
86 {
87 unsigned long addr;
88 u8 bus = dev->bus->number;
89 u8 device_fn = dev->devfn;
90
91 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
92 "pci_addr=0x%p, type1=0x%p)\n",
93 bus, device_fn, where, pci_addr, type1));
94
95 *type1 = (bus != 0);
96
97 addr = (bus << 16) | (device_fn << 8) | where;
98 addr |= IRONGATE_CONF;
99
100 *pci_addr = addr;
101 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
102 return 0;
103 }
104
105 static int
106 irongate_read_config_byte(struct pci_dev *dev, int where, u8 *value)
107 {
108 unsigned long addr;
109 unsigned char type1;
110
111 if (mk_conf_addr(dev, where, &addr, &type1))
112 return PCIBIOS_DEVICE_NOT_FOUND;
113
114 *value = __kernel_ldbu(*(vucp)addr);
115 return PCIBIOS_SUCCESSFUL;
116 }
117
118 static int
119 irongate_read_config_word(struct pci_dev *dev, int where, u16 *value)
120 {
121 unsigned long addr;
122 unsigned char type1;
123
124 if (mk_conf_addr(dev, where, &addr, &type1))
125 return PCIBIOS_DEVICE_NOT_FOUND;
126
127 *value = __kernel_ldwu(*(vusp)addr);
128 return PCIBIOS_SUCCESSFUL;
129 }
130
131 static int
132 irongate_read_config_dword(struct pci_dev *dev, int where, u32 *value)
133 {
134 unsigned long addr;
135 unsigned char type1;
136
137 if (mk_conf_addr(dev, where, &addr, &type1))
138 return PCIBIOS_DEVICE_NOT_FOUND;
139
140 *value = *(vuip)addr;
141 return PCIBIOS_SUCCESSFUL;
142 }
143
144 static int
145 irongate_write_config_byte(struct pci_dev *dev, int where, u8 value)
146 {
147 unsigned long addr;
148 unsigned char type1;
149
150 if (mk_conf_addr(dev, where, &addr, &type1))
151 return PCIBIOS_DEVICE_NOT_FOUND;
152
153 __kernel_stb(value, *(vucp)addr);
154 mb();
155 __kernel_ldbu(*(vucp)addr);
156 return PCIBIOS_SUCCESSFUL;
157 }
158
159 static int
160 irongate_write_config_word(struct pci_dev *dev, int where, u16 value)
161 {
162 unsigned long addr;
163 unsigned char type1;
164
165 if (mk_conf_addr(dev, where, &addr, &type1))
166 return PCIBIOS_DEVICE_NOT_FOUND;
167
168 __kernel_stw(value, *(vusp)addr);
169 mb();
170 __kernel_ldwu(*(vusp)addr);
171 return PCIBIOS_SUCCESSFUL;
172 }
173
174 static int
175 irongate_write_config_dword(struct pci_dev *dev, int where, u32 value)
176 {
177 unsigned long addr;
178 unsigned char type1;
179
180 if (mk_conf_addr(dev, where, &addr, &type1))
181 return PCIBIOS_DEVICE_NOT_FOUND;
182
183 *(vuip)addr = value;
184 mb();
185 *(vuip)addr;
186 return PCIBIOS_SUCCESSFUL;
187 }
188
189
190 struct pci_ops irongate_pci_ops =
191 {
192 read_byte: irongate_read_config_byte,
193 read_word: irongate_read_config_word,
194 read_dword: irongate_read_config_dword,
195 write_byte: irongate_write_config_byte,
196 write_word: irongate_write_config_word,
197 write_dword: irongate_write_config_dword
198 };
199
200 #ifdef DEBUG_IRONGATE
201 static void
202 irongate_register_dump(const char *function_name)
203 {
204 printk("%s: Irongate registers:\n"
205 "\tFunction 0:\n"
206 "\tdev_vendor\t0x%08x\n"
207 "\tstat_cmd\t0x%08x\n"
208 "\tclass\t\t0x%08x\n"
209 "\tlatency\t\t0x%08x\n"
210 "\tbar0\t\t0x%08x\n"
211 "\tbar1\t\t0x%08x\n"
212 "\tbar2\t\t0x%08x\n"
213 "\trsrvd0[0]\t0x%08x\n"
214 "\trsrvd0[1]\t0x%08x\n"
215 "\trsrvd0[2]\t0x%08x\n"
216 "\trsrvd0[3]\t0x%08x\n"
217 "\trsrvd0[4]\t0x%08x\n"
218 "\trsrvd0[5]\t0x%08x\n"
219 "\tcapptr\t\t0x%08x\n"
220 "\trsrvd1[0]\t0x%08x\n"
221 "\trsrvd1[1]\t0x%08x\n"
222 "\tbacsr10\t\t0x%08x\n"
223 "\tbacsr32\t\t0x%08x\n"
224 "\tbacsr54\t\t0x%08x\n"
225 "\trsrvd2[0]\t0x%08x\n"
226 "\tdrammap\t\t0x%08x\n"
227 "\tdramtm\t\t0x%08x\n"
228 "\tdramms\t\t0x%08x\n"
229 "\trsrvd3[0]\t0x%08x\n"
230 "\tbiu0\t\t0x%08x\n"
231 "\tbiusip\t\t0x%08x\n"
232 "\trsrvd4[0]\t0x%08x\n"
233 "\trsrvd4[1]\t0x%08x\n"
234 "\tmro\t\t0x%08x\n"
235 "\trsrvd5[0]\t0x%08x\n"
236 "\trsrvd5[1]\t0x%08x\n"
237 "\trsrvd5[2]\t0x%08x\n"
238 "\twhami\t\t0x%08x\n"
239 "\tpciarb\t\t0x%08x\n"
240 "\tpcicfg\t\t0x%08x\n"
241 "\trsrvd6[0]\t0x%08x\n"
242 "\trsrvd6[1]\t0x%08x\n"
243 "\trsrvd6[2]\t0x%08x\n"
244 "\trsrvd6[3]\t0x%08x\n"
245 "\trsrvd6[4]\t0x%08x\n"
246 "\tagpcap\t\t0x%08x\n"
247 "\tagpstat\t\t0x%08x\n"
248 "\tagpcmd\t\t0x%08x\n"
249 "\tagpva\t\t0x%08x\n"
250 "\tagpmode\t\t0x%08x\n"
251
252 "\n\tFunction 1:\n"
253 "\tdev_vendor:\t0x%08x\n"
254 "\tcmd_status:\t0x%08x\n"
255 "\trevid_etc :\t0x%08x\n"
256 "\thtype_etc :\t0x%08x\n"
257 "\trsrvd0[0] :\t0x%08x\n"
258 "\trsrvd0[1] :\t0x%08x\n"
259 "\tbus_nmbers:\t0x%08x\n"
260 "\tio_baselim:\t0x%08x\n"
261 "\tmem_bselim:\t0x%08x\n"
262 "\tpf_baselib:\t0x%08x\n"
263 "\trsrvd1[0] :\t0x%08x\n"
264 "\trsrvd1[1] :\t0x%08x\n"
265 "\tio_baselim:\t0x%08x\n"
266 "\trsrvd2[0] :\t0x%08x\n"
267 "\trsrvd2[1] :\t0x%08x\n"
268 "\tinterrupt :\t0x%08x\n",
269
270 function_name,
271 IRONGATE0->dev_vendor,
272 IRONGATE0->stat_cmd,
273 IRONGATE0->class,
274 IRONGATE0->latency,
275 IRONGATE0->bar0,
276 IRONGATE0->bar1,
277 IRONGATE0->bar2,
278 IRONGATE0->rsrvd0[0],
279 IRONGATE0->rsrvd0[1],
280 IRONGATE0->rsrvd0[2],
281 IRONGATE0->rsrvd0[3],
282 IRONGATE0->rsrvd0[4],
283 IRONGATE0->rsrvd0[5],
284 IRONGATE0->capptr,
285 IRONGATE0->rsrvd1[0],
286 IRONGATE0->rsrvd1[1],
287 IRONGATE0->bacsr10,
288 IRONGATE0->bacsr32,
289 IRONGATE0->bacsr54,
290 IRONGATE0->rsrvd2[0],
291 IRONGATE0->drammap,
292 IRONGATE0->dramtm,
293 IRONGATE0->dramms,
294 IRONGATE0->rsrvd3[0],
295 IRONGATE0->biu0,
296 IRONGATE0->biusip,
297 IRONGATE0->rsrvd4[0],
298 IRONGATE0->rsrvd4[1],
299 IRONGATE0->mro,
300 IRONGATE0->rsrvd5[0],
301 IRONGATE0->rsrvd5[1],
302 IRONGATE0->rsrvd5[2],
303 IRONGATE0->whami,
304 IRONGATE0->pciarb,
305 IRONGATE0->pcicfg,
306 IRONGATE0->rsrvd6[0],
307 IRONGATE0->rsrvd6[1],
308 IRONGATE0->rsrvd6[2],
309 IRONGATE0->rsrvd6[3],
310 IRONGATE0->rsrvd6[4],
311 IRONGATE0->agpcap,
312 IRONGATE0->agpstat,
313 IRONGATE0->agpcmd,
314 IRONGATE0->agpva,
315 IRONGATE0->agpmode,
316 IRONGATE1->dev_vendor,
317 IRONGATE1->stat_cmd,
318 IRONGATE1->class,
319 IRONGATE1->htype,
320 IRONGATE1->rsrvd0[0],
321 IRONGATE1->rsrvd0[1],
322 IRONGATE1->busnos,
323 IRONGATE1->io_baselim_regs,
324 IRONGATE1->mem_baselim,
325 IRONGATE1->pfmem_baselim,
326 IRONGATE1->rsrvd1[0],
327 IRONGATE1->rsrvd1[1],
328 IRONGATE1->io_baselim,
329 IRONGATE1->rsrvd2[0],
330 IRONGATE1->rsrvd2[1],
331 IRONGATE1->interrupt );
332 }
333 #else
334 #define irongate_register_dump(x)
335 #endif
336
337 int
338 irongate_pci_clr_err(void)
339 {
340 unsigned int nmi_ctl=0;
341 unsigned int IRONGATE_jd;
342
343 again:
344 IRONGATE_jd = IRONGATE0->stat_cmd;
345 printk("Iron stat_cmd %x\n", IRONGATE_jd);
346 IRONGATE0->stat_cmd = IRONGATE_jd; /* write again clears error bits */
347 mb();
348 IRONGATE_jd = IRONGATE0->stat_cmd; /* re-read to force write */
349
350 IRONGATE_jd = IRONGATE0->dramms;
351 printk("Iron dramms %x\n", IRONGATE_jd);
352 IRONGATE0->dramms = IRONGATE_jd; /* write again clears error bits */
353 mb();
354 IRONGATE_jd = IRONGATE0->dramms; /* re-read to force write */
355
356 /* Clear ALI NMI */
357 nmi_ctl = inb(0x61);
358 nmi_ctl |= 0x0c;
359 outb(nmi_ctl, 0x61);
360 nmi_ctl &= ~0x0c;
361 outb(nmi_ctl, 0x61);
362
363 IRONGATE_jd = IRONGATE0->dramms;
364 if (IRONGATE_jd & 0x300) goto again;
365
366 return 0;
367 }
368
369 void __init
370 irongate_init_arch(void)
371 {
372 struct pci_controller *hose;
373
374 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
375 irongate_pci_clr_err();
376 irongate_register_dump(__FUNCTION__);
377
378 /*
379 * HACK: set AGP aperture size to 256MB.
380 * This should really be changed during PCI probe, when the
381 * size of the aperture the AGP card wants is known.
382 */
383 printk("irongate_init_arch: AGPVA was 0x%x\n", IRONGATE0->agpva);
384 IRONGATE0->agpva = (IRONGATE0->agpva & ~0x0000000f) | 0x00000007;
385
386 /*
387 * Create our single hose.
388 */
389
390 pci_isa_hose = hose = alloc_pci_controller();
391 hose->io_space = &ioport_resource;
392 hose->mem_space = &iomem_resource;
393 hose->index = 0;
394
395 /* This is for userland consumption. For some reason, the 40-bit
396 PIO bias that we use in the kernel through KSEG didn't work for
397 the page table based user mappings. So make sure we get the
398 43-bit PIO bias. */
399 hose->sparse_mem_base = 0;
400 hose->sparse_io_base = 0;
401 hose->dense_mem_base
402 = (IRONGATE_MEM & 0xffffffffff) | 0x80000000000;
403 hose->dense_io_base
404 = (IRONGATE_IO & 0xffffffffff) | 0x80000000000;
405
406 hose->sg_isa = hose->sg_pci = NULL;
407 __direct_map_base = 0;
408 __direct_map_size = 0xffffffff;
409 }
410
411 /*
412 * IO map and AGP support
413 */
414 #include <linux/vmalloc.h>
415 #include <asm/pgalloc.h>
416
417 static inline void
418 irongate_remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
419 unsigned long phys_addr, unsigned long flags)
420 {
421 unsigned long end;
422
423 address &= ~PMD_MASK;
424 end = address + size;
425 if (end > PMD_SIZE)
426 end = PMD_SIZE;
427 if (address >= end)
428 BUG();
429 do {
430 if (!pte_none(*pte)) {
431 printk("irongate_remap_area_pte: page already exists\n");
432 BUG();
433 }
434 set_pte(pte,
435 mk_pte_phys(phys_addr,
436 __pgprot(_PAGE_VALID | _PAGE_ASM |
437 _PAGE_KRE | _PAGE_KWE | flags)));
438 address += PAGE_SIZE;
439 phys_addr += PAGE_SIZE;
440 pte++;
441 } while (address && (address < end));
442 }
443
444 static inline int
445 irongate_remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size,
446 unsigned long phys_addr, unsigned long flags)
447 {
448 unsigned long end;
449
450 address &= ~PGDIR_MASK;
451 end = address + size;
452 if (end > PGDIR_SIZE)
453 end = PGDIR_SIZE;
454 phys_addr -= address;
455 if (address >= end)
456 BUG();
457 do {
458 pte_t * pte = pte_alloc(&init_mm, pmd, address);
459 if (!pte)
460 return -ENOMEM;
461 irongate_remap_area_pte(pte, address, end - address,
462 address + phys_addr, flags);
463 address = (address + PMD_SIZE) & PMD_MASK;
464 pmd++;
465 } while (address && (address < end));
466 return 0;
467 }
468
469 static int
470 irongate_remap_area_pages(unsigned long address, unsigned long phys_addr,
471 unsigned long size, unsigned long flags)
472 {
473 pgd_t * dir;
474 unsigned long end = address + size;
475
476 phys_addr -= address;
477 dir = pgd_offset(&init_mm, address);
478 flush_cache_all();
479 if (address >= end)
480 BUG();
481 do {
482 pmd_t *pmd;
483 pmd = pmd_alloc(&init_mm, dir, address);
484 if (!pmd)
485 return -ENOMEM;
486 if (irongate_remap_area_pmd(pmd, address, end - address,
487 phys_addr + address, flags))
488 return -ENOMEM;
489 address = (address + PGDIR_SIZE) & PGDIR_MASK;
490 dir++;
491 } while (address && (address < end));
492 return 0;
493 }
494
495 #include <linux/agp_backend.h>
496 #include <linux/agpgart.h>
497
498 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
499 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr))
500
501 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
502 #define GET_GATT(addr) (gatt_pages[GET_PAGE_DIR_IDX(addr)])
503
504 unsigned long
505 irongate_ioremap(unsigned long addr, unsigned long size)
506 {
507 struct vm_struct *area;
508 unsigned long vaddr;
509 unsigned long baddr, last;
510 u32 *mmio_regs, *gatt_pages, *cur_gatt, pte;
511 unsigned long gart_bus_addr, gart_aper_size;
512
513 gart_bus_addr = (unsigned long)IRONGATE0->bar0 &
514 PCI_BASE_ADDRESS_MEM_MASK;
515
516 if (!gart_bus_addr) /* FIXME - there must be a better way!!! */
517 return addr + IRONGATE_MEM;
518
519 gart_aper_size = IRONGATE_DEFAULT_AGP_APER_SIZE; /* FIXME */
520
521 /*
522 * Check for within the AGP aperture...
523 */
524 do {
525 /*
526 * Check the AGP area
527 */
528 if (addr >= gart_bus_addr && addr + size - 1 <
529 gart_bus_addr + gart_aper_size)
530 break;
531
532 /*
533 * Not found - assume legacy ioremap
534 */
535 return addr + IRONGATE_MEM;
536 } while(0);
537
538 mmio_regs = (u32 *)(((unsigned long)IRONGATE0->bar1 &
539 PCI_BASE_ADDRESS_MEM_MASK) + IRONGATE_MEM);
540
541 gatt_pages = (u32 *)(phys_to_virt(mmio_regs[1])); /* FIXME */
542
543 /*
544 * Adjust the limits (mappings must be page aligned)
545 */
546 if (addr & ~PAGE_MASK) {
547 printk("AGP ioremap failed... addr not page aligned (0x%lx)\n",
548 addr);
549 return addr + IRONGATE_MEM;
550 }
551 last = addr + size - 1;
552 size = PAGE_ALIGN(last) - addr;
553
554 #if 0
555 printk("irongate_ioremap(0x%lx, 0x%lx)\n", addr, size);
556 printk("irongate_ioremap: gart_bus_addr 0x%lx\n", gart_bus_addr);
557 printk("irongate_ioremap: gart_aper_size 0x%lx\n", gart_aper_size);
558 printk("irongate_ioremap: mmio_regs %p\n", mmio_regs);
559 printk("irongate_ioremap: gatt_pages %p\n", gatt_pages);
560
561 for(baddr = addr; baddr <= last; baddr += PAGE_SIZE)
562 {
563 cur_gatt = phys_to_virt(GET_GATT(baddr) & ~1);
564 pte = cur_gatt[GET_GATT_OFF(baddr)] & ~1;
565 printk("irongate_ioremap: cur_gatt %p pte 0x%x\n",
566 cur_gatt, pte);
567 }
568 #endif
569
570 /*
571 * Map it
572 */
573 area = get_vm_area(size, VM_IOREMAP);
574 if (!area) return (unsigned long)NULL;
575
576 for(baddr = addr, vaddr = (unsigned long)area->addr;
577 baddr <= last;
578 baddr += PAGE_SIZE, vaddr += PAGE_SIZE)
579 {
580 cur_gatt = phys_to_virt(GET_GATT(baddr) & ~1);
581 pte = cur_gatt[GET_GATT_OFF(baddr)] & ~1;
582
583 if (irongate_remap_area_pages(VMALLOC_VMADDR(vaddr),
584 pte, PAGE_SIZE, 0)) {
585 printk("AGP ioremap: FAILED to map...\n");
586 vfree(area->addr);
587 return (unsigned long)NULL;
588 }
589 }
590
591 flush_tlb_all();
592
593 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
594 #if 0
595 printk("irongate_ioremap(0x%lx, 0x%lx) returning 0x%lx\n",
596 addr, size, vaddr);
597 #endif
598 return vaddr;
599 }
600
601 void
602 irongate_iounmap(unsigned long addr)
603 {
604 if (((long)addr >> 41) == -2)
605 return; /* kseg map, nothing to do */
606 if (addr) return vfree((void *)(PAGE_MASK & addr));
607 }
608