File: /usr/src/linux/arch/sparc/mm/iommu.c
1 /* $Id: iommu.c,v 1.21 2001/02/13 01:16:43 davem Exp $
2 * iommu.c: IOMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995 Pete Zaitcev
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/mm.h>
14 #include <linux/slab.h>
15 #include <asm/scatterlist.h>
16 #include <asm/pgalloc.h>
17 #include <asm/pgtable.h>
18 #include <asm/sbus.h>
19 #include <asm/io.h>
20 #include <asm/mxcc.h>
21 #include <asm/mbus.h>
22
23 /* srmmu.c */
24 extern int viking_mxcc_present;
25 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
26 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
27 extern int flush_page_for_dma_global;
28 static int viking_flush = 0;
29 /* viking.S */
30 extern void viking_flush_page(unsigned long page);
31 extern void viking_mxcc_flush_page(unsigned long page);
32
33 #define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
34 #define MKIOPTE(phys) (((((phys)>>4) & IOPTE_PAGE) | IOPERM) & ~IOPTE_WAZ)
35
36 static inline void iommu_map_dvma_pages_for_iommu(struct iommu_struct *iommu)
37 {
38 unsigned long kern_end = (unsigned long) high_memory;
39 unsigned long first = PAGE_OFFSET;
40 unsigned long last = kern_end;
41 iopte_t *iopte = iommu->page_table;
42
43 iopte += ((first - iommu->start) >> PAGE_SHIFT);
44 while(first <= last) {
45 *iopte++ = __iopte(MKIOPTE(__pa(first)));
46 first += PAGE_SIZE;
47 }
48 }
49
50 void __init
51 iommu_init(int iommund, struct sbus_bus *sbus)
52 {
53 unsigned int impl, vers, ptsize;
54 unsigned long tmp;
55 struct iommu_struct *iommu;
56 struct linux_prom_registers iommu_promregs[PROMREG_MAX];
57 struct resource r;
58 int i;
59
60 iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC);
61 prom_getproperty(iommund, "reg", (void *) iommu_promregs,
62 sizeof(iommu_promregs));
63 memset(&r, 0, sizeof(r));
64 r.flags = iommu_promregs[0].which_io;
65 r.start = iommu_promregs[0].phys_addr;
66 iommu->regs = (struct iommu_regs *)
67 sbus_ioremap(&r, 0, PAGE_SIZE * 3, "iommu_regs");
68 if(!iommu->regs)
69 panic("Cannot map IOMMU registers.");
70 impl = (iommu->regs->control & IOMMU_CTRL_IMPL) >> 28;
71 vers = (iommu->regs->control & IOMMU_CTRL_VERS) >> 24;
72 tmp = iommu->regs->control;
73 tmp &= ~(IOMMU_CTRL_RNGE);
74 switch(PAGE_OFFSET & 0xf0000000) {
75 case 0xf0000000:
76 tmp |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
77 iommu->plow = iommu->start = 0xf0000000;
78 break;
79 case 0xe0000000:
80 tmp |= (IOMMU_RNGE_512MB | IOMMU_CTRL_ENAB);
81 iommu->plow = iommu->start = 0xe0000000;
82 break;
83 case 0xd0000000:
84 case 0xc0000000:
85 tmp |= (IOMMU_RNGE_1GB | IOMMU_CTRL_ENAB);
86 iommu->plow = iommu->start = 0xc0000000;
87 break;
88 case 0xb0000000:
89 case 0xa0000000:
90 case 0x90000000:
91 case 0x80000000:
92 tmp |= (IOMMU_RNGE_2GB | IOMMU_CTRL_ENAB);
93 iommu->plow = iommu->start = 0x80000000;
94 break;
95 }
96 iommu->regs->control = tmp;
97 iommu_invalidate(iommu->regs);
98 iommu->end = 0xffffffff;
99
100 /* Allocate IOMMU page table */
101 ptsize = iommu->end - iommu->start + 1;
102 ptsize = (ptsize >> PAGE_SHIFT) * sizeof(iopte_t);
103
104 /* Stupid alignment constraints give me a headache.
105 We need 256K or 512K or 1M or 2M area aligned to
106 its size and current gfp will fortunately give
107 it to us. */
108 for (i = 6; i < 9; i++)
109 if ((1 << (i + PAGE_SHIFT)) == ptsize)
110 break;
111 tmp = __get_free_pages(GFP_DMA, i);
112 if (!tmp) {
113 prom_printf("Could not allocate iopte of size 0x%08x\n", ptsize);
114 prom_halt();
115 }
116 iommu->lowest = iommu->page_table = (iopte_t *)tmp;
117
118 /* Initialize new table. */
119 flush_cache_all();
120 memset(iommu->page_table, 0, ptsize);
121 iommu_map_dvma_pages_for_iommu(iommu);
122 if(viking_mxcc_present) {
123 unsigned long start = (unsigned long) iommu->page_table;
124 unsigned long end = (start + ptsize);
125 while(start < end) {
126 viking_mxcc_flush_page(start);
127 start += PAGE_SIZE;
128 }
129 } else if (viking_flush) {
130 unsigned long start = (unsigned long) iommu->page_table;
131 unsigned long end = (start + ptsize);
132 while(start < end) {
133 viking_flush_page(start);
134 start += PAGE_SIZE;
135 }
136 }
137 flush_tlb_all();
138 iommu->regs->base = __pa((unsigned long) iommu->page_table) >> 4;
139 iommu_invalidate(iommu->regs);
140
141 sbus->iommu = iommu;
142 printk("IOMMU: impl %d vers %d page table at %p of size %d bytes\n",
143 impl, vers, iommu->page_table, ptsize);
144 }
145
146 static __u32 iommu_get_scsi_one_noflush(char *vaddr, unsigned long len, struct sbus_bus *sbus)
147 {
148 return (__u32)vaddr;
149 }
150
151 static __u32 iommu_get_scsi_one_gflush(char *vaddr, unsigned long len, struct sbus_bus *sbus)
152 {
153 flush_page_for_dma(0);
154 return (__u32)vaddr;
155 }
156
157 static __u32 iommu_get_scsi_one_pflush(char *vaddr, unsigned long len, struct sbus_bus *sbus)
158 {
159 unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
160
161 while(page < ((unsigned long)(vaddr + len))) {
162 flush_page_for_dma(page);
163 page += PAGE_SIZE;
164 }
165 return (__u32)vaddr;
166 }
167
168 static void iommu_get_scsi_sgl_noflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus)
169 {
170 for (; sz >= 0; sz--) {
171 sg[sz].dvma_address = (__u32) (sg[sz].address);
172 sg[sz].dvma_length = (__u32) (sg[sz].length);
173 }
174 }
175
176 static void iommu_get_scsi_sgl_gflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus)
177 {
178 flush_page_for_dma(0);
179 for (; sz >= 0; sz--) {
180 sg[sz].dvma_address = (__u32) (sg[sz].address);
181 sg[sz].dvma_length = (__u32) (sg[sz].length);
182 }
183 }
184
185 static void iommu_get_scsi_sgl_pflush(struct scatterlist *sg, int sz, struct sbus_bus *sbus)
186 {
187 unsigned long page, oldpage = 0;
188
189 while(sz >= 0) {
190 page = ((unsigned long) sg[sz].address) & PAGE_MASK;
191 if (oldpage == page)
192 page += PAGE_SIZE; /* We flushed that page already */
193 while(page < (unsigned long)(sg[sz].address + sg[sz].length)) {
194 flush_page_for_dma(page);
195 page += PAGE_SIZE;
196 }
197 sg[sz].dvma_address = (__u32) (sg[sz].address);
198 sg[sz].dvma_length = (__u32) (sg[sz].length);
199 sz--;
200 oldpage = page - PAGE_SIZE;
201 }
202 }
203
204 static void iommu_release_scsi_one(__u32 vaddr, unsigned long len, struct sbus_bus *sbus)
205 {
206 }
207
208 static void iommu_release_scsi_sgl(struct scatterlist *sg, int sz, struct sbus_bus *sbus)
209 {
210 }
211
212 #ifdef CONFIG_SBUS
213 static void iommu_map_dma_area(unsigned long va, __u32 addr, int len)
214 {
215 unsigned long page, end, ipte_cache;
216 pgprot_t dvma_prot;
217 struct iommu_struct *iommu = sbus_root->iommu;
218 iopte_t *iopte = iommu->page_table;
219 iopte_t *first;
220
221 if(viking_mxcc_present || srmmu_modtype == HyperSparc) {
222 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
223 ipte_cache = 1;
224 } else {
225 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
226 ipte_cache = 0;
227 }
228
229 iopte += ((addr - iommu->start) >> PAGE_SHIFT);
230 first = iopte;
231 end = PAGE_ALIGN((addr + len));
232 while(addr < end) {
233 page = va;
234 {
235 pgd_t *pgdp;
236 pmd_t *pmdp;
237 pte_t *ptep;
238
239 if (viking_mxcc_present)
240 viking_mxcc_flush_page(page);
241 else if (viking_flush)
242 viking_flush_page(page);
243 else
244 __flush_page_to_ram(page);
245
246 pgdp = pgd_offset(&init_mm, addr);
247 pmdp = pmd_offset(pgdp, addr);
248 ptep = pte_offset(pmdp, addr);
249
250 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
251 if (ipte_cache != 0) {
252 iopte_val(*iopte++) = MKIOPTE(__pa(page));
253 } else {
254 iopte_val(*iopte++) =
255 MKIOPTE(__pa(page)) & ~IOPTE_CACHE;
256 }
257 }
258 addr += PAGE_SIZE;
259 va += PAGE_SIZE;
260 }
261 /* P3: why do we need this?
262 *
263 * DAVEM: Because there are several aspects, none of which
264 * are handled by a single interface. Some cpus are
265 * completely not I/O DMA coherent, and some have
266 * virtually indexed caches. The driver DMA flushing
267 * methods handle the former case, but here during
268 * IOMMU page table modifications, and usage of non-cacheable
269 * cpu mappings of pages potentially in the cpu caches, we have
270 * to handle the latter case as well.
271 */
272 flush_cache_all();
273 if(viking_mxcc_present) {
274 unsigned long start = ((unsigned long) first) & PAGE_MASK;
275 unsigned long end = PAGE_ALIGN(((unsigned long) iopte));
276 while(start < end) {
277 viking_mxcc_flush_page(start);
278 start += PAGE_SIZE;
279 }
280 } else if(viking_flush) {
281 unsigned long start = ((unsigned long) first) & PAGE_MASK;
282 unsigned long end = PAGE_ALIGN(((unsigned long) iopte));
283 while(start < end) {
284 viking_flush_page(start);
285 start += PAGE_SIZE;
286 }
287 }
288 flush_tlb_all();
289 iommu_invalidate(iommu->regs);
290 }
291
292 static void iommu_unmap_dma_area(unsigned long busa, int len)
293 {
294 struct iommu_struct *iommu = sbus_root->iommu;
295 iopte_t *iopte = iommu->page_table;
296 unsigned long end;
297
298 iopte += ((busa - iommu->start) >> PAGE_SHIFT);
299 end = PAGE_ALIGN((busa + len));
300 while (busa < end) {
301 iopte_val(*iopte++) = 0;
302 busa += PAGE_SIZE;
303 }
304 flush_tlb_all(); /* P3: Hmm... it would not hurt. */
305 iommu_invalidate(iommu->regs);
306 }
307
308 static unsigned long iommu_translate_dvma(unsigned long busa)
309 {
310 struct iommu_struct *iommu = sbus_root->iommu;
311 iopte_t *iopte = iommu->page_table;
312 unsigned long pa;
313
314 iopte += ((busa - iommu->start) >> PAGE_SHIFT);
315 pa = pte_val(*iopte);
316 pa = (pa & 0xFFFFFFF0) << 4; /* Loose higher bits of 36 */
317 return pa + PAGE_OFFSET;
318 }
319 #endif
320
321 static char *iommu_lockarea(char *vaddr, unsigned long len)
322 {
323 return vaddr;
324 }
325
326 static void iommu_unlockarea(char *vaddr, unsigned long len)
327 {
328 }
329
330 void __init ld_mmu_iommu(void)
331 {
332 viking_flush = (BTFIXUPVAL_CALL(flush_page_for_dma) == (unsigned long)viking_flush_page);
333 BTFIXUPSET_CALL(mmu_lockarea, iommu_lockarea, BTFIXUPCALL_RETO0);
334 BTFIXUPSET_CALL(mmu_unlockarea, iommu_unlockarea, BTFIXUPCALL_NOP);
335
336 if (!BTFIXUPVAL_CALL(flush_page_for_dma)) {
337 /* IO coherent chip */
338 BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_noflush, BTFIXUPCALL_RETO0);
339 BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_noflush, BTFIXUPCALL_NORM);
340 } else if (flush_page_for_dma_global) {
341 /* flush_page_for_dma flushes everything, no matter of what page is it */
342 BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_gflush, BTFIXUPCALL_NORM);
343 BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_gflush, BTFIXUPCALL_NORM);
344 } else {
345 BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_pflush, BTFIXUPCALL_NORM);
346 BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_pflush, BTFIXUPCALL_NORM);
347 }
348 BTFIXUPSET_CALL(mmu_release_scsi_one, iommu_release_scsi_one, BTFIXUPCALL_NOP);
349 BTFIXUPSET_CALL(mmu_release_scsi_sgl, iommu_release_scsi_sgl, BTFIXUPCALL_NOP);
350
351 #ifdef CONFIG_SBUS
352 BTFIXUPSET_CALL(mmu_map_dma_area, iommu_map_dma_area, BTFIXUPCALL_NORM);
353 BTFIXUPSET_CALL(mmu_unmap_dma_area, iommu_unmap_dma_area, BTFIXUPCALL_NORM);
354 BTFIXUPSET_CALL(mmu_translate_dvma, iommu_translate_dvma, BTFIXUPCALL_NORM);
355 #endif
356 }
357