File: /usr/src/linux/arch/alpha/kernel/core_mcpcia.c
1 /*
2 * linux/arch/alpha/kernel/core_mcpcia.c
3 *
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
5 *
6 * Code common to all MCbus-PCI Adaptor core logic chipsets
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/sched.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15
16 #include <asm/ptrace.h>
17 #include <asm/system.h>
18 #include <asm/hwrpb.h>
19
20 #define __EXTERN_INLINE inline
21 #include <asm/io.h>
22 #include <asm/core_mcpcia.h>
23 #undef __EXTERN_INLINE
24
25 #include "proto.h"
26 #include "pci_impl.h"
27
28 /*
29 * NOTE: Herein lie back-to-back mb instructions. They are magic.
30 * One plausible explanation is that the i/o controller does not properly
31 * handle the system transaction. Another involves timing. Ho hum.
32 */
33
34 /*
35 * BIOS32-style PCI interface:
36 */
37
38 #define DEBUG_CFG 0
39
40 #if DEBUG_CFG
41 # define DBG_CFG(args) printk args
42 #else
43 # define DBG_CFG(args)
44 #endif
45
46 #define MCPCIA_MAX_HOSES 4
47
48 /*
49 * Given a bus, device, and function number, compute resulting
50 * configuration space address and setup the MCPCIA_HAXR2 register
51 * accordingly. It is therefore not safe to have concurrent
52 * invocations to configuration space access routines, but there
53 * really shouldn't be any need for this.
54 *
55 * Type 0:
56 *
57 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
58 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
59 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
61 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
62 *
63 * 31:11 Device select bit.
64 * 10:8 Function number
65 * 7:2 Register number
66 *
67 * Type 1:
68 *
69 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
70 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
71 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
73 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
74 *
75 * 31:24 reserved
76 * 23:16 bus number (8 bits = 128 possible buses)
77 * 15:11 Device number (5 bits)
78 * 10:8 function number
79 * 7:2 register number
80 *
81 * Notes:
82 * The function number selects which function of a multi-function device
83 * (e.g., SCSI and Ethernet).
84 *
85 * The register selects a DWORD (32 bit) register offset. Hence it
86 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
87 * bits.
88 */
89
90 static unsigned int
91 conf_read(unsigned long addr, unsigned char type1,
92 struct pci_controller *hose)
93 {
94 unsigned long flags;
95 unsigned long mid = MCPCIA_HOSE2MID(hose->index);
96 unsigned int stat0, value, temp, cpu;
97
98 cpu = smp_processor_id();
99
100 __save_and_cli(flags);
101
102 DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",
103 addr, type1, mid));
104
105 /* Reset status register to avoid losing errors. */
106 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
107 *(vuip)MCPCIA_CAP_ERR(mid) = stat0;
108 mb();
109 temp = *(vuip)MCPCIA_CAP_ERR(mid);
110 DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));
111
112 mb();
113 draina();
114 mcheck_expected(cpu) = 1;
115 mcheck_taken(cpu) = 0;
116 mcheck_extra(cpu) = mid;
117 mb();
118
119 /* Access configuration space. */
120 value = *((vuip)addr);
121 mb();
122 mb(); /* magic */
123
124 if (mcheck_taken(cpu)) {
125 mcheck_taken(cpu) = 0;
126 value = 0xffffffffU;
127 mb();
128 }
129 mcheck_expected(cpu) = 0;
130 mb();
131
132 DBG_CFG(("conf_read(): finished\n"));
133
134 __restore_flags(flags);
135 return value;
136 }
137
138 static void
139 conf_write(unsigned long addr, unsigned int value, unsigned char type1,
140 struct pci_controller *hose)
141 {
142 unsigned long flags;
143 unsigned long mid = MCPCIA_HOSE2MID(hose->index);
144 unsigned int stat0, temp, cpu;
145
146 cpu = smp_processor_id();
147
148 __save_and_cli(flags); /* avoid getting hit by machine check */
149
150 /* Reset status register to avoid losing errors. */
151 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
152 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();
153 temp = *(vuip)MCPCIA_CAP_ERR(mid);
154 DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));
155
156 draina();
157 mcheck_expected(cpu) = 1;
158 mcheck_extra(cpu) = mid;
159 mb();
160
161 /* Access configuration space. */
162 *((vuip)addr) = value;
163 mb();
164 mb(); /* magic */
165 temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
166 mcheck_expected(cpu) = 0;
167 mb();
168
169 DBG_CFG(("conf_write(): finished\n"));
170 __restore_flags(flags);
171 }
172
173 static int
174 mk_conf_addr(struct pci_dev *dev, int where, struct pci_controller *hose,
175 unsigned long *pci_addr, unsigned char *type1)
176 {
177 u8 bus = dev->bus->number;
178 u8 devfn = dev->devfn;
179 unsigned long addr;
180
181 DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"
182 " pci_addr=0x%p, type1=0x%p)\n",
183 bus, devfn, hose->index, where, pci_addr, type1));
184
185 /* Type 1 configuration cycle for *ALL* busses. */
186 *type1 = 1;
187
188 if (dev->bus->number == hose->first_busno)
189 bus = 0;
190 addr = (bus << 16) | (devfn << 8) | (where);
191 addr <<= 5; /* swizzle for SPARSE */
192 addr |= hose->config_space_base;
193
194 *pci_addr = addr;
195 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
196 return 0;
197 }
198
199 static int
200 mcpcia_read_config_byte(struct pci_dev *dev, int where, u8 *value)
201 {
202 struct pci_controller *hose = dev->sysdata;
203 unsigned long addr, w;
204 unsigned char type1;
205
206 if (mk_conf_addr(dev, where, hose, &addr, &type1))
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
209 addr |= 0x00;
210 w = conf_read(addr, type1, hose);
211 *value = __kernel_extbl(w, where & 3);
212 return PCIBIOS_SUCCESSFUL;
213 }
214
215 static int
216 mcpcia_read_config_word(struct pci_dev *dev, int where, u16 *value)
217 {
218 struct pci_controller *hose = dev->sysdata;
219 unsigned long addr, w;
220 unsigned char type1;
221
222 if (mk_conf_addr(dev, where, hose, &addr, &type1))
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 addr |= 0x08;
226 w = conf_read(addr, type1, hose);
227 *value = __kernel_extwl(w, where & 3);
228 return PCIBIOS_SUCCESSFUL;
229 }
230
231 static int
232 mcpcia_read_config_dword(struct pci_dev *dev, int where, u32 *value)
233 {
234 struct pci_controller *hose = dev->sysdata;
235 unsigned long addr;
236 unsigned char type1;
237
238 if (mk_conf_addr(dev, where, hose, &addr, &type1))
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 addr |= 0x18;
242 *value = conf_read(addr, type1, hose);
243 return PCIBIOS_SUCCESSFUL;
244 }
245
246 static int
247 mcpcia_write_config(struct pci_dev *dev, int where, u32 value, long mask)
248 {
249 struct pci_controller *hose = dev->sysdata;
250 unsigned long addr;
251 unsigned char type1;
252
253 if (mk_conf_addr(dev, where, hose, &addr, &type1))
254 return PCIBIOS_DEVICE_NOT_FOUND;
255
256 addr |= mask;
257 value = __kernel_insql(value, where & 3);
258 conf_write(addr, value, type1, hose);
259 return PCIBIOS_SUCCESSFUL;
260 }
261
262 static int
263 mcpcia_write_config_byte(struct pci_dev *dev, int where, u8 value)
264 {
265 return mcpcia_write_config(dev, where, value, 0x00);
266 }
267
268 static int
269 mcpcia_write_config_word(struct pci_dev *dev, int where, u16 value)
270 {
271 return mcpcia_write_config(dev, where, value, 0x08);
272 }
273
274 static int
275 mcpcia_write_config_dword(struct pci_dev *dev, int where, u32 value)
276 {
277 return mcpcia_write_config(dev, where, value, 0x18);
278 }
279
280 struct pci_ops mcpcia_pci_ops =
281 {
282 read_byte: mcpcia_read_config_byte,
283 read_word: mcpcia_read_config_word,
284 read_dword: mcpcia_read_config_dword,
285 write_byte: mcpcia_write_config_byte,
286 write_word: mcpcia_write_config_word,
287 write_dword: mcpcia_write_config_dword
288 };
289
290 void
291 mcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
292 {
293 wmb();
294 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;
295 mb();
296 }
297
298 static int __init
299 mcpcia_probe_hose(int h)
300 {
301 int cpu = smp_processor_id();
302 int mid = MCPCIA_HOSE2MID(h);
303 unsigned int pci_rev;
304
305 /* Gotta be REAL careful. If hose is absent, we get an mcheck. */
306
307 mb();
308 mb();
309 draina();
310 wrmces(7);
311
312 mcheck_expected(cpu) = 2; /* indicates probing */
313 mcheck_taken(cpu) = 0;
314 mcheck_extra(cpu) = mid;
315 mb();
316
317 /* Access the bus revision word. */
318 pci_rev = *(vuip)MCPCIA_REV(mid);
319
320 mb();
321 mb(); /* magic */
322 if (mcheck_taken(cpu)) {
323 mcheck_taken(cpu) = 0;
324 pci_rev = 0xffffffff;
325 mb();
326 }
327 mcheck_expected(cpu) = 0;
328 mb();
329
330 return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;
331 }
332
333 static void __init
334 mcpcia_new_hose(int h)
335 {
336 struct pci_controller *hose;
337 struct resource *io, *mem, *hae_mem;
338 int mid = MCPCIA_HOSE2MID(h);
339
340 hose = alloc_pci_controller();
341 if (h == 0)
342 pci_isa_hose = hose;
343 io = alloc_resource();
344 mem = alloc_resource();
345 hae_mem = alloc_resource();
346
347 hose->io_space = io;
348 hose->mem_space = hae_mem;
349 hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR;
350 hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR;
351 hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR;
352 hose->dense_io_base = 0;
353 hose->config_space_base = MCPCIA_CONF(mid);
354 hose->index = h;
355
356 io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS;
357 io->end = io->start + 0xffff;
358 io->name = pci_io_names[h];
359 io->flags = IORESOURCE_IO;
360
361 mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS;
362 mem->end = mem->start + 0xffffffff;
363 mem->name = pci_mem_names[h];
364 mem->flags = IORESOURCE_MEM;
365
366 hae_mem->start = mem->start;
367 hae_mem->end = mem->start + MCPCIA_MEM_MASK;
368 hae_mem->name = pci_hae0_name;
369 hae_mem->flags = IORESOURCE_MEM;
370
371 if (request_resource(&ioport_resource, io) < 0)
372 printk(KERN_ERR "Failed to request IO on hose %d\n", h);
373 if (request_resource(&iomem_resource, mem) < 0)
374 printk(KERN_ERR "Failed to request MEM on hose %d\n", h);
375 if (request_resource(mem, hae_mem) < 0)
376 printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h);
377 }
378
379 static void
380 mcpcia_pci_clr_err(int mid)
381 {
382 *(vuip)MCPCIA_CAP_ERR(mid);
383 *(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */
384 mb();
385 *(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */
386 }
387
388 static void __init
389 mcpcia_startup_hose(struct pci_controller *hose)
390 {
391 int mid = MCPCIA_HOSE2MID(hose->index);
392 unsigned int tmp;
393
394 mcpcia_pci_clr_err(mid);
395
396 /*
397 * Set up error reporting.
398 */
399 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
400 tmp |= 0x0006; /* master/target abort */
401 *(vuip)MCPCIA_CAP_ERR(mid) = tmp;
402 mb();
403 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
404
405 /*
406 * Set up the PCI->physical memory translation windows.
407 *
408 * Window 0 is scatter-gather 8MB at 8MB (for isa)
409 * Window 1 is scatter-gather 128MB at 1GB
410 * Window 2 is direct access 2GB at 2GB
411 * ??? We ought to scale window 1 with memory.
412 */
413 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
414 hose->sg_pci = iommu_arena_new(hose, 0x40000000, 0x08000000, 0);
415
416 __direct_map_base = 0x80000000;
417 __direct_map_size = 0x80000000;
418
419 *(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3;
420 *(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000;
421 *(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8;
422
423 *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3;
424 *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000;
425 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8;
426
427 *(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1;
428 *(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000;
429 *(vuip)MCPCIA_T2_BASE(mid) = 0;
430
431 *(vuip)MCPCIA_W3_BASE(mid) = 0x0;
432
433 mcpcia_pci_tbi(hose, 0, -1);
434
435 *(vuip)MCPCIA_HBASE(mid) = 0x0;
436 mb();
437
438 *(vuip)MCPCIA_HAE_MEM(mid) = 0U;
439 mb();
440 *(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */
441 *(vuip)MCPCIA_HAE_IO(mid) = 0;
442 mb();
443 *(vuip)MCPCIA_HAE_IO(mid); /* read it back. */
444 }
445
446 void __init
447 mcpcia_init_arch(void)
448 {
449 /* With multiple PCI busses, we play with I/O as physical addrs. */
450 ioport_resource.end = ~0UL;
451 iomem_resource.end = ~0UL;
452
453 /* Allocate hose 0. That's the one that all the ISA junk hangs
454 off of, from which we'll be registering stuff here in a bit.
455 Other hose detection is done in mcpcia_init_hoses, which is
456 called from init_IRQ. */
457
458 mcpcia_new_hose(0);
459 }
460
461 /* This is called from init_IRQ, since we cannot take interrupts
462 before then. Which means we cannot do this in init_arch. */
463
464 void __init
465 mcpcia_init_hoses(void)
466 {
467 struct pci_controller *hose;
468 int hose_count;
469 int h;
470
471 /* First, find how many hoses we have. */
472 hose_count = 0;
473 for (h = 0; h < MCPCIA_MAX_HOSES; ++h) {
474 if (mcpcia_probe_hose(h)) {
475 if (h != 0)
476 mcpcia_new_hose(h);
477 hose_count++;
478 }
479 }
480
481 printk("mcpcia_init_hoses: found %d hoses\n", hose_count);
482
483 /* Now do init for each hose. */
484 for (hose = hose_head; hose; hose = hose->next)
485 mcpcia_startup_hose(hose);
486 }
487
488 static void
489 mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout)
490 {
491 struct el_common_EV5_uncorrectable_mcheck *frame;
492 int i;
493
494 frame = &logout->procdata;
495
496 /* Print PAL fields */
497 for (i = 0; i < 24; i += 2) {
498 printk(" paltmp[%d-%d] = %16lx %16lx\n",
499 i, i+1, frame->paltemp[i], frame->paltemp[i+1]);
500 }
501 for (i = 0; i < 8; i += 2) {
502 printk(" shadow[%d-%d] = %16lx %16lx\n",
503 i, i+1, frame->shadow[i],
504 frame->shadow[i+1]);
505 }
506 printk(" Addr of excepting instruction = %16lx\n",
507 frame->exc_addr);
508 printk(" Summary of arithmetic traps = %16lx\n",
509 frame->exc_sum);
510 printk(" Exception mask = %16lx\n",
511 frame->exc_mask);
512 printk(" Base address for PALcode = %16lx\n",
513 frame->pal_base);
514 printk(" Interrupt Status Reg = %16lx\n",
515 frame->isr);
516 printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n",
517 frame->icsr);
518 printk(" I-CACHE Reg %s parity error = %16lx\n",
519 (frame->ic_perr_stat & 0x800L) ?
520 "Data" : "Tag",
521 frame->ic_perr_stat);
522 printk(" D-CACHE error Reg = %16lx\n",
523 frame->dc_perr_stat);
524 if (frame->dc_perr_stat & 0x2) {
525 switch (frame->dc_perr_stat & 0x03c) {
526 case 8:
527 printk(" Data error in bank 1\n");
528 break;
529 case 4:
530 printk(" Data error in bank 0\n");
531 break;
532 case 20:
533 printk(" Tag error in bank 1\n");
534 break;
535 case 10:
536 printk(" Tag error in bank 0\n");
537 break;
538 }
539 }
540 printk(" Effective VA = %16lx\n",
541 frame->va);
542 printk(" Reason for D-stream = %16lx\n",
543 frame->mm_stat);
544 printk(" EV5 SCache address = %16lx\n",
545 frame->sc_addr);
546 printk(" EV5 SCache TAG/Data parity = %16lx\n",
547 frame->sc_stat);
548 printk(" EV5 BC_TAG_ADDR = %16lx\n",
549 frame->bc_tag_addr);
550 printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",
551 frame->ei_addr);
552 printk(" Fill Syndrome = %16lx\n",
553 frame->fill_syndrome);
554 printk(" EI_STAT reg = %16lx\n",
555 frame->ei_stat);
556 printk(" LD_LOCK = %16lx\n",
557 frame->ld_lock);
558 }
559
560 static void
561 mcpcia_print_system_area(unsigned long la_ptr)
562 {
563 struct el_common *frame;
564 struct pci_controller *hose;
565
566 struct IOD_subpacket {
567 unsigned long base;
568 unsigned int whoami;
569 unsigned int rsvd1;
570 unsigned int pci_rev;
571 unsigned int cap_ctrl;
572 unsigned int hae_mem;
573 unsigned int hae_io;
574 unsigned int int_ctl;
575 unsigned int int_reg;
576 unsigned int int_mask0;
577 unsigned int int_mask1;
578 unsigned int mc_err0;
579 unsigned int mc_err1;
580 unsigned int cap_err;
581 unsigned int rsvd2;
582 unsigned int pci_err1;
583 unsigned int mdpa_stat;
584 unsigned int mdpa_syn;
585 unsigned int mdpb_stat;
586 unsigned int mdpb_syn;
587 unsigned int rsvd3;
588 unsigned int rsvd4;
589 unsigned int rsvd5;
590 } *iodpp;
591
592 frame = (struct el_common *)la_ptr;
593 iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset);
594
595 for (hose = hose_head; hose; hose = hose->next, iodpp++) {
596
597 printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n",
598 hose->index, iodpp->base);
599 printk(" WHOAMI = %8x\n", iodpp->whoami);
600 printk(" PCI_REV = %8x\n", iodpp->pci_rev);
601 printk(" CAP_CTRL = %8x\n", iodpp->cap_ctrl);
602 printk(" HAE_MEM = %8x\n", iodpp->hae_mem);
603 printk(" HAE_IO = %8x\n", iodpp->hae_io);
604 printk(" INT_CTL = %8x\n", iodpp->int_ctl);
605 printk(" INT_REG = %8x\n", iodpp->int_reg);
606 printk(" INT_MASK0 = %8x\n", iodpp->int_mask0);
607 printk(" INT_MASK1 = %8x\n", iodpp->int_mask1);
608 printk(" MC_ERR0 = %8x\n", iodpp->mc_err0);
609 printk(" MC_ERR1 = %8x\n", iodpp->mc_err1);
610 printk(" CAP_ERR = %8x\n", iodpp->cap_err);
611 printk(" PCI_ERR1 = %8x\n", iodpp->pci_err1);
612 printk(" MDPA_STAT = %8x\n", iodpp->mdpa_stat);
613 printk(" MDPA_SYN = %8x\n", iodpp->mdpa_syn);
614 printk(" MDPB_STAT = %8x\n", iodpp->mdpb_stat);
615 printk(" MDPB_SYN = %8x\n", iodpp->mdpb_syn);
616 }
617 }
618
619 void
620 mcpcia_machine_check(unsigned long vector, unsigned long la_ptr,
621 struct pt_regs * regs)
622 {
623 struct el_common *mchk_header;
624 struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout;
625 unsigned int cpu = smp_processor_id();
626 int expected;
627
628 mchk_header = (struct el_common *)la_ptr;
629 mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr;
630 expected = mcheck_expected(cpu);
631
632 mb();
633 mb(); /* magic */
634 draina();
635
636 switch (expected) {
637 case 0:
638 {
639 /* FIXME: how do we figure out which hose the
640 error was on? */
641 struct pci_controller *hose;
642 for (hose = hose_head; hose; hose = hose->next)
643 mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index));
644 break;
645 }
646 case 1:
647 mcpcia_pci_clr_err(mcheck_extra(cpu));
648 break;
649 default:
650 /* Otherwise, we're being called from mcpcia_probe_hose
651 and there's no hose clear an error from. */
652 break;
653 }
654
655 wrmces(0x7);
656 mb();
657
658 process_mcheck_info(vector, la_ptr, regs, "MCPCIA", expected != 0);
659 if (!expected && vector != 0x620 && vector != 0x630) {
660 mcpcia_print_uncorrectable(mchk_logout);
661 mcpcia_print_system_area(la_ptr);
662 }
663 }
664