File: /usr/src/linux/include/asm-sparc64/chmctrl.h
1 /* $Id: chmctrl.h,v 1.1 2001/03/29 11:43:28 davem Exp $ */
2 #ifndef _SPARC64_CHMCTRL_H
3 #define _SPARC64_CHMCTRL_H
4
5 /* Cheetah memory controller programmable registers. */
6 #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
7 #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
8 #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
9 #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
10 #define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
11 #define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
12 #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
13 #define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
14 #define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
15
16 /* Memory Timing Control I */
17 #define TCTRL1_SDRAMCTL_DLY 0xf000000000000000
18 #define TCTRL1_SDRAMCTL_DLY_SHIFT 60
19 #define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000
20 #define TCTRL1_SDRAMCLK_DLY_SHIFT 57
21 #define TCTRL1_R 0x0100000000000000
22 #define TCTRL1_R_SHIFT 56
23 #define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000
24 #define TCTRL1_AUTORFR_CYCLE_SHIFT 49
25 #define TCTRL1_RD_WAIT 0x0001f00000000000
26 #define TCTRL1_RD_WAIT_SHIFT 44
27 #define TCTRL1_PC_CYCLE 0x00000fc000000000
28 #define TCTRL1_PC_CYCLE_SHIFT 38
29 #define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000
30 #define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
31 #define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000
32 #define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
33 #define TCTRL1_ACT_WR_DLY 0x0000000003f00000
34 #define TCTRL1_ACT_WR_DLY_SHIFT 20
35 #define TCTRL1_ACT_RD_DLY 0x00000000000fc000
36 #define TCTRL1_ACT_RD_DLY_SHIFT 14
37 #define TCTRL1_BANK_PRESENT 0x0000000000003000
38 #define TCTRL1_BANK_PRESENT_SHIFT 12
39 #define TCTRL1_RFR_INT 0x0000000000000ff8
40 #define TCTRL1_RFR_INT_SHIFT 3
41 #define TCTRL1_SET_MODE_REG 0x0000000000000004
42 #define TCTRL1_SET_MODE_REG_SHIFT 2
43 #define TCTRL1_RFR_ENABLE 0x0000000000000002
44 #define TCTRL1_RFR_ENABLE_SHIFT 1
45 #define TCTRL1_PRECHG_ALL 0x0000000000000001
46 #define TCTRL1_PRECHG_ALL_SHIFT 0
47
48 /* Memory Timing Control II */
49 #define TCTRL2_WR_MSEL_DLY 0xfc00000000000000
50 #define TCTRL2_WR_MSEL_DLY_SHIFT 58
51 #define TCTRL2_RD_MSEL_DLY 0x03f0000000000000
52 #define TCTRL2_RD_MSEL_DLY_SHIFT 52
53 #define TCTRL2_WRDATA_THLD 0x000c000000000000
54 #define TCTRL2_WRDATA_THLD_SHIFT 50
55 #define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000
56 #define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
57 #define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000
58 #define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
59 #define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000
60 #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
61 #define TCTRL2_RDWR_1_DLY 0x0000003f00000000
62 #define TCTRL2_RDWR_1_DLY_SHIFT 32
63 #define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000
64 #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
65 #define TCTRL2_WRWR_1_DLY 0x0000000007e00000
66 #define TCTRL2_WRWR_1_DLY_SHIFT 21
67 #define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000
68 #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
69 #define TCTRL2_R 0x0000000000008000
70 #define TCTRL2_R_SHIFT 15
71 #define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fff
72 #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
73
74 /* Memory Timing Control III */
75 #define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000
76 #define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
77 #define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000
78 #define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
79 #define TCTRL3_R 0x0100000000000000
80 #define TCTRL3_R_SHIFT 56
81 #define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000
82 #define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
83 #define TCTRL3_RD_WAIT 0x0001f00000000000
84 #define TCTRL3_RD_WAIT_SHIFT 44
85 #define TCTRL3_PC_CYCLE 0x00000fc000000000
86 #define TCTRL3_PC_CYCLE_SHIFT 38
87 #define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000
88 #define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
89 #define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000
90 #define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
91 #define TCTRL3_ACT_WR_DLY 0x0000000003f00000
92 #define TCTRL3_ACT_WR_DLY_SHIFT 20
93 #define TCTRL3_ACT_RD_DLY 0x00000000000fc000
94 #define TCTRL3_ACT_RD_DLY_SHIFT 14
95 #define TCTRL3_BANK_PRESENT 0x0000000000003000
96 #define TCTRL3_BANK_PRESENT_SHIFT 12
97 #define TCTRL3_RFR_INT 0x0000000000000ff8
98 #define TCTRL3_RFR_INT_SHIFT 3
99 #define TCTRL3_SET_MODE_REG 0x0000000000000004
100 #define TCTRL3_SET_MODE_REG_SHIFT 2
101 #define TCTRL3_RFR_ENABLE 0x0000000000000002
102 #define TCTRL3_RFR_ENABLE_SHIFT 1
103 #define TCTRL3_PRECHG_ALL 0x0000000000000001
104 #define TCTRL3_PRECHG_ALL_SHIFT 0
105
106 /* Memory Timing Control IV */
107 #define TCTRL4_WR_MSEL_DLY 0xfc00000000000000
108 #define TCTRL4_WR_MSEL_DLY_SHIFT 58
109 #define TCTRL4_RD_MSEL_DLY 0x03f0000000000000
110 #define TCTRL4_RD_MSEL_DLY_SHIFT 52
111 #define TCTRL4_WRDATA_THLD 0x000c000000000000
112 #define TCTRL4_WRDATA_THLD_SHIFT 50
113 #define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000
114 #define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
115 #define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000
116 #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
117 #define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000
118 #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
119 #define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000
120 #define TCTRL4_RD_WR_TI_DLY_SHIFT 32
121 #define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000
122 #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
123 #define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000
124 #define TCTRL4_WR_WR_TI_DLY_SHIFT 21
125 #define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f0000
126 #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
127 #define TCTRL4_R 0x0000000000008000
128 #define TCTRL4_R_SHIFT 15
129 #define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fff
130 #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
131
132 /* All 4 memory address decoding registers have the
133 * same layout.
134 */
135 #define MEM_DECODE_VALID 0x8000000000000000 /* Valid */
136 #define MEM_DECODE_VALID_SHIFT 63
137 #define MEM_DECODE_UK 0x001ffe0000000000 /* Upper mask */
138 #define MEM_DECODE_UK_SHIFT 41
139 #define MEM_DECODE_UM 0x0000001ffff00000 /* Upper match */
140 #define MEM_DECODE_UM_SHIFT 20
141 #define MEM_DECODE_LK 0x000000000003c000 /* Lower mask */
142 #define MEM_DECODE_LK_SHIFT 14
143 #define MEM_DECODE_LM 0x0000000000000f00 /* Lower match */
144 #define MEM_DECODE_LM_SHIFT 8
145
146 #define PA_UPPER_BITS 0x000007fffc000000
147 #define PA_UPPER_BITS_SHIFT 26
148 #define PA_LOWER_BITS 0x00000000000003c0
149 #define PA_LOWER_BITS_SHIFT 6
150
151 #define MACTRL_R0 0x8000000000000000
152 #define MACTRL_R0_SHIFT 63
153 #define MACTRL_ADDR_LE_PW 0x7000000000000000
154 #define MACTRL_ADDR_LE_PW_SHIFT 60
155 #define MACTRL_CMD_PW 0x0f00000000000000
156 #define MACTRL_CMD_PW_SHIFT 56
157 #define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000
158 #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
159 #define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000
160 #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
161 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000
162 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
163 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000
164 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
165 #define MACTRL_R1 0x0000001000000000
166 #define MACTRL_R1_SHIFT 36
167 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000
168 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
169 #define MACTRL_ENC_INTLV_B3 0x00000000f8000000
170 #define MACTRL_ENC_INTLV_B3_SHIFT 27
171 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000
172 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
173 #define MACTRL_ENC_INTLV_B2 0x00000000007c0000
174 #define MACTRL_ENC_INTLV_B2_SHIFT 18
175 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000
176 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
177 #define MACTRL_ENC_INTLV_B1 0x0000000000003e00
178 #define MACTRL_ENC_INTLV_B1_SHIFT 9
179 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0
180 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
181 #define MACTRL_ENC_INTLV_B0 0x000000000000001f
182 #define MACTRL_ENC_INTLV_B0_SHIFT 0
183
184 #endif /* _SPARC64_CHMCTRL_H */
185