File: /usr/src/linux/include/asm-alpha/core_t2.h
1 #ifndef __ALPHA_T2__H__
2 #define __ALPHA_T2__H__
3
4 #include <linux/config.h>
5 #include <linux/types.h>
6 #include <asm/compiler.h>
7
8
9 /*
10 * T2 is the internal name for the core logic chipset which provides
11 * memory controller and PCI access for the SABLE-based systems.
12 *
13 * This file is based on:
14 *
15 * SABLE I/O Specification
16 * Revision/Update Information: 1.3
17 *
18 * jestabro@amt.tay1.dec.com Initial Version.
19 *
20 */
21
22 #define T2_MEM_R1_MASK 0x03ffffff /* Mem sparse region 1 mask is 26 bits */
23
24 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
25 #define _GAMMA_BIAS 0x8000000000UL
26
27 #if defined(CONFIG_ALPHA_GENERIC)
28 #define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias
29 #elif defined(CONFIG_ALPHA_GAMMA)
30 #define GAMMA_BIAS _GAMMA_BIAS
31 #else
32 #define GAMMA_BIAS 0
33 #endif
34
35 /*
36 * Memory spaces:
37 */
38 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
39 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
40 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
41 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
42
43 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
44 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
45 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
46 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
47 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
48 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
49 #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
50 #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
51 #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
52 #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
53 #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
54 #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
55 #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
56 #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
57 #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
58 #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
59 #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
60
61 #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
62 #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
63
64 #define T2_HAE_ADDRESS T2_HAE_1
65
66 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
67 3.8fff.ffff
68 *
69 * +--------------+ 3 8000 0000
70 * | CPU 0 CSRs |
71 * +--------------+ 3 8100 0000
72 * | CPU 1 CSRs |
73 * +--------------+ 3 8200 0000
74 * | CPU 2 CSRs |
75 * +--------------+ 3 8300 0000
76 * | CPU 3 CSRs |
77 * +--------------+ 3 8400 0000
78 * | CPU Reserved |
79 * +--------------+ 3 8700 0000
80 * | Mem Reserved |
81 * +--------------+ 3 8800 0000
82 * | Mem 0 CSRs |
83 * +--------------+ 3 8900 0000
84 * | Mem 1 CSRs |
85 * +--------------+ 3 8a00 0000
86 * | Mem 2 CSRs |
87 * +--------------+ 3 8b00 0000
88 * | Mem 3 CSRs |
89 * +--------------+ 3 8c00 0000
90 * | Mem Reserved |
91 * +--------------+ 3 8e00 0000
92 * | PCI Bridge |
93 * +--------------+ 3 8f00 0000
94 * | Expansion IO |
95 * +--------------+ 3 9000 0000
96 *
97 *
98 */
99 #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
100 #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
101 #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
102 #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
103 #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
104 #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
105 #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
106 #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
107
108
109 /*
110 * Sable CPU Module CSRS
111 *
112 * These are CSRs for hardware other than the CPU chip on the CPU module.
113 * The CPU module has Backup Cache control logic, Cbus control logic, and
114 * interrupt control logic on it. There is a duplicate tag store to speed
115 * up maintaining cache coherency.
116 */
117
118 struct sable_cpu_csr {
119 unsigned long bcc; long fill_00[3]; /* Backup Cache Control */
120 unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */
121 unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */
122 unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */
123 unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
124 unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */
125 unsigned long cbctl; long fill_06[3]; /* CBus Control */
126 unsigned long cbe; long fill_07[3]; /* CBus Error */
127 unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */
128 unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */
129 unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */
130 unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */
131 unsigned long sic; long fill_12[3]; /* System Interrupt Clear */
132 unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */
133 unsigned long madrl; long fill_14[3]; /* CBus Miss Address */
134 unsigned long rev; long fill_15[3]; /* CMIC Revision */
135 };
136
137 /*
138 * Data structure for handling T2 machine checks:
139 */
140 struct el_t2_frame_header {
141 unsigned int elcf_fid; /* Frame ID (from above) */
142 unsigned int elcf_size; /* Size of frame in bytes */
143 };
144
145 struct el_t2_procdata_mcheck {
146 unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */
147 /* EV4-specific fields */
148 unsigned long elfmc_exc_addr; /* Addr of excepting insn. */
149 unsigned long elfmc_exc_sum; /* Summary of arith traps. */
150 unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */
151 unsigned long elfmc_iccsr; /* IBox hardware enables. */
152 unsigned long elfmc_pal_base; /* Base address for PALcode. */
153 unsigned long elfmc_hier; /* Hardware Interrupt Enable. */
154 unsigned long elfmc_hirr; /* Hardware Interrupt Request. */
155 unsigned long elfmc_mm_csr; /* D-stream fault info. */
156 unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */
157 unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
158 unsigned long elfmc_abox_ctl; /* ABox Control Register. */
159 unsigned long elfmc_biu_stat; /* BIU Status. */
160 unsigned long elfmc_biu_addr; /* BUI Address. */
161 unsigned long elfmc_biu_ctl; /* BIU Control. */
162 unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */
163 unsigned long elfmc_fill_addr;/* Cache block which was being read. */
164 unsigned long elfmc_va; /* Effective VA of fault or miss. */
165 unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */
166 };
167
168 /*
169 * Sable processor specific Machine Check Data segment.
170 */
171
172 struct el_t2_logout_header {
173 unsigned int elfl_size; /* size in bytes of logout area. */
174 int elfl_sbz1:31; /* Should be zero. */
175 char elfl_retry:1; /* Retry flag. */
176 unsigned int elfl_procoffset; /* Processor-specific offset. */
177 unsigned int elfl_sysoffset; /* Offset of system-specific. */
178 unsigned int elfl_error_type; /* PAL error type code. */
179 unsigned int elfl_frame_rev; /* PAL Frame revision. */
180 };
181 struct el_t2_sysdata_mcheck {
182 unsigned long elcmc_bcc; /* CSR 0 */
183 unsigned long elcmc_bcce; /* CSR 1 */
184 unsigned long elcmc_bccea; /* CSR 2 */
185 unsigned long elcmc_bcue; /* CSR 3 */
186 unsigned long elcmc_bcuea; /* CSR 4 */
187 unsigned long elcmc_dter; /* CSR 5 */
188 unsigned long elcmc_cbctl; /* CSR 6 */
189 unsigned long elcmc_cbe; /* CSR 7 */
190 unsigned long elcmc_cbeal; /* CSR 8 */
191 unsigned long elcmc_cbeah; /* CSR 9 */
192 unsigned long elcmc_pmbx; /* CSR 10 */
193 unsigned long elcmc_ipir; /* CSR 11 */
194 unsigned long elcmc_sic; /* CSR 12 */
195 unsigned long elcmc_adlk; /* CSR 13 */
196 unsigned long elcmc_madrl; /* CSR 14 */
197 unsigned long elcmc_crrev4; /* CSR 15 */
198 };
199
200 /*
201 * Sable memory error frame - sable pfms section 3.42
202 */
203 struct el_t2_data_memory {
204 struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */
205 unsigned int elcm_module; /* Module id. */
206 unsigned int elcm_res04; /* Reserved. */
207 unsigned long elcm_merr; /* CSR0: Error Reg 1. */
208 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */
209 unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */
210 unsigned long elcm_mconf; /* CSR3: Configuration. */
211 unsigned long elcm_medc1; /* CSR4: EDC Status 1. */
212 unsigned long elcm_medc2; /* CSR5: EDC Status 2. */
213 unsigned long elcm_medcc; /* CSR6: EDC Control. */
214 unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */
215 unsigned long elcm_mref; /* CSR8: Refresh Control. */
216 unsigned long elcm_filter; /* CSR9: CRD Filter Control. */
217 };
218
219
220 /*
221 * Sable other CPU error frame - sable pfms section 3.43
222 */
223 struct el_t2_data_other_cpu {
224 short elco_cpuid; /* CPU ID */
225 short elco_res02[3];
226 unsigned long elco_bcc; /* CSR 0 */
227 unsigned long elco_bcce; /* CSR 1 */
228 unsigned long elco_bccea; /* CSR 2 */
229 unsigned long elco_bcue; /* CSR 3 */
230 unsigned long elco_bcuea; /* CSR 4 */
231 unsigned long elco_dter; /* CSR 5 */
232 unsigned long elco_cbctl; /* CSR 6 */
233 unsigned long elco_cbe; /* CSR 7 */
234 unsigned long elco_cbeal; /* CSR 8 */
235 unsigned long elco_cbeah; /* CSR 9 */
236 unsigned long elco_pmbx; /* CSR 10 */
237 unsigned long elco_ipir; /* CSR 11 */
238 unsigned long elco_sic; /* CSR 12 */
239 unsigned long elco_adlk; /* CSR 13 */
240 unsigned long elco_madrl; /* CSR 14 */
241 unsigned long elco_crrev4; /* CSR 15 */
242 };
243
244 /*
245 * Sable other CPU error frame - sable pfms section 3.44
246 */
247 struct el_t2_data_t2{
248 struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */
249 unsigned long elct_iocsr; /* IO Control and Status Register */
250 unsigned long elct_cerr1; /* Cbus Error Register 1 */
251 unsigned long elct_cerr2; /* Cbus Error Register 2 */
252 unsigned long elct_cerr3; /* Cbus Error Register 3 */
253 unsigned long elct_perr1; /* PCI Error Register 1 */
254 unsigned long elct_perr2; /* PCI Error Register 2 */
255 unsigned long elct_hae0_1; /* High Address Extension Register 1 */
256 unsigned long elct_hae0_2; /* High Address Extension Register 2 */
257 unsigned long elct_hbase; /* High Base Register */
258 unsigned long elct_wbase1; /* Window Base Register 1 */
259 unsigned long elct_wmask1; /* Window Mask Register 1 */
260 unsigned long elct_tbase1; /* Translated Base Register 1 */
261 unsigned long elct_wbase2; /* Window Base Register 2 */
262 unsigned long elct_wmask2; /* Window Mask Register 2 */
263 unsigned long elct_tbase2; /* Translated Base Register 2 */
264 unsigned long elct_tdr0; /* TLB Data Register 0 */
265 unsigned long elct_tdr1; /* TLB Data Register 1 */
266 unsigned long elct_tdr2; /* TLB Data Register 2 */
267 unsigned long elct_tdr3; /* TLB Data Register 3 */
268 unsigned long elct_tdr4; /* TLB Data Register 4 */
269 unsigned long elct_tdr5; /* TLB Data Register 5 */
270 unsigned long elct_tdr6; /* TLB Data Register 6 */
271 unsigned long elct_tdr7; /* TLB Data Register 7 */
272 };
273
274 /*
275 * Sable error log data structure - sable pfms section 3.40
276 */
277 struct el_t2_data_corrected {
278 unsigned long elcpb_biu_stat;
279 unsigned long elcpb_biu_addr;
280 unsigned long elcpb_biu_ctl;
281 unsigned long elcpb_fill_syndrome;
282 unsigned long elcpb_fill_addr;
283 unsigned long elcpb_bc_tag;
284 };
285
286 /*
287 * Sable error log data structure
288 * Note there are 4 memory slots on sable (see t2.h)
289 */
290 struct el_t2_frame_mcheck {
291 struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
292 struct el_t2_logout_header elfmc_hdr;
293 struct el_t2_procdata_mcheck elfmc_procdata;
294 struct el_t2_sysdata_mcheck elfmc_sysdata;
295 struct el_t2_data_t2 elfmc_t2data;
296 struct el_t2_data_memory elfmc_memdata[4];
297 struct el_t2_frame_header elfmc_footer; /* empty */
298 };
299
300
301 /*
302 * Sable error log data structures on memory errors
303 */
304 struct el_t2_frame_corrected {
305 struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
306 struct el_t2_logout_header elfcc_hdr;
307 struct el_t2_data_corrected elfcc_procdata;
308 /* struct el_t2_data_t2 elfcc_t2data; */
309 /* struct el_t2_data_memory elfcc_memdata[4]; */
310 struct el_t2_frame_header elfcc_footer; /* empty */
311 };
312
313
314 #ifdef __KERNEL__
315
316 #ifndef __EXTERN_INLINE
317 #define __EXTERN_INLINE extern inline
318 #define __IO_EXTERN_INLINE
319 #endif
320
321 /*
322 * I/O functions:
323 *
324 * T2 (the core logic PCI/memory support chipset for the SABLE
325 * series of processors uses a sparse address mapping scheme to
326 * get at PCI memory and I/O.
327 */
328
329 #define vip volatile int *
330 #define vuip volatile unsigned int *
331
332 __EXTERN_INLINE unsigned int t2_inb(unsigned long addr)
333 {
334 long result = *(vip) ((addr << 5) + T2_IO + 0x00);
335 return __kernel_extbl(result, addr & 3);
336 }
337
338 __EXTERN_INLINE void t2_outb(unsigned char b, unsigned long addr)
339 {
340 unsigned long w;
341
342 w = __kernel_insbl(b, addr & 3);
343 *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
344 mb();
345 }
346
347 __EXTERN_INLINE unsigned int t2_inw(unsigned long addr)
348 {
349 long result = *(vip) ((addr << 5) + T2_IO + 0x08);
350 return __kernel_extwl(result, addr & 3);
351 }
352
353 __EXTERN_INLINE void t2_outw(unsigned short b, unsigned long addr)
354 {
355 unsigned long w;
356
357 w = __kernel_inswl(b, addr & 3);
358 *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
359 mb();
360 }
361
362 __EXTERN_INLINE unsigned int t2_inl(unsigned long addr)
363 {
364 return *(vuip) ((addr << 5) + T2_IO + 0x18);
365 }
366
367 __EXTERN_INLINE void t2_outl(unsigned int b, unsigned long addr)
368 {
369 *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
370 mb();
371 }
372
373
374 /*
375 * Memory functions.
376 *
377 * For reading and writing 8 and 16 bit quantities we need to
378 * go through one of the three sparse address mapping regions
379 * and use the HAE_MEM CSR to provide some bits of the address.
380 * The following few routines use only sparse address region 1
381 * which gives 1Gbyte of accessible space which relates exactly
382 * to the amount of PCI memory mapping *into* system address space.
383 * See p 6-17 of the specification but it looks something like this:
384 *
385 * 21164 Address:
386 *
387 * 3 2 1
388 * 9876543210987654321098765432109876543210
389 * 1ZZZZ0.PCI.QW.Address............BBLL
390 *
391 * ZZ = SBZ
392 * BB = Byte offset
393 * LL = Transfer length
394 *
395 * PCI Address:
396 *
397 * 3 2 1
398 * 10987654321098765432109876543210
399 * HHH....PCI.QW.Address........ 00
400 *
401 * HHH = 31:29 HAE_MEM CSR
402 *
403 */
404
405 __EXTERN_INLINE unsigned long t2_readb(unsigned long addr)
406 {
407 unsigned long result, msb;
408
409 msb = addr & 0xE0000000;
410 addr &= T2_MEM_R1_MASK;
411 set_hae(msb);
412
413 result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
414 return __kernel_extbl(result, addr & 3);
415 }
416
417 __EXTERN_INLINE unsigned long t2_readw(unsigned long addr)
418 {
419 unsigned long result, msb;
420
421 msb = addr & 0xE0000000;
422 addr &= T2_MEM_R1_MASK;
423 set_hae(msb);
424
425 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
426 return __kernel_extwl(result, addr & 3);
427 }
428
429 /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
430 __EXTERN_INLINE unsigned long t2_readl(unsigned long addr)
431 {
432 unsigned long msb;
433
434 msb = addr & 0xE0000000;
435 addr &= T2_MEM_R1_MASK;
436 set_hae(msb);
437
438 return *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
439 }
440
441 __EXTERN_INLINE unsigned long t2_readq(unsigned long addr)
442 {
443 unsigned long r0, r1, work, msb;
444
445 msb = addr & 0xE0000000;
446 addr &= T2_MEM_R1_MASK;
447 set_hae(msb);
448
449 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
450 r0 = *(vuip)(work);
451 r1 = *(vuip)(work + (4 << 5));
452 return r1 << 32 | r0;
453 }
454
455 __EXTERN_INLINE void t2_writeb(unsigned char b, unsigned long addr)
456 {
457 unsigned long msb, w;
458
459 msb = addr & 0xE0000000;
460 addr &= T2_MEM_R1_MASK;
461 set_hae(msb);
462
463 w = __kernel_insbl(b, addr & 3);
464 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
465 }
466
467 __EXTERN_INLINE void t2_writew(unsigned short b, unsigned long addr)
468 {
469 unsigned long msb, w;
470
471 msb = addr & 0xE0000000;
472 addr &= T2_MEM_R1_MASK;
473 set_hae(msb);
474
475 w = __kernel_inswl(b, addr & 3);
476 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
477 }
478
479 /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
480 __EXTERN_INLINE void t2_writel(unsigned int b, unsigned long addr)
481 {
482 unsigned long msb;
483
484 msb = addr & 0xE0000000;
485 addr &= T2_MEM_R1_MASK;
486 set_hae(msb);
487
488 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
489 }
490
491 __EXTERN_INLINE void t2_writeq(unsigned long b, unsigned long addr)
492 {
493 unsigned long msb, work;
494
495 msb = addr & 0xE0000000;
496 addr &= T2_MEM_R1_MASK;
497 set_hae(msb);
498
499 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
500 *(vuip)work = b;
501 *(vuip)(work + (4 << 5)) = b >> 32;
502 }
503
504 __EXTERN_INLINE unsigned long t2_ioremap(unsigned long addr,
505 unsigned long size
506 __attribute__((unused)))
507 {
508 return addr;
509 }
510
511 __EXTERN_INLINE void t2_iounmap(unsigned long addr)
512 {
513 return;
514 }
515
516 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
517 {
518 return (long)addr >= 0;
519 }
520
521 #undef vip
522 #undef vuip
523
524 #ifdef __WANT_IO_DEF
525
526 #define __inb(p) t2_inb((unsigned long)(p))
527 #define __inw(p) t2_inw((unsigned long)(p))
528 #define __inl(p) t2_inl((unsigned long)(p))
529 #define __outb(x,p) t2_outb((x),(unsigned long)(p))
530 #define __outw(x,p) t2_outw((x),(unsigned long)(p))
531 #define __outl(x,p) t2_outl((x),(unsigned long)(p))
532 #define __readb(a) t2_readb((unsigned long)(a))
533 #define __readw(a) t2_readw((unsigned long)(a))
534 #define __readl(a) t2_readl((unsigned long)(a))
535 #define __readq(a) t2_readq((unsigned long)(a))
536 #define __writeb(x,a) t2_writeb((x),(unsigned long)(a))
537 #define __writew(x,a) t2_writew((x),(unsigned long)(a))
538 #define __writel(x,a) t2_writel((x),(unsigned long)(a))
539 #define __writeq(x,a) t2_writeq((x),(unsigned long)(a))
540 #define __ioremap(a,s) t2_ioremap((unsigned long)(a),(s))
541 #define __iounmap(a) t2_iounmap((unsigned long)(a))
542 #define __is_ioaddr(a) t2_is_ioaddr((unsigned long)(a))
543
544 #endif /* __WANT_IO_DEF */
545
546 #ifdef __IO_EXTERN_INLINE
547 #undef __EXTERN_INLINE
548 #undef __IO_EXTERN_INLINE
549 #endif
550
551 #endif /* __KERNEL__ */
552
553 #endif /* __ALPHA_T2__H__ */
554