File: /usr/src/linux/drivers/char/drm/i810_drm.h
1 #ifndef _I810_DRM_H_
2 #define _I810_DRM_H_
3
4 /* WARNING: These defines must be the same as what the Xserver uses.
5 * if you change them, you must change the defines in the Xserver.
6 */
7
8 #ifndef _I810_DEFINES_
9 #define _I810_DEFINES_
10
11 #define I810_DMA_BUF_ORDER 12
12 #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
13 #define I810_DMA_BUF_NR 256
14 #define I810_NR_SAREA_CLIPRECTS 8
15
16 /* Each region is a minimum of 64k, and there are at most 64 of them.
17 */
18 #define I810_NR_TEX_REGIONS 64
19 #define I810_LOG_MIN_TEX_REGION_SIZE 16
20 #endif
21
22 #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23 #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24 #define I810_UPLOAD_CTX 0x4
25 #define I810_UPLOAD_BUFFERS 0x8
26 #define I810_UPLOAD_TEX0 0x10
27 #define I810_UPLOAD_TEX1 0x20
28 #define I810_UPLOAD_CLIPRECTS 0x40
29
30
31 /* Indices into buf.Setup where various bits of state are mirrored per
32 * context and per buffer. These can be fired at the card as a unit,
33 * or in a piecewise fashion as required.
34 */
35
36 /* Destbuffer state
37 * - backbuffer linear offset and pitch -- invarient in the current dri
38 * - zbuffer linear offset and pitch -- also invarient
39 * - drawing origin in back and depth buffers.
40 *
41 * Keep the depth/back buffer state here to acommodate private buffers
42 * in the future.
43 */
44 #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
45 #define I810_DESTREG_DI1 1
46 #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
47 #define I810_DESTREG_DV1 3
48 #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
49 #define I810_DESTREG_DR1 5
50 #define I810_DESTREG_DR2 6
51 #define I810_DESTREG_DR3 7
52 #define I810_DESTREG_DR4 8
53 #define I810_DEST_SETUP_SIZE 10
54
55 /* Context state
56 */
57 #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
58 #define I810_CTXREG_CF1 1
59 #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
60 #define I810_CTXREG_ST1 3
61 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
62 #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
63 #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
64 #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
65 #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
66 #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
67 #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
68 #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
69 #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */
70 #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */
71 #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */
72 #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */
73 #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
74 #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
75 #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
76 #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
77 #define I810_CTX_SETUP_SIZE 20
78
79 /* Texture state (per tex unit)
80 */
81 #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
82 #define I810_TEXREG_MI1 1
83 #define I810_TEXREG_MI2 2
84 #define I810_TEXREG_MI3 3
85 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
86 #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
87 #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
88 #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */
89 #define I810_TEX_SETUP_SIZE 8
90
91 #define I810_FRONT 0x1
92 #define I810_BACK 0x2
93 #define I810_DEPTH 0x4
94
95
96 typedef struct _drm_i810_init {
97 enum {
98 I810_INIT_DMA = 0x01,
99 I810_CLEANUP_DMA = 0x02
100 } func;
101 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
102 int ring_map_idx;
103 int buffer_map_idx;
104 #else
105 unsigned int mmio_offset;
106 unsigned int buffers_offset;
107 #endif
108 int sarea_priv_offset;
109 unsigned int ring_start;
110 unsigned int ring_end;
111 unsigned int ring_size;
112 unsigned int front_offset;
113 unsigned int back_offset;
114 unsigned int depth_offset;
115 unsigned int w;
116 unsigned int h;
117 unsigned int pitch;
118 unsigned int pitch_bits;
119 } drm_i810_init_t;
120
121 /* Warning: If you change the SAREA structure you must change the Xserver
122 * structure as well */
123
124 typedef struct _drm_i810_tex_region {
125 unsigned char next, prev; /* indices to form a circular LRU */
126 unsigned char in_use; /* owned by a client, or free? */
127 int age; /* tracked by clients to update local LRU's */
128 } drm_i810_tex_region_t;
129
130 typedef struct _drm_i810_sarea {
131 unsigned int ContextState[I810_CTX_SETUP_SIZE];
132 unsigned int BufferState[I810_DEST_SETUP_SIZE];
133 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
134 unsigned int dirty;
135
136 unsigned int nbox;
137 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
138
139 /* Maintain an LRU of contiguous regions of texture space. If
140 * you think you own a region of texture memory, and it has an
141 * age different to the one you set, then you are mistaken and
142 * it has been stolen by another client. If global texAge
143 * hasn't changed, there is no need to walk the list.
144 *
145 * These regions can be used as a proxy for the fine-grained
146 * texture information of other clients - by maintaining them
147 * in the same lru which is used to age their own textures,
148 * clients have an approximate lru for the whole of global
149 * texture space, and can make informed decisions as to which
150 * areas to kick out. There is no need to choose whether to
151 * kick out your own texture or someone else's - simply eject
152 * them all in LRU order.
153 */
154
155 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1];
156 /* Last elt is sentinal */
157 int texAge; /* last time texture was uploaded */
158 int last_enqueue; /* last time a buffer was enqueued */
159 int last_dispatch; /* age of the most recently dispatched buffer */
160 int last_quiescent; /* */
161 int ctxOwner; /* last context to upload state */
162
163 int vertex_prim;
164
165 } drm_i810_sarea_t;
166
167 typedef struct _drm_i810_clear {
168 int clear_color;
169 int clear_depth;
170 int flags;
171 } drm_i810_clear_t;
172
173
174
175 /* These may be placeholders if we have more cliprects than
176 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
177 * false, indicating that the buffer will be dispatched again with a
178 * new set of cliprects.
179 */
180 typedef struct _drm_i810_vertex {
181 int idx; /* buffer index */
182 int used; /* nr bytes in use */
183 int discard; /* client is finished with the buffer? */
184 } drm_i810_vertex_t;
185
186 typedef struct _drm_i810_copy_t {
187 int idx; /* buffer index */
188 int used; /* nr bytes in use */
189 void *address; /* Address to copy from */
190 } drm_i810_copy_t;
191
192 typedef struct drm_i810_dma {
193 void *virtual;
194 int request_idx;
195 int request_size;
196 int granted;
197 } drm_i810_dma_t;
198
199 #endif /* _I810_DRM_H_ */
200