File: /usr/src/linux/drivers/char/drm/drm.h
1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 *
30 * Acknowledgements:
31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
32 *
33 */
34
35 #ifndef _DRM_H_
36 #define _DRM_H_
37
38 #if defined(__linux__)
39 #include <linux/config.h>
40 #include <asm/ioctl.h> /* For _IO* macros */
41 #define DRM_IOCTL_NR(n) _IOC_NR(n)
42 #elif defined(__FreeBSD__)
43 #include <sys/ioccom.h>
44 #define DRM_IOCTL_NR(n) ((n) & 0xff)
45 #endif
46
47 #define XFREE86_VERSION(major,minor,patch,snap) \
48 ((major << 16) | (minor << 8) | patch)
49
50 #ifndef CONFIG_XFREE86_VERSION
51 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
52 #endif
53
54 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
55 #define DRM_PROC_DEVICES "/proc/devices"
56 #define DRM_PROC_MISC "/proc/misc"
57 #define DRM_PROC_DRM "/proc/drm"
58 #define DRM_DEV_DRM "/dev/drm"
59 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
60 #define DRM_DEV_UID 0
61 #define DRM_DEV_GID 0
62 #endif
63
64 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
65 #define DRM_MAJOR 226
66 #define DRM_MAX_MINOR 15
67 #endif
68 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
69 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
70 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
71 #define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */
72
73 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
74 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
75 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
76 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
77 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
78
79 typedef unsigned long drm_handle_t;
80 typedef unsigned int drm_context_t;
81 typedef unsigned int drm_drawable_t;
82 typedef unsigned int drm_magic_t;
83
84 /* Warning: If you change this structure, make sure you change
85 * XF86DRIClipRectRec in the server as well */
86
87 typedef struct drm_clip_rect {
88 unsigned short x1;
89 unsigned short y1;
90 unsigned short x2;
91 unsigned short y2;
92 } drm_clip_rect_t;
93
94 typedef struct drm_tex_region {
95 unsigned char next;
96 unsigned char prev;
97 unsigned char in_use;
98 unsigned char padding;
99 unsigned int age;
100 } drm_tex_region_t;
101
102 /* Seperate include files for the i810/mga/r128 specific structures */
103 #include "mga_drm.h"
104 #include "i810_drm.h"
105 #include "r128_drm.h"
106 #include "radeon_drm.h"
107 #ifdef CONFIG_DRM_SIS
108 #include "sis_drm.h"
109 #endif
110
111 typedef struct drm_version {
112 int version_major; /* Major version */
113 int version_minor; /* Minor version */
114 int version_patchlevel;/* Patch level */
115 size_t name_len; /* Length of name buffer */
116 char *name; /* Name of driver */
117 size_t date_len; /* Length of date buffer */
118 char *date; /* User-space buffer to hold date */
119 size_t desc_len; /* Length of desc buffer */
120 char *desc; /* User-space buffer to hold desc */
121 } drm_version_t;
122
123 typedef struct drm_unique {
124 size_t unique_len; /* Length of unique */
125 char *unique; /* Unique name for driver instantiation */
126 } drm_unique_t;
127
128 typedef struct drm_list {
129 int count; /* Length of user-space structures */
130 drm_version_t *version;
131 } drm_list_t;
132
133 typedef struct drm_block {
134 int unused;
135 } drm_block_t;
136
137 typedef struct drm_control {
138 enum {
139 DRM_ADD_COMMAND,
140 DRM_RM_COMMAND,
141 DRM_INST_HANDLER,
142 DRM_UNINST_HANDLER
143 } func;
144 int irq;
145 } drm_control_t;
146
147 typedef enum drm_map_type {
148 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
149 _DRM_REGISTERS = 1, /* no caching, no core dump */
150 _DRM_SHM = 2, /* shared, cached */
151 _DRM_AGP = 3, /* AGP/GART */
152 _DRM_SCATTER_GATHER = 4 /* Scatter/gather memory for PCI DMA */
153 } drm_map_type_t;
154
155 typedef enum drm_map_flags {
156 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
157 _DRM_READ_ONLY = 0x02,
158 _DRM_LOCKED = 0x04, /* shared, cached, locked */
159 _DRM_KERNEL = 0x08, /* kernel requires access */
160 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
161 _DRM_CONTAINS_LOCK = 0x20, /* SHM page that contains lock */
162 _DRM_REMOVABLE = 0x40 /* Removable mapping */
163 } drm_map_flags_t;
164
165 typedef struct drm_ctx_priv_map {
166 unsigned int ctx_id; /* Context requesting private mapping */
167 void *handle; /* Handle of map */
168 } drm_ctx_priv_map_t;
169
170 typedef struct drm_map {
171 unsigned long offset; /* Requested physical address (0 for SAREA)*/
172 unsigned long size; /* Requested physical size (bytes) */
173 drm_map_type_t type; /* Type of memory to map */
174 drm_map_flags_t flags; /* Flags */
175 void *handle; /* User-space: "Handle" to pass to mmap */
176 /* Kernel-space: kernel-virtual address */
177 int mtrr; /* MTRR slot used */
178 /* Private data */
179 } drm_map_t;
180
181 typedef struct drm_client {
182 int idx; /* Which client desired? */
183 int auth; /* Is client authenticated? */
184 unsigned long pid; /* Process id */
185 unsigned long uid; /* User id */
186 unsigned long magic; /* Magic */
187 unsigned long iocs; /* Ioctl count */
188 } drm_client_t;
189
190 typedef enum {
191 _DRM_STAT_LOCK,
192 _DRM_STAT_OPENS,
193 _DRM_STAT_CLOSES,
194 _DRM_STAT_IOCTLS,
195 _DRM_STAT_LOCKS,
196 _DRM_STAT_UNLOCKS,
197 _DRM_STAT_VALUE, /* Generic value */
198 _DRM_STAT_BYTE, /* Generic byte counter (1024bytes/K) */
199 _DRM_STAT_COUNT, /* Generic non-byte counter (1000/k) */
200
201 _DRM_STAT_IRQ, /* IRQ */
202 _DRM_STAT_PRIMARY, /* Primary DMA bytes */
203 _DRM_STAT_SECONDARY, /* Secondary DMA bytes */
204 _DRM_STAT_DMA, /* DMA */
205 _DRM_STAT_SPECIAL, /* Special DMA (e.g., priority or polled) */
206 _DRM_STAT_MISSED /* Missed DMA opportunity */
207
208 /* Add to the *END* of the list */
209 } drm_stat_type_t;
210
211 typedef struct drm_stats {
212 unsigned long count;
213 struct {
214 unsigned long value;
215 drm_stat_type_t type;
216 } data[15];
217 } drm_stats_t;
218
219 typedef enum drm_lock_flags {
220 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
221 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
222 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
223 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
224 /* These *HALT* flags aren't supported yet
225 -- they will be used to support the
226 full-screen DGA-like mode. */
227 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
228 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
229 } drm_lock_flags_t;
230
231 typedef struct drm_lock {
232 int context;
233 drm_lock_flags_t flags;
234 } drm_lock_t;
235
236 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
237 /* Flags for DMA buffer dispatch */
238 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
239 Note, the buffer may not yet have
240 been processed by the hardware --
241 getting a hardware lock with the
242 hardware quiescent will ensure
243 that the buffer has been
244 processed. */
245 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
246 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
247
248 /* Flags for DMA buffer request */
249 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
250 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
251 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
252 } drm_dma_flags_t;
253
254 typedef struct drm_buf_desc {
255 int count; /* Number of buffers of this size */
256 int size; /* Size in bytes */
257 int low_mark; /* Low water mark */
258 int high_mark; /* High water mark */
259 enum {
260 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
261 _DRM_AGP_BUFFER = 0x02, /* Buffer is in agp space */
262 _DRM_SG_BUFFER = 0x04 /* Scatter/gather memory buffer */
263 } flags;
264 unsigned long agp_start; /* Start address of where the agp buffers
265 * are in the agp aperture */
266 } drm_buf_desc_t;
267
268 typedef struct drm_buf_info {
269 int count; /* Entries in list */
270 drm_buf_desc_t *list;
271 } drm_buf_info_t;
272
273 typedef struct drm_buf_free {
274 int count;
275 int *list;
276 } drm_buf_free_t;
277
278 typedef struct drm_buf_pub {
279 int idx; /* Index into master buflist */
280 int total; /* Buffer size */
281 int used; /* Amount of buffer in use (for DMA) */
282 void *address; /* Address of buffer */
283 } drm_buf_pub_t;
284
285 typedef struct drm_buf_map {
286 int count; /* Length of buflist */
287 void *virtual; /* Mmaped area in user-virtual */
288 drm_buf_pub_t *list; /* Buffer information */
289 } drm_buf_map_t;
290
291 typedef struct drm_dma {
292 /* Indices here refer to the offset into
293 buflist in drm_buf_get_t. */
294 int context; /* Context handle */
295 int send_count; /* Number of buffers to send */
296 int *send_indices; /* List of handles to buffers */
297 int *send_sizes; /* Lengths of data to send */
298 drm_dma_flags_t flags; /* Flags */
299 int request_count; /* Number of buffers requested */
300 int request_size; /* Desired size for buffers */
301 int *request_indices; /* Buffer information */
302 int *request_sizes;
303 int granted_count; /* Number of buffers granted */
304 } drm_dma_t;
305
306 typedef enum {
307 _DRM_CONTEXT_PRESERVED = 0x01,
308 _DRM_CONTEXT_2DONLY = 0x02
309 } drm_ctx_flags_t;
310
311 typedef struct drm_ctx {
312 drm_context_t handle;
313 drm_ctx_flags_t flags;
314 } drm_ctx_t;
315
316 typedef struct drm_ctx_res {
317 int count;
318 drm_ctx_t *contexts;
319 } drm_ctx_res_t;
320
321 typedef struct drm_draw {
322 drm_drawable_t handle;
323 } drm_draw_t;
324
325 typedef struct drm_auth {
326 drm_magic_t magic;
327 } drm_auth_t;
328
329 typedef struct drm_irq_busid {
330 int irq;
331 int busnum;
332 int devnum;
333 int funcnum;
334 } drm_irq_busid_t;
335
336 typedef struct drm_agp_mode {
337 unsigned long mode;
338 } drm_agp_mode_t;
339
340 /* For drm_agp_alloc -- allocated a buffer */
341 typedef struct drm_agp_buffer {
342 unsigned long size; /* In bytes -- will round to page boundary */
343 unsigned long handle; /* Used for BIND/UNBIND ioctls */
344 unsigned long type; /* Type of memory to allocate */
345 unsigned long physical; /* Physical used by i810 */
346 } drm_agp_buffer_t;
347
348 /* For drm_agp_bind */
349 typedef struct drm_agp_binding {
350 unsigned long handle; /* From drm_agp_buffer */
351 unsigned long offset; /* In bytes -- will round to page boundary */
352 } drm_agp_binding_t;
353
354 typedef struct drm_agp_info {
355 int agp_version_major;
356 int agp_version_minor;
357 unsigned long mode;
358 unsigned long aperture_base; /* physical address */
359 unsigned long aperture_size; /* bytes */
360 unsigned long memory_allowed; /* bytes */
361 unsigned long memory_used;
362
363 /* PCI information */
364 unsigned short id_vendor;
365 unsigned short id_device;
366 } drm_agp_info_t;
367
368 typedef struct drm_scatter_gather {
369 unsigned long size; /* In bytes -- will round to page boundary */
370 unsigned long handle; /* Used for mapping / unmapping */
371 } drm_scatter_gather_t;
372
373 #define DRM_IOCTL_BASE 'd'
374 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
375 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
376 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
377 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
378
379
380 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
381 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
382 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
383 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
384 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
385 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
386 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
387
388 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
389 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
390 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
391 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
392 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
393 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
394 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
395 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
396 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
397 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
398 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
399
400 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
401
402 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
403 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
404
405 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
406 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
407 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
408 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
409 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
410 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
411 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
412 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
413 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
414 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
415 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
416 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
417 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
418
419 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
420 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
421 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
422 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
423 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
424 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
425 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
426 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
427
428 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
429 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
430
431 /* MGA specific ioctls */
432 #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
433 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
434 #define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
435 #define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
436 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
437 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
438 #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
439 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
440 #define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
441
442 /* i810 specific ioctls */
443 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
444 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
445 #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
446 #define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
447 #define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
448 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
449 #define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
450 #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
451 #define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
452
453 /* Rage 128 specific ioctls */
454 #define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
455 #define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
456 #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
457 #define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
458 #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
459 #define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
460 #define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
461 #define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
462 #define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
463 #define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
464 #define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
465 #define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
466 #define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
467 #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
468 #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
469
470 /* Radeon specific ioctls */
471 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
472 #define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
473 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
474 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
475 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
476 #define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
477 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
478 #define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
479 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
480 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
481 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
482 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
483 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
484 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
485
486 #ifdef CONFIG_DRM_SIS
487 /* SiS specific ioctls */
488 #define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
489 #define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
490 #define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
491 #define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
492 #define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
493 #define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
494 #define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
495 #define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
496 #endif
497
498 #endif
499