File: /usr/src/linux/arch/sparc64/kernel/pci_iommu.c
1 /* $Id: pci_iommu.c,v 1.15 2001/08/24 19:36:58 kanoj Exp $
2 * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/mm.h>
11
12 #include <asm/pbm.h>
13
14 #include "iommu_common.h"
15
16 #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
17 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
18
19 /* Accessing IOMMU and Streaming Buffer registers.
20 * REG parameter is a physical address. All registers
21 * are 64-bits in size.
22 */
23 #define pci_iommu_read(__reg) \
24 ({ u64 __ret; \
25 __asm__ __volatile__("ldxa [%1] %2, %0" \
26 : "=r" (__ret) \
27 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
28 : "memory"); \
29 __ret; \
30 })
31 #define pci_iommu_write(__reg, __val) \
32 __asm__ __volatile__("stxa %0, [%1] %2" \
33 : /* no outputs */ \
34 : "r" (__val), "r" (__reg), \
35 "i" (ASI_PHYS_BYPASS_EC_E))
36
37 /* Must be invoked under the IOMMU lock. */
38 static void __iommu_flushall(struct pci_iommu *iommu)
39 {
40 unsigned long tag;
41 int entry;
42
43 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
44 for (entry = 0; entry < 16; entry++) {
45 pci_iommu_write(tag, 0);
46 tag += 8;
47 }
48
49 /* Ensure completion of previous PIO writes. */
50 (void) pci_iommu_read(iommu->write_complete_reg);
51
52 /* Now update everyone's flush point. */
53 for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
54 iommu->alloc_info[entry].flush =
55 iommu->alloc_info[entry].next;
56 }
57 }
58
59 static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
60 {
61 iopte_t *iopte, *limit, *first;
62 unsigned long cnum, ent, flush_point;
63
64 cnum = 0;
65 while ((1UL << cnum) < npages)
66 cnum++;
67 iopte = (iommu->page_table +
68 (cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
69
70 if (cnum == 0)
71 limit = (iommu->page_table +
72 iommu->lowest_consistent_map);
73 else
74 limit = (iopte +
75 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
76
77 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
78 flush_point = iommu->alloc_info[cnum].flush;
79
80 first = iopte;
81 for (;;) {
82 if (iopte_val(*iopte) == 0UL) {
83 if ((iopte + (1 << cnum)) >= limit)
84 ent = 0;
85 else
86 ent = ent + 1;
87 iommu->alloc_info[cnum].next = ent;
88 if (ent == flush_point)
89 __iommu_flushall(iommu);
90 break;
91 }
92 iopte += (1 << cnum);
93 ent++;
94 if (iopte >= limit) {
95 iopte = (iommu->page_table +
96 (cnum <<
97 (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
98 ent = 0;
99 }
100 if (ent == flush_point)
101 __iommu_flushall(iommu);
102 if (iopte == first)
103 goto bad;
104 }
105
106 /* I've got your streaming cluster right here buddy boy... */
107 return iopte;
108
109 bad:
110 printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
111 npages);
112 return NULL;
113 }
114
115 static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
116 unsigned long npages, unsigned long ctx)
117 {
118 unsigned long cnum, ent;
119
120 cnum = 0;
121 while ((1UL << cnum) < npages)
122 cnum++;
123
124 ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
125 >> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
126
127 /* If the global flush might not have caught this entry,
128 * adjust the flush point such that we will flush before
129 * ever trying to reuse it.
130 */
131 #define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
132 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
133 iommu->alloc_info[cnum].flush = ent;
134 #undef between
135 }
136
137 /* We allocate consistent mappings from the end of cluster zero. */
138 static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
139 {
140 iopte_t *iopte;
141
142 iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
143 while (iopte > iommu->page_table) {
144 iopte--;
145 if (!(iopte_val(*iopte) & IOPTE_VALID)) {
146 unsigned long tmp = npages;
147
148 while (--tmp) {
149 iopte--;
150 if (iopte_val(*iopte) & IOPTE_VALID)
151 break;
152 }
153 if (tmp == 0) {
154 u32 entry = (iopte - iommu->page_table);
155
156 if (entry < iommu->lowest_consistent_map)
157 iommu->lowest_consistent_map = entry;
158 return iopte;
159 }
160 }
161 }
162 return NULL;
163 }
164
165 #define IOPTE_CONSISTENT(CTX) \
166 (IOPTE_VALID | IOPTE_CACHE | \
167 (((CTX) << 47) & IOPTE_CONTEXT))
168
169 #define IOPTE_STREAMING(CTX) \
170 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
171
172 #define IOPTE_INVALID 0UL
173
174 /* Allocate and map kernel buffer of size SIZE using consistent mode
175 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
176 * successful and set *DMA_ADDRP to the PCI side dma address.
177 */
178 void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
179 {
180 struct pcidev_cookie *pcp;
181 struct pci_iommu *iommu;
182 iopte_t *iopte;
183 unsigned long flags, order, first_page, ctx;
184 void *ret;
185 int npages;
186
187 size = IO_PAGE_ALIGN(size);
188 order = get_order(size);
189 if (order >= 10)
190 return NULL;
191
192 first_page = __get_free_pages(GFP_ATOMIC, order);
193 if (first_page == 0UL)
194 return NULL;
195 memset((char *)first_page, 0, PAGE_SIZE << order);
196
197 pcp = pdev->sysdata;
198 iommu = pcp->pbm->iommu;
199
200 spin_lock_irqsave(&iommu->lock, flags);
201 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
202 if (iopte == NULL) {
203 spin_unlock_irqrestore(&iommu->lock, flags);
204 free_pages(first_page, order);
205 return NULL;
206 }
207
208 *dma_addrp = (iommu->page_table_map_base +
209 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
210 ret = (void *) first_page;
211 npages = size >> IO_PAGE_SHIFT;
212 ctx = 0;
213 if (iommu->iommu_ctxflush)
214 ctx = iommu->iommu_cur_ctx++;
215 first_page = __pa(first_page);
216 while (npages--) {
217 iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
218 IOPTE_WRITE |
219 (first_page & IOPTE_PAGE));
220 iopte++;
221 first_page += IO_PAGE_SIZE;
222 }
223
224 {
225 int i;
226 u32 daddr = *dma_addrp;
227
228 npages = size >> IO_PAGE_SHIFT;
229 for (i = 0; i < npages; i++) {
230 pci_iommu_write(iommu->iommu_flush, daddr);
231 daddr += IO_PAGE_SIZE;
232 }
233 }
234
235 spin_unlock_irqrestore(&iommu->lock, flags);
236
237 return ret;
238 }
239
240 /* Free and unmap a consistent DMA translation. */
241 void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
242 {
243 struct pcidev_cookie *pcp;
244 struct pci_iommu *iommu;
245 iopte_t *iopte;
246 unsigned long flags, order, npages, i, ctx;
247
248 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
249 pcp = pdev->sysdata;
250 iommu = pcp->pbm->iommu;
251 iopte = iommu->page_table +
252 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
253
254 spin_lock_irqsave(&iommu->lock, flags);
255
256 if ((iopte - iommu->page_table) ==
257 iommu->lowest_consistent_map) {
258 iopte_t *walk = iopte + npages;
259 iopte_t *limit;
260
261 limit = (iommu->page_table +
262 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
263 while (walk < limit) {
264 if (iopte_val(*walk) != IOPTE_INVALID)
265 break;
266 walk++;
267 }
268 iommu->lowest_consistent_map =
269 (walk - iommu->page_table);
270 }
271
272 /* Data for consistent mappings cannot enter the streaming
273 * buffers, so we only need to update the TSB. We flush
274 * the IOMMU here as well to prevent conflicts with the
275 * streaming mapping deferred tlb flush scheme.
276 */
277
278 ctx = 0;
279 if (iommu->iommu_ctxflush)
280 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
281
282 for (i = 0; i < npages; i++, iopte++)
283 iopte_val(*iopte) = IOPTE_INVALID;
284
285 if (iommu->iommu_ctxflush) {
286 pci_iommu_write(iommu->iommu_ctxflush, ctx);
287 } else {
288 for (i = 0; i < npages; i++) {
289 u32 daddr = dvma + (i << IO_PAGE_SHIFT);
290
291 pci_iommu_write(iommu->iommu_flush, daddr);
292 }
293 }
294
295 spin_unlock_irqrestore(&iommu->lock, flags);
296
297 order = get_order(size);
298 if (order < 10)
299 free_pages((unsigned long)cpu, order);
300 }
301
302 /* Map a single buffer at PTR of SZ bytes for PCI DMA
303 * in streaming mode.
304 */
305 dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
306 {
307 struct pcidev_cookie *pcp;
308 struct pci_iommu *iommu;
309 struct pci_strbuf *strbuf;
310 iopte_t *base;
311 unsigned long flags, npages, oaddr;
312 unsigned long i, base_paddr, ctx;
313 u32 bus_addr, ret;
314 unsigned long iopte_protection;
315
316 pcp = pdev->sysdata;
317 iommu = pcp->pbm->iommu;
318 strbuf = &pcp->pbm->stc;
319
320 if (direction == PCI_DMA_NONE)
321 BUG();
322
323 oaddr = (unsigned long)ptr;
324 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
325 npages >>= IO_PAGE_SHIFT;
326
327 spin_lock_irqsave(&iommu->lock, flags);
328
329 base = alloc_streaming_cluster(iommu, npages);
330 if (base == NULL)
331 goto bad;
332 bus_addr = (iommu->page_table_map_base +
333 ((base - iommu->page_table) << IO_PAGE_SHIFT));
334 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
335 base_paddr = __pa(oaddr & IO_PAGE_MASK);
336 ctx = 0;
337 if (iommu->iommu_ctxflush)
338 ctx = iommu->iommu_cur_ctx++;
339 if (strbuf->strbuf_enabled)
340 iopte_protection = IOPTE_STREAMING(ctx);
341 else
342 iopte_protection = IOPTE_CONSISTENT(ctx);
343 if (direction != PCI_DMA_TODEVICE)
344 iopte_protection |= IOPTE_WRITE;
345
346 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
347 iopte_val(*base) = iopte_protection | base_paddr;
348
349 spin_unlock_irqrestore(&iommu->lock, flags);
350
351 return ret;
352
353 bad:
354 spin_unlock_irqrestore(&iommu->lock, flags);
355 BUG();
356 return 0;
357 }
358
359 /* Unmap a single streaming mode DMA translation. */
360 void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
361 {
362 struct pcidev_cookie *pcp;
363 struct pci_iommu *iommu;
364 struct pci_strbuf *strbuf;
365 iopte_t *base;
366 unsigned long flags, npages, i, ctx;
367
368 if (direction == PCI_DMA_NONE)
369 BUG();
370
371 pcp = pdev->sysdata;
372 iommu = pcp->pbm->iommu;
373 strbuf = &pcp->pbm->stc;
374
375 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
376 npages >>= IO_PAGE_SHIFT;
377 base = iommu->page_table +
378 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
379 #ifdef DEBUG_PCI_IOMMU
380 if (iopte_val(*base) == IOPTE_INVALID)
381 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n", bus_addr, sz, __builtin_return_address(0));
382 #endif
383 bus_addr &= IO_PAGE_MASK;
384
385 spin_lock_irqsave(&iommu->lock, flags);
386
387 /* Record the context, if any. */
388 ctx = 0;
389 if (iommu->iommu_ctxflush)
390 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
391
392 /* Step 1: Kick data out of streaming buffers if necessary. */
393 if (strbuf->strbuf_enabled) {
394 u32 vaddr = bus_addr;
395
396 PCI_STC_FLUSHFLAG_INIT(strbuf);
397 if (strbuf->strbuf_ctxflush &&
398 iommu->iommu_ctxflush) {
399 unsigned long matchreg, flushreg;
400
401 flushreg = strbuf->strbuf_ctxflush;
402 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
403 do {
404 pci_iommu_write(flushreg, ctx);
405 } while(((long)pci_iommu_read(matchreg)) < 0L);
406 } else {
407 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
408 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
409 }
410
411 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
412 (void) pci_iommu_read(iommu->write_complete_reg);
413 while (!PCI_STC_FLUSHFLAG_SET(strbuf))
414 membar("#LoadLoad");
415 }
416
417 /* Step 2: Clear out first TSB entry. */
418 iopte_val(*base) = IOPTE_INVALID;
419
420 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
421 npages, ctx);
422
423 spin_unlock_irqrestore(&iommu->lock, flags);
424 }
425
426 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, unsigned long iopte_protection)
427 {
428 struct scatterlist *dma_sg = sg;
429 int i;
430
431 for (i = 0; i < nused; i++) {
432 unsigned long pteval = ~0UL;
433 u32 dma_npages;
434
435 dma_npages = ((dma_sg->dvma_address & (IO_PAGE_SIZE - 1UL)) +
436 dma_sg->dvma_length +
437 ((u32)(IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
438 do {
439 unsigned long offset;
440 signed int len;
441
442 /* If we are here, we know we have at least one
443 * more page to map. So walk forward until we
444 * hit a page crossing, and begin creating new
445 * mappings from that spot.
446 */
447 for (;;) {
448 unsigned long tmp;
449
450 tmp = (unsigned long) __pa(sg->address);
451 len = sg->length;
452 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
453 pteval = tmp & IO_PAGE_MASK;
454 offset = tmp & (IO_PAGE_SIZE - 1UL);
455 break;
456 }
457 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
458 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
459 offset = 0UL;
460 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
461 break;
462 }
463 sg++;
464 }
465
466 pteval = iopte_protection | (pteval & IOPTE_PAGE);
467 while (len > 0) {
468 *iopte++ = __iopte(pteval);
469 pteval += IO_PAGE_SIZE;
470 len -= (IO_PAGE_SIZE - offset);
471 offset = 0;
472 dma_npages--;
473 }
474
475 pteval = (pteval & IOPTE_PAGE) + len;
476 sg++;
477
478 /* Skip over any tail mappings we've fully mapped,
479 * adjusting pteval along the way. Stop when we
480 * detect a page crossing event.
481 */
482 while ((pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
483 pteval == __pa(sg->address) &&
484 ((pteval ^
485 (__pa(sg->address) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
486 pteval += sg->length;
487 sg++;
488 }
489 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
490 pteval = ~0UL;
491 } while (dma_npages != 0);
492 dma_sg++;
493 }
494 }
495
496 /* Map a set of buffers described by SGLIST with NELEMS array
497 * elements in streaming mode for PCI DMA.
498 * When making changes here, inspect the assembly output. I was having
499 * hard time to kepp this routine out of using stack slots for holding variables.
500 */
501 int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
502 {
503 struct pcidev_cookie *pcp;
504 struct pci_iommu *iommu;
505 struct pci_strbuf *strbuf;
506 unsigned long flags, ctx, npages, iopte_protection;
507 iopte_t *base;
508 u32 dma_base;
509 struct scatterlist *sgtmp;
510 int used;
511
512 /* Fast path single entry scatterlists. */
513 if (nelems == 1) {
514 sglist->dvma_address = pci_map_single(pdev, sglist->address, sglist->length, direction);
515 sglist->dvma_length = sglist->length;
516 return 1;
517 }
518
519 pcp = pdev->sysdata;
520 iommu = pcp->pbm->iommu;
521 strbuf = &pcp->pbm->stc;
522
523 if (direction == PCI_DMA_NONE)
524 BUG();
525
526 /* Step 1: Prepare scatter list. */
527
528 npages = prepare_sg(sglist, nelems);
529
530 /* Step 2: Allocate a cluster. */
531
532 spin_lock_irqsave(&iommu->lock, flags);
533
534 base = alloc_streaming_cluster(iommu, npages);
535 if (base == NULL)
536 goto bad;
537 dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
538
539 /* Step 3: Normalize DMA addresses. */
540 used = nelems;
541
542 sgtmp = sglist;
543 while (used && sgtmp->dvma_length) {
544 sgtmp->dvma_address += dma_base;
545 sgtmp++;
546 used--;
547 }
548 used = nelems - used;
549
550 /* Step 4: Choose a context if necessary. */
551 ctx = 0;
552 if (iommu->iommu_ctxflush)
553 ctx = iommu->iommu_cur_ctx++;
554
555 /* Step 5: Create the mappings. */
556 if (strbuf->strbuf_enabled)
557 iopte_protection = IOPTE_STREAMING(ctx);
558 else
559 iopte_protection = IOPTE_CONSISTENT(ctx);
560 if (direction != PCI_DMA_TODEVICE)
561 iopte_protection |= IOPTE_WRITE;
562 fill_sg (base, sglist, used, iopte_protection);
563 #ifdef VERIFY_SG
564 verify_sglist(sglist, nelems, base, npages);
565 #endif
566
567 spin_unlock_irqrestore(&iommu->lock, flags);
568
569 return used;
570
571 bad:
572 spin_unlock_irqrestore(&iommu->lock, flags);
573 BUG();
574 return 0;
575 }
576
577 /* Unmap a set of streaming mode DMA translations. */
578 void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
579 {
580 struct pcidev_cookie *pcp;
581 struct pci_iommu *iommu;
582 struct pci_strbuf *strbuf;
583 iopte_t *base;
584 unsigned long flags, ctx, i, npages;
585 u32 bus_addr;
586
587 if (direction == PCI_DMA_NONE)
588 BUG();
589
590 pcp = pdev->sysdata;
591 iommu = pcp->pbm->iommu;
592 strbuf = &pcp->pbm->stc;
593
594 bus_addr = sglist->dvma_address & IO_PAGE_MASK;
595
596 for (i = 1; i < nelems; i++)
597 if (sglist[i].dvma_length == 0)
598 break;
599 i--;
600 npages = (IO_PAGE_ALIGN(sglist[i].dvma_address + sglist[i].dvma_length) - bus_addr) >> IO_PAGE_SHIFT;
601
602 base = iommu->page_table +
603 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
604
605 #ifdef DEBUG_PCI_IOMMU
606 if (iopte_val(*base) == IOPTE_INVALID)
607 printk("pci_unmap_sg called on non-mapped region %08x,%d from %016lx\n", sglist->dvma_address, nelems, __builtin_return_address(0));
608 #endif
609
610 spin_lock_irqsave(&iommu->lock, flags);
611
612 /* Record the context, if any. */
613 ctx = 0;
614 if (iommu->iommu_ctxflush)
615 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
616
617 /* Step 1: Kick data out of streaming buffers if necessary. */
618 if (strbuf->strbuf_enabled) {
619 u32 vaddr = bus_addr;
620
621 PCI_STC_FLUSHFLAG_INIT(strbuf);
622 if (strbuf->strbuf_ctxflush &&
623 iommu->iommu_ctxflush) {
624 unsigned long matchreg, flushreg;
625
626 flushreg = strbuf->strbuf_ctxflush;
627 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
628 do {
629 pci_iommu_write(flushreg, ctx);
630 } while(((long)pci_iommu_read(matchreg)) < 0L);
631 } else {
632 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
633 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
634 }
635
636 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
637 (void) pci_iommu_read(iommu->write_complete_reg);
638 while (!PCI_STC_FLUSHFLAG_SET(strbuf))
639 membar("#LoadLoad");
640 }
641
642 /* Step 2: Clear out first TSB entry. */
643 iopte_val(*base) = IOPTE_INVALID;
644
645 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
646 npages, ctx);
647
648 spin_unlock_irqrestore(&iommu->lock, flags);
649 }
650
651 /* Make physical memory consistent for a single
652 * streaming mode DMA translation after a transfer.
653 */
654 void pci_dma_sync_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
655 {
656 struct pcidev_cookie *pcp;
657 struct pci_iommu *iommu;
658 struct pci_strbuf *strbuf;
659 unsigned long flags, ctx, npages;
660
661 pcp = pdev->sysdata;
662 iommu = pcp->pbm->iommu;
663 strbuf = &pcp->pbm->stc;
664
665 if (!strbuf->strbuf_enabled)
666 return;
667
668 spin_lock_irqsave(&iommu->lock, flags);
669
670 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
671 npages >>= IO_PAGE_SHIFT;
672 bus_addr &= IO_PAGE_MASK;
673
674 /* Step 1: Record the context, if any. */
675 ctx = 0;
676 if (iommu->iommu_ctxflush &&
677 strbuf->strbuf_ctxflush) {
678 iopte_t *iopte;
679
680 iopte = iommu->page_table +
681 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
682 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
683 }
684
685 /* Step 2: Kick data out of streaming buffers. */
686 PCI_STC_FLUSHFLAG_INIT(strbuf);
687 if (iommu->iommu_ctxflush &&
688 strbuf->strbuf_ctxflush) {
689 unsigned long matchreg, flushreg;
690
691 flushreg = strbuf->strbuf_ctxflush;
692 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
693 do {
694 pci_iommu_write(flushreg, ctx);
695 } while(((long)pci_iommu_read(matchreg)) < 0L);
696 } else {
697 unsigned long i;
698
699 for (i = 0; i < npages; i++, bus_addr += IO_PAGE_SIZE)
700 pci_iommu_write(strbuf->strbuf_pflush, bus_addr);
701 }
702
703 /* Step 3: Perform flush synchronization sequence. */
704 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
705 (void) pci_iommu_read(iommu->write_complete_reg);
706 while (!PCI_STC_FLUSHFLAG_SET(strbuf))
707 membar("#LoadLoad");
708
709 spin_unlock_irqrestore(&iommu->lock, flags);
710 }
711
712 /* Make physical memory consistent for a set of streaming
713 * mode DMA translations after a transfer.
714 */
715 void pci_dma_sync_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
716 {
717 struct pcidev_cookie *pcp;
718 struct pci_iommu *iommu;
719 struct pci_strbuf *strbuf;
720 unsigned long flags, ctx;
721
722 pcp = pdev->sysdata;
723 iommu = pcp->pbm->iommu;
724 strbuf = &pcp->pbm->stc;
725
726 if (!strbuf->strbuf_enabled)
727 return;
728
729 spin_lock_irqsave(&iommu->lock, flags);
730
731 /* Step 1: Record the context, if any. */
732 ctx = 0;
733 if (iommu->iommu_ctxflush &&
734 strbuf->strbuf_ctxflush) {
735 iopte_t *iopte;
736
737 iopte = iommu->page_table +
738 ((sglist[0].dvma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
739 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
740 }
741
742 /* Step 2: Kick data out of streaming buffers. */
743 PCI_STC_FLUSHFLAG_INIT(strbuf);
744 if (iommu->iommu_ctxflush &&
745 strbuf->strbuf_ctxflush) {
746 unsigned long matchreg, flushreg;
747
748 flushreg = strbuf->strbuf_ctxflush;
749 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
750 do {
751 pci_iommu_write(flushreg, ctx);
752 } while (((long)pci_iommu_read(matchreg)) < 0L);
753 } else {
754 unsigned long i, npages;
755 u32 bus_addr;
756
757 bus_addr = sglist[0].dvma_address & IO_PAGE_MASK;
758
759 for(i = 1; i < nelems; i++)
760 if (!sglist[i].dvma_length)
761 break;
762 i--;
763 npages = (IO_PAGE_ALIGN(sglist[i].dvma_address + sglist[i].dvma_length) - bus_addr) >> IO_PAGE_SHIFT;
764 for (i = 0; i < npages; i++, bus_addr += IO_PAGE_SIZE)
765 pci_iommu_write(strbuf->strbuf_pflush, bus_addr);
766 }
767
768 /* Step 3: Perform flush synchronization sequence. */
769 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
770 (void) pci_iommu_read(iommu->write_complete_reg);
771 while (!PCI_STC_FLUSHFLAG_SET(strbuf))
772 membar("#LoadLoad");
773
774 spin_unlock_irqrestore(&iommu->lock, flags);
775 }
776
777 int pci_dma_supported(struct pci_dev *pdev, dma_addr_t device_mask)
778 {
779 struct pcidev_cookie *pcp = pdev->sysdata;
780 u32 dma_addr_mask;
781
782 if (pdev == NULL) {
783 dma_addr_mask = 0xffffffff;
784 } else {
785 struct pci_iommu *iommu = pcp->pbm->iommu;
786
787 dma_addr_mask = iommu->dma_addr_mask;
788 }
789
790 return (device_mask & dma_addr_mask) == dma_addr_mask;
791 }
792