File: /usr/src/linux/arch/sparc64/kernel/pci_schizo.c
1 /* $Id: pci_schizo.c,v 1.21 2001/08/24 19:36:58 kanoj Exp $
2 * pci_schizo.c: SCHIZO specific PCI controller support.
3 *
4 * Copyright (C) 2001 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12
13 #include <asm/pbm.h>
14 #include <asm/iommu.h>
15 #include <asm/irq.h>
16 #include <asm/upa.h>
17
18 #include "pci_impl.h"
19 #include "iommu_common.h"
20
21 /* All SCHIZO registers are 64-bits. The following accessor
22 * routines are how they are accessed. The REG parameter
23 * is a physical address.
24 */
25 #define schizo_read(__reg) \
26 ({ u64 __ret; \
27 __asm__ __volatile__("ldxa [%1] %2, %0" \
28 : "=r" (__ret) \
29 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
30 : "memory"); \
31 __ret; \
32 })
33 #define schizo_write(__reg, __val) \
34 __asm__ __volatile__("stxa %0, [%1] %2" \
35 : /* no outputs */ \
36 : "r" (__val), "r" (__reg), \
37 "i" (ASI_PHYS_BYPASS_EC_E))
38
39 /* This is a convention that at least Excalibur and Merlin
40 * follow. I suppose the SCHIZO used in Starcat and friends
41 * will do similar.
42 *
43 * The only way I could see this changing is if the newlink
44 * block requires more space in Schizo's address space than
45 * they predicted, thus requiring an address space reorg when
46 * the newer Schizo is taped out.
47 *
48 * These offsets look weird because I keep in p->controller_regs
49 * the second PROM register property minus 0x10000 which is the
50 * base of the Safari and UPA64S registers of SCHIZO.
51 */
52 #define SCHIZO_PBM_A_REGS_OFF (0x600000UL - 0x400000UL)
53 #define SCHIZO_PBM_B_REGS_OFF (0x700000UL - 0x400000UL)
54
55 /* Streaming buffer control register. */
56 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
57 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
58 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
59 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
60 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
61
62 /* IOMMU control register. */
63 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000 /* Reserved */
64 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000 /* Translation Error Status */
65 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000 /* Translation Error encountered */
66 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000 /* Enable translation locking */
67 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000 /* Translation lock pointer */
68 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000 /* TSB Size */
69 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000 /* TSB Table 1024 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000 /* TSB Table 2048 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000 /* TSB Table 4096 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000 /* TSB Table 8192 8-byte entries */
73 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000 /* TSB Table 16k 8-byte entries */
74 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000 /* TSB Table 32k 8-byte entries */
75 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000 /* TSB Table 64k 8-byte entries */
76 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000 /* TSB Table 128k 8-byte entries */
77 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8 /* Reserved */
78 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004 /* Assumed page size, 0=8k 1=64k */
79 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002 /* Diagnostic mode enable */
80 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001 /* IOMMU Enable */
81
82 /* Schizo config space address format is nearly identical to
83 * that of PSYCHO:
84 *
85 * 32 24 23 16 15 11 10 8 7 2 1 0
86 * ---------------------------------------------------------
87 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
88 * ---------------------------------------------------------
89 */
90 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
91 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
92 (((unsigned long)(BUS) << 16) | \
93 ((unsigned long)(DEVFN) << 8) | \
94 ((unsigned long)(REG)))
95
96 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
97 unsigned char bus,
98 unsigned int devfn,
99 int where)
100 {
101 if (!pbm)
102 return NULL;
103 return (void *)
104 (SCHIZO_CONFIG_BASE(pbm) |
105 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
106 }
107
108 /* 4 slots on pbm A, and 6 slots on pbm B. In both cases
109 * slot 0 is the SCHIZO host bridge itself.
110 */
111 static int schizo_out_of_range(struct pci_pbm_info *pbm,
112 unsigned char bus,
113 unsigned char devfn)
114 {
115 return ((pbm->parent == 0) ||
116 ((pbm == &pbm->parent->pbm_B) &&
117 (bus == pbm->pci_first_busno) &&
118 PCI_SLOT(devfn) > 6) ||
119 ((pbm == &pbm->parent->pbm_A) &&
120 (bus == pbm->pci_first_busno) &&
121 PCI_SLOT(devfn) > 4));
122 }
123
124 /* SCHIZO PCI configuration space accessors. */
125
126 static int schizo_read_byte(struct pci_dev *dev, int where, u8 *value)
127 {
128 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
129 unsigned char bus = dev->bus->number;
130 unsigned int devfn = dev->devfn;
131 u8 *addr;
132
133 *value = 0xff;
134 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
135 if (!addr)
136 return PCIBIOS_SUCCESSFUL;
137
138 if (schizo_out_of_range(pbm, bus, devfn))
139 return PCIBIOS_SUCCESSFUL;
140 pci_config_read8(addr, value);
141 return PCIBIOS_SUCCESSFUL;
142 }
143
144 static int schizo_read_word(struct pci_dev *dev, int where, u16 *value)
145 {
146 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
147 unsigned char bus = dev->bus->number;
148 unsigned int devfn = dev->devfn;
149 u16 *addr;
150
151 *value = 0xffff;
152 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
153 if (!addr)
154 return PCIBIOS_SUCCESSFUL;
155
156 if (schizo_out_of_range(pbm, bus, devfn))
157 return PCIBIOS_SUCCESSFUL;
158
159 if (where & 0x01) {
160 printk("pcibios_read_config_word: misaligned reg [%x]\n",
161 where);
162 return PCIBIOS_SUCCESSFUL;
163 }
164 pci_config_read16(addr, value);
165 return PCIBIOS_SUCCESSFUL;
166 }
167
168 static int schizo_read_dword(struct pci_dev *dev, int where, u32 *value)
169 {
170 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
171 unsigned char bus = dev->bus->number;
172 unsigned int devfn = dev->devfn;
173 u32 *addr;
174
175 *value = 0xffffffff;
176 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
177 if (!addr)
178 return PCIBIOS_SUCCESSFUL;
179
180 if (schizo_out_of_range(pbm, bus, devfn))
181 return PCIBIOS_SUCCESSFUL;
182
183 if (where & 0x03) {
184 printk("pcibios_read_config_dword: misaligned reg [%x]\n",
185 where);
186 return PCIBIOS_SUCCESSFUL;
187 }
188
189 pci_config_read32(addr, value);
190 return PCIBIOS_SUCCESSFUL;
191 }
192
193 static int schizo_write_byte(struct pci_dev *dev, int where, u8 value)
194 {
195 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
196 unsigned char bus = dev->bus->number;
197 unsigned int devfn = dev->devfn;
198 u8 *addr;
199
200 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
201 if (!addr)
202 return PCIBIOS_SUCCESSFUL;
203
204 if (schizo_out_of_range(pbm, bus, devfn))
205 return PCIBIOS_SUCCESSFUL;
206
207 pci_config_write8(addr, value);
208 return PCIBIOS_SUCCESSFUL;
209 }
210
211 static int schizo_write_word(struct pci_dev *dev, int where, u16 value)
212 {
213 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
214 unsigned char bus = dev->bus->number;
215 unsigned int devfn = dev->devfn;
216 u16 *addr;
217
218 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
219 if (!addr)
220 return PCIBIOS_SUCCESSFUL;
221
222 if (schizo_out_of_range(pbm, bus, devfn))
223 return PCIBIOS_SUCCESSFUL;
224
225 if (where & 0x01) {
226 printk("pcibios_write_config_word: misaligned reg [%x]\n",
227 where);
228 return PCIBIOS_SUCCESSFUL;
229 }
230 pci_config_write16(addr, value);
231 return PCIBIOS_SUCCESSFUL;
232 }
233
234 static int schizo_write_dword(struct pci_dev *dev, int where, u32 value)
235 {
236 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
237 unsigned char bus = dev->bus->number;
238 unsigned int devfn = dev->devfn;
239 u32 *addr;
240
241 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
242 if (!addr)
243 return PCIBIOS_SUCCESSFUL;
244
245 if (schizo_out_of_range(pbm, bus, devfn))
246 return PCIBIOS_SUCCESSFUL;
247
248 if (where & 0x03) {
249 printk("pcibios_write_config_dword: misaligned reg [%x]\n",
250 where);
251 return PCIBIOS_SUCCESSFUL;
252 }
253 pci_config_write32(addr, value);
254 return PCIBIOS_SUCCESSFUL;
255 }
256
257 static struct pci_ops schizo_ops = {
258 schizo_read_byte,
259 schizo_read_word,
260 schizo_read_dword,
261 schizo_write_byte,
262 schizo_write_word,
263 schizo_write_dword
264 };
265
266 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
267 * imap/iclr registers are per-PBM.
268 */
269 #define SCHIZO_IMAP_BASE 0x1000UL
270 #define SCHIZO_ICLR_BASE 0x1400UL
271
272 static unsigned long schizo_imap_offset(unsigned long ino)
273 {
274 return SCHIZO_IMAP_BASE + (ino * 8UL);
275 }
276
277 static unsigned long schizo_iclr_offset(unsigned long ino)
278 {
279 return SCHIZO_ICLR_BASE + (ino * 8UL);
280 }
281
282 /* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
283 * INOs which will not have an associated PCI device struct, ie. onboard
284 * EBUS devices and PCI controller internal error interrupts.
285 */
286 static unsigned char schizo_pil_table[] = {
287 /*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
288 /*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
289 /*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
290 /*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
291 /*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
292 /*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
293 /*0x18*/3, /* SCSI */
294 /*0x19*/3, /* second SCSI */
295 /*0x1a*/0, /* UNKNOWN */
296 /*0x1b*/0, /* UNKNOWN */
297 /*0x1c*/8, /* Parallel */
298 /*0x1d*/5, /* Ethernet */
299 /*0x1e*/8, /* Firewire-1394 */
300 /*0x1f*/9, /* USB */
301 /*0x20*/13, /* Audio Record */
302 /*0x21*/14, /* Audio Playback */
303 /*0x22*/12, /* Serial */
304 /*0x23*/2, /* EBUS I2C */
305 /*0x24*/10, /* RTC Clock */
306 /*0x25*/11, /* Floppy */
307 /*0x26*/0, /* UNKNOWN */
308 /*0x27*/0, /* UNKNOWN */
309 /*0x28*/0, /* UNKNOWN */
310 /*0x29*/0, /* UNKNOWN */
311 /*0x2a*/10, /* UPA 1 */
312 /*0x2b*/10, /* UPA 2 */
313 /*0x2c*/0, /* UNKNOWN */
314 /*0x2d*/0, /* UNKNOWN */
315 /*0x2e*/0, /* UNKNOWN */
316 /*0x2f*/0, /* UNKNOWN */
317 /*0x30*/15, /* Uncorrectable ECC */
318 /*0x31*/15, /* Correctable ECC */
319 /*0x32*/15, /* PCI Bus A Error */
320 /*0x33*/15, /* PCI Bus B Error */
321 /*0x34*/15, /* Safari Bus Error */
322 /*0x35*/0, /* Reserved */
323 /*0x36*/0, /* Reserved */
324 /*0x37*/0, /* Reserved */
325 /*0x38*/0, /* Reserved for NewLink */
326 /*0x39*/0, /* Reserved for NewLink */
327 /*0x3a*/0, /* Reserved for NewLink */
328 /*0x3b*/0, /* Reserved for NewLink */
329 /*0x3c*/0, /* Reserved for NewLink */
330 /*0x3d*/0, /* Reserved for NewLink */
331 /*0x3e*/0, /* Reserved for NewLink */
332 /*0x3f*/0, /* Reserved for NewLink */
333 };
334
335 static int __init schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
336 {
337 int ret;
338
339 ret = schizo_pil_table[ino];
340 if (ret == 0 && pdev == NULL) {
341 ret = 1;
342 } else if (ret == 0) {
343 switch ((pdev->class >> 16) & 0xff) {
344 case PCI_BASE_CLASS_STORAGE:
345 ret = 4;
346 break;
347
348 case PCI_BASE_CLASS_NETWORK:
349 ret = 6;
350 break;
351
352 case PCI_BASE_CLASS_DISPLAY:
353 ret = 9;
354 break;
355
356 case PCI_BASE_CLASS_MULTIMEDIA:
357 case PCI_BASE_CLASS_MEMORY:
358 case PCI_BASE_CLASS_BRIDGE:
359 ret = 10;
360 break;
361
362 default:
363 ret = 1;
364 break;
365 };
366 }
367
368 return ret;
369 }
370
371 static unsigned int __init schizo_irq_build(struct pci_pbm_info *pbm,
372 struct pci_dev *pdev,
373 unsigned int ino)
374 {
375 struct pci_controller_info *p = pbm->parent;
376 struct ino_bucket *bucket;
377 unsigned long imap, iclr, pbm_off;
378 unsigned long imap_off, iclr_off;
379 int pil, inofixup = 0;
380
381 if (pbm == &p->pbm_A)
382 pbm_off = SCHIZO_PBM_A_REGS_OFF;
383 else
384 pbm_off = SCHIZO_PBM_B_REGS_OFF;
385
386 ino &= PCI_IRQ_INO;
387 imap_off = schizo_imap_offset(ino);
388
389 /* Now build the IRQ bucket. */
390 pil = schizo_ino_to_pil(pdev, ino);
391 imap = p->controller_regs + pbm_off + imap_off;
392 imap += 4;
393
394 iclr_off = schizo_iclr_offset(ino);
395 iclr = p->controller_regs + pbm_off + iclr_off;
396 iclr += 4;
397
398 if (ino < 0x18)
399 inofixup = ino & 0x03;
400
401 bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
402 bucket->flags |= IBF_PCI;
403
404 return __irq(bucket);
405 }
406
407 /* SCHIZO error handling support. */
408 enum schizo_error_type {
409 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
410 };
411
412 static spinlock_t stc_buf_lock = SPIN_LOCK_UNLOCKED;
413 static unsigned long stc_error_buf[128];
414 static unsigned long stc_tag_buf[16];
415 static unsigned long stc_line_buf[16];
416
417 static void schizo_clear_other_err_intr(int irq)
418 {
419 struct ino_bucket *bucket = __bucket(irq);
420 unsigned long iclr = bucket->iclr;
421
422 iclr += (SCHIZO_PBM_B_REGS_OFF - SCHIZO_PBM_A_REGS_OFF);
423 upa_writel(ICLR_IDLE, iclr);
424 }
425
426 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
427 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
428 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
429
430 #define SCHIZO_STCERR_WRITE 0x2UL
431 #define SCHIZO_STCERR_READ 0x1UL
432
433 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
434 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
435 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
436 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
437
438 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
439 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
440 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
441 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
442 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
443 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
444
445 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
446 enum schizo_error_type type)
447 {
448 struct pci_controller_info *p = pbm->parent;
449 struct pci_strbuf *strbuf = &pbm->stc;
450 unsigned long regbase = p->controller_regs;
451 unsigned long err_base, tag_base, line_base;
452 u64 control;
453 char pbm_name = (pbm == &p->pbm_A ? 'A' : 'B');
454 int i;
455
456 if (pbm == &p->pbm_A)
457 regbase += SCHIZO_PBM_A_REGS_OFF;
458 else
459 regbase += SCHIZO_PBM_B_REGS_OFF;
460
461 err_base = regbase + SCHIZO_STC_ERR;
462 tag_base = regbase + SCHIZO_STC_TAG;
463 line_base = regbase + SCHIZO_STC_LINE;
464
465 spin_lock(&stc_buf_lock);
466
467 /* This is __REALLY__ dangerous. When we put the
468 * streaming buffer into diagnostic mode to probe
469 * it's tags and error status, we _must_ clear all
470 * of the line tag valid bits before re-enabling
471 * the streaming buffer. If any dirty data lives
472 * in the STC when we do this, we will end up
473 * invalidating it before it has a chance to reach
474 * main memory.
475 */
476 control = schizo_read(strbuf->strbuf_control);
477 schizo_write(strbuf->strbuf_control,
478 (control | SCHIZO_STRBUF_CTRL_DENAB));
479 for (i = 0; i < 128; i++) {
480 unsigned long val;
481
482 val = schizo_read(err_base + (i * 8UL));
483 schizo_write(err_base + (i * 8UL), 0UL);
484 stc_error_buf[i] = val;
485 }
486 for (i = 0; i < 16; i++) {
487 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
488 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
489 schizo_write(tag_base + (i * 8UL), 0UL);
490 schizo_write(line_base + (i * 8UL), 0UL);
491 }
492
493 /* OK, state is logged, exit diagnostic mode. */
494 schizo_write(strbuf->strbuf_control, control);
495
496 for (i = 0; i < 16; i++) {
497 int j, saw_error, first, last;
498
499 saw_error = 0;
500 first = i * 8;
501 last = first + 8;
502 for (j = first; j < last; j++) {
503 unsigned long errval = stc_error_buf[j];
504 if (errval != 0) {
505 saw_error++;
506 printk("SCHIZO%d: PBM-%c STC_ERR(%d)[wr(%d)rd(%d)]\n",
507 p->index, pbm_name,
508 j,
509 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
510 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
511 }
512 }
513 if (saw_error != 0) {
514 unsigned long tagval = stc_tag_buf[i];
515 unsigned long lineval = stc_line_buf[i];
516 printk("SCHIZO%d: PBM-%c STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
517 p->index, pbm_name,
518 i,
519 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
520 (tagval & SCHIZO_STCTAG_VPN),
521 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
522 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
523
524 /* XXX Should spit out per-bank error information... -DaveM */
525 printk("SCHIZO%d: PBM-%c STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
526 "V(%d)FOFN(%d)]\n",
527 p->index, pbm_name,
528 i,
529 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
530 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
531 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
532 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
533 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
534 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
535 }
536 }
537
538 spin_unlock(&stc_buf_lock);
539 }
540
541 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
542 * controller level errors.
543 */
544
545 #define SCHIZO_IOMMU_TAG 0xa580UL
546 #define SCHIZO_IOMMU_DATA 0xa600UL
547
548 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
549 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
550 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
551 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
552 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
553 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
554 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
555
556 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
557 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
558 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
559
560 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
561 enum schizo_error_type type)
562 {
563 struct pci_controller_info *p = pbm->parent;
564 struct pci_iommu *iommu = pbm->iommu;
565 unsigned long iommu_tag[16];
566 unsigned long iommu_data[16];
567 unsigned long flags;
568 u64 control;
569 char pbm_name = (pbm == &p->pbm_A ? 'A' : 'B');
570 int i;
571
572 spin_lock_irqsave(&iommu->lock, flags);
573 control = schizo_read(iommu->iommu_control);
574 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
575 unsigned long base;
576 char *type_string;
577
578 /* Clear the error encountered bit. */
579 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
580 schizo_write(iommu->iommu_control, control);
581
582 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
583 case 0:
584 type_string = "Protection Error";
585 break;
586 case 1:
587 type_string = "Invalid Error";
588 break;
589 case 2:
590 type_string = "TimeOut Error";
591 break;
592 case 3:
593 default:
594 type_string = "ECC Error";
595 break;
596 };
597 printk("SCHIZO%d: PBM-%c IOMMU Error, type[%s]\n",
598 p->index, pbm_name, type_string);
599
600 /* Put the IOMMU into diagnostic mode and probe
601 * it's TLB for entries with error status.
602 *
603 * It is very possible for another DVMA to occur
604 * while we do this probe, and corrupt the system
605 * further. But we are so screwed at this point
606 * that we are likely to crash hard anyways, so
607 * get as much diagnostic information to the
608 * console as we can.
609 */
610 schizo_write(iommu->iommu_control,
611 control | SCHIZO_IOMMU_CTRL_DENAB);
612
613 base = p->controller_regs;
614 if (pbm == &p->pbm_A)
615 base += SCHIZO_PBM_A_REGS_OFF;
616 else
617 base += SCHIZO_PBM_B_REGS_OFF;
618
619 for (i = 0; i < 16; i++) {
620 iommu_tag[i] =
621 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
622 iommu_data[i] =
623 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
624
625 /* Now clear out the entry. */
626 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
627 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
628 }
629
630 /* Leave diagnostic mode. */
631 schizo_write(iommu->iommu_control, control);
632
633 for (i = 0; i < 16; i++) {
634 unsigned long tag, data;
635
636 tag = iommu_tag[i];
637 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
638 continue;
639
640 data = iommu_data[i];
641 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
642 case 0:
643 type_string = "Protection Error";
644 break;
645 case 1:
646 type_string = "Invalid Error";
647 break;
648 case 2:
649 type_string = "TimeOut Error";
650 break;
651 case 3:
652 default:
653 type_string = "ECC Error";
654 break;
655 };
656 printk("SCHIZO%d: PBM-%c IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
657 "sz(%dK) vpg(%08lx)]\n",
658 p->index, pbm_name, i, type_string,
659 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
660 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
661 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
662 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
663 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
664 printk("SCHIZO%d: PBM-%c IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
665 p->index, pbm_name, i,
666 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
667 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
668 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
669 }
670 }
671 __schizo_check_stc_error_pbm(pbm, type);
672 spin_unlock_irqrestore(&iommu->lock, flags);
673 }
674
675 static void schizo_check_iommu_error(struct pci_controller_info *p,
676 enum schizo_error_type type)
677 {
678 schizo_check_iommu_error_pbm(&p->pbm_A, type);
679 schizo_check_iommu_error_pbm(&p->pbm_B, type);
680 }
681
682 /* Uncorrectable ECC error status gathering. */
683 #define SCHIZO_UE_AFSR 0x10030UL
684 #define SCHIZO_UE_AFAR 0x10038UL
685
686 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL
687 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL
688 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL
689 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL
690 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL
691 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL
692 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL
693 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL
694 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL
695 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL
696 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL
697 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL
698 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL
699 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL
700
701 static void schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
702 {
703 struct pci_controller_info *p = dev_id;
704 unsigned long afsr_reg = p->controller_regs + SCHIZO_UE_AFSR;
705 unsigned long afar_reg = p->controller_regs + SCHIZO_UE_AFAR;
706 unsigned long afsr, afar, error_bits;
707 int reported, limit;
708
709 /* Latch uncorrectable error status. */
710 afar = schizo_read(afar_reg);
711
712 /* If either of the error pending bits are set in the
713 * AFSR, the error status is being actively updated by
714 * the hardware and we must re-read to get a clean value.
715 */
716 limit = 1000;
717 do {
718 afsr = schizo_read(afsr_reg);
719 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
720
721 /* Clear the primary/secondary error status bits. */
722 error_bits = afsr &
723 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
724 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
725 if (!error_bits)
726 return;
727 schizo_write(afsr_reg, error_bits);
728
729 /* Log the error. */
730 printk("SCHIZO%d: Uncorrectable Error, primary error type[%s]\n",
731 p->index,
732 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
733 "PIO" :
734 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
735 "DMA Read" :
736 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
737 "DMA Write" : "???")))));
738 printk("SCHIZO%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
739 p->index,
740 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
741 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
742 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
743 printk("SCHIZO%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
744 p->index,
745 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
746 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
747 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
748 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
749 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
750 printk("SCHIZO%d: UE AFAR [%016lx]\n", p->index, afar);
751 printk("SCHIZO%d: UE Secondary errors [", p->index);
752 reported = 0;
753 if (afsr & SCHIZO_UEAFSR_SPIO) {
754 reported++;
755 printk("(PIO)");
756 }
757 if (afsr & SCHIZO_UEAFSR_SDMA) {
758 reported++;
759 printk("(DMA)");
760 }
761 if (!reported)
762 printk("(none)");
763 printk("]\n");
764
765 /* Interrogate IOMMU for error status. */
766 schizo_check_iommu_error(p, UE_ERR);
767
768 schizo_clear_other_err_intr(irq);
769 }
770
771 #define SCHIZO_CE_AFSR 0x10040UL
772 #define SCHIZO_CE_AFAR 0x10048UL
773
774 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
775 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
776 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
777 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
778 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
779 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
780 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
781 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
782 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
783 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
784 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
785 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
786 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
787 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
788
789 static void schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
790 {
791 struct pci_controller_info *p = dev_id;
792 unsigned long afsr_reg = p->controller_regs + SCHIZO_CE_AFSR;
793 unsigned long afar_reg = p->controller_regs + SCHIZO_CE_AFAR;
794 unsigned long afsr, afar, error_bits;
795 int reported, limit;
796
797 /* Latch error status. */
798 afar = schizo_read(afar_reg);
799
800 /* If either of the error pending bits are set in the
801 * AFSR, the error status is being actively updated by
802 * the hardware and we must re-read to get a clean value.
803 */
804 limit = 1000;
805 do {
806 afsr = schizo_read(afsr_reg);
807 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
808
809 /* Clear primary/secondary error status bits. */
810 error_bits = afsr &
811 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
812 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
813 if (!error_bits)
814 return;
815 schizo_write(afsr_reg, error_bits);
816
817 /* Log the error. */
818 printk("SCHIZO%d: Correctable Error, primary error type[%s]\n",
819 p->index,
820 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
821 "PIO" :
822 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
823 "DMA Read" :
824 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
825 "DMA Write" : "???")))));
826
827 /* XXX Use syndrome and afar to print out module string just like
828 * XXX UDB CE trap handler does... -DaveM
829 */
830 printk("SCHIZO%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
831 p->index,
832 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
833 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
834 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
835 printk("SCHIZO%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
836 p->index,
837 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
838 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
839 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
840 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
841 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
842 printk("SCHIZO%d: CE AFAR [%016lx]\n", p->index, afar);
843 printk("SCHIZO%d: CE Secondary errors [", p->index);
844 reported = 0;
845 if (afsr & SCHIZO_CEAFSR_SPIO) {
846 reported++;
847 printk("(PIO)");
848 }
849 if (afsr & SCHIZO_CEAFSR_SDMA) {
850 reported++;
851 printk("(DMA)");
852 }
853 if (!reported)
854 printk("(none)");
855 printk("]\n");
856
857 schizo_clear_other_err_intr(irq);
858 }
859
860 #define SCHIZO_PCI_AFSR 0x2010UL
861 #define SCHIZO_PCI_AFAR 0x2018UL
862
863 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL
864 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL
865 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL
866 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL
867 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL
868 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL
869 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL
870 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL
871 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL
872 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL
873 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL
874 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL
875 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL
876 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL
877 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL
878 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL
879 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL
880
881 static void schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
882 {
883 struct pci_pbm_info *pbm = dev_id;
884 struct pci_controller_info *p = pbm->parent;
885 unsigned long afsr_reg, afar_reg, base;
886 unsigned long afsr, afar, error_bits;
887 int reported;
888 char pbm_name;
889
890 base = p->controller_regs;
891 if (pbm == &pbm->parent->pbm_A) {
892 base += SCHIZO_PBM_A_REGS_OFF;
893 pbm_name = 'A';
894 } else {
895 base += SCHIZO_PBM_B_REGS_OFF;
896 pbm_name = 'B';
897 }
898
899 afsr_reg = base + SCHIZO_PCI_AFSR;
900 afar_reg = base + SCHIZO_PCI_AFAR;
901
902 /* Latch error status. */
903 afar = schizo_read(afar_reg);
904 afsr = schizo_read(afsr_reg);
905
906 /* Clear primary/secondary error status bits. */
907 error_bits = afsr &
908 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
909 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
910 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
911 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
912 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
913 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
914 if (!error_bits)
915 return;
916 schizo_write(afsr_reg, error_bits);
917
918 /* Log the error. */
919 printk("SCHIZO%d: PBM-%c PCI Error, primary error type[%s]\n",
920 p->index, pbm_name,
921 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
922 "Master Abort" :
923 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
924 "Target Abort" :
925 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
926 "Excessive Retries" :
927 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
928 "Parity Error" :
929 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
930 "Timeout" :
931 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
932 "Bus Unusable" : "???"))))))));
933 printk("SCHIZO%d: PBM-%c bytemask[%04lx] was_block(%d) space(%s)\n",
934 p->index, pbm_name,
935 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
936 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
937 ((afsr & SCHIZO_PCIAFSR_CFG) ?
938 "Config" :
939 ((afsr & SCHIZO_PCIAFSR_MEM) ?
940 "Memory" :
941 ((afsr & SCHIZO_PCIAFSR_IO) ?
942 "I/O" : "???"))));
943 printk("SCHIZO%d: PBM-%c PCI AFAR [%016lx]\n",
944 p->index, pbm_name, afar);
945 printk("SCHIZO%d: PBM-%c PCI Secondary errors [",
946 p->index, pbm_name);
947 reported = 0;
948 if (afsr & SCHIZO_PCIAFSR_SMA) {
949 reported++;
950 printk("(Master Abort)");
951 }
952 if (afsr & SCHIZO_PCIAFSR_STA) {
953 reported++;
954 printk("(Target Abort)");
955 }
956 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
957 reported++;
958 printk("(Excessive Retries)");
959 }
960 if (afsr & SCHIZO_PCIAFSR_SPERR) {
961 reported++;
962 printk("(Parity Error)");
963 }
964 if (afsr & SCHIZO_PCIAFSR_STTO) {
965 reported++;
966 printk("(Timeout)");
967 }
968 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
969 reported++;
970 printk("(Bus Unusable)");
971 }
972 if (!reported)
973 printk("(none)");
974 printk("]\n");
975
976 /* For the error types shown, scan PBM's PCI bus for devices
977 * which have logged that error type.
978 */
979
980 /* If we see a Target Abort, this could be the result of an
981 * IOMMU translation error of some sort. It is extremely
982 * useful to log this information as usually it indicates
983 * a bug in the IOMMU support code or a PCI device driver.
984 */
985 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
986 schizo_check_iommu_error(p, PCI_ERR);
987 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
988 }
989 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
990 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
991
992 /* For excessive retries, PSYCHO/PBM will abort the device
993 * and there is no way to specifically check for excessive
994 * retries in the config space status registers. So what
995 * we hope is that we'll catch it via the master/target
996 * abort events.
997 */
998
999 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
1000 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1001
1002 schizo_clear_other_err_intr(irq);
1003 }
1004
1005 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
1006
1007 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
1008
1009 #define SAFARI_ERROR_BADCMD 0x4000000000000000UL
1010 #define SAFARI_ERROR_SSMDIS 0x2000000000000000UL
1011 #define SAFARI_ERROR_BADMA 0x1000000000000000UL
1012 #define SAFARI_ERROR_BADMB 0x0800000000000000UL
1013 #define SAFARI_ERROR_BADMC 0x0400000000000000UL
1014 #define SAFARI_ERROR_CPU1PS 0x0000000000002000UL
1015 #define SAFARI_ERROR_CPU1PB 0x0000000000001000UL
1016 #define SAFARI_ERROR_CPU0PS 0x0000000000000800UL
1017 #define SAFARI_ERROR_CPU0PB 0x0000000000000400UL
1018 #define SAFARI_ERROR_CIQTO 0x0000000000000200UL
1019 #define SAFARI_ERROR_LPQTO 0x0000000000000100UL
1020 #define SAFARI_ERROR_SFPQTO 0x0000000000000080UL
1021 #define SAFARI_ERROR_UFPQTO 0x0000000000000040UL
1022 #define SAFARI_ERROR_APERR 0x0000000000000020UL
1023 #define SAFARI_ERROR_UNMAP 0x0000000000000010UL
1024 #define SAFARI_ERROR_BUSERR 0x0000000000000004UL
1025 #define SAFARI_ERROR_TIMEOUT 0x0000000000000002UL
1026 #define SAFARI_ERROR_ILL 0x0000000000000001UL
1027
1028 /* We only expect UNMAP errors here. The rest of the Safari errors
1029 * are marked fatal and thus cause a system reset.
1030 */
1031 static void schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs)
1032 {
1033 struct pci_controller_info *p = dev_id;
1034 u64 errlog;
1035
1036 errlog = schizo_read(p->controller_regs + SCHIZO_SAFARI_ERRLOG);
1037 schizo_write(p->controller_regs + SCHIZO_SAFARI_ERRLOG,
1038 errlog & ~(SAFARI_ERRLOG_ERROUT));
1039
1040 if (!(errlog & SAFARI_ERROR_UNMAP)) {
1041 printk("SCHIZO%d: Unexpected Safari error interrupt, errlog[%016lx]\n",
1042 p->index, errlog);
1043
1044 schizo_clear_other_err_intr(irq);
1045 return;
1046 }
1047
1048 printk("SCHIZO%d: Safari interrupt, UNMAPPED error, interrogating IOMMUs.\n",
1049 p->index);
1050 schizo_check_iommu_error(p, SAFARI_ERR);
1051
1052 schizo_clear_other_err_intr(irq);
1053 }
1054
1055 /* Nearly identical to PSYCHO equivalents... */
1056 #define SCHIZO_ECC_CTRL 0x10020UL
1057 #define SCHIZO_ECCCTRL_EE 0x8000000000000000 /* Enable ECC Checking */
1058 #define SCHIZO_ECCCTRL_UE 0x4000000000000000 /* Enable UE Interrupts */
1059 #define SCHIZO_ECCCTRL_CE 0x2000000000000000 /* Enable CE INterrupts */
1060
1061 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
1062 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
1063 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
1064 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
1065
1066 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
1067 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
1068 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
1069 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
1070 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
1071
1072 #define SCHIZO_PCIA_CTRL (SCHIZO_PBM_A_REGS_OFF + 0x2000UL)
1073 #define SCHIZO_PCIB_CTRL (SCHIZO_PBM_B_REGS_OFF + 0x2000UL)
1074 #define SCHIZO_PCICTRL_BUNUS (1UL << 63UL)
1075 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL)
1076 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL)
1077 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL)
1078 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL)
1079 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL)
1080 #define SCHIZO_PCICTRL_SERR (1UL << 34UL)
1081 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL)
1082 #define SCHIZO_PCICTRL_EEN (1UL << 17UL)
1083
1084 static void __init schizo_register_error_handlers(struct pci_controller_info *p)
1085 {
1086 struct pci_pbm_info *pbm_a = &p->pbm_A;
1087 struct pci_pbm_info *pbm_b = &p->pbm_B;
1088 unsigned long base = p->controller_regs;
1089 unsigned int irq, portid = p->portid;
1090 struct ino_bucket *bucket;
1091 u64 tmp;
1092
1093 /* Build IRQs and register handlers. */
1094 irq = schizo_irq_build(pbm_a, NULL, (portid << 6) | SCHIZO_UE_INO);
1095 if (request_irq(irq, schizo_ue_intr,
1096 SA_SHIRQ, "SCHIZO UE", p) < 0) {
1097 prom_printf("SCHIZO%d: Cannot register UE interrupt.\n",
1098 p->index);
1099 prom_halt();
1100 }
1101 bucket = __bucket(irq);
1102 tmp = readl(bucket->imap);
1103 upa_writel(tmp, (base + SCHIZO_PBM_B_REGS_OFF + schizo_imap_offset(SCHIZO_UE_INO) + 4));
1104
1105 irq = schizo_irq_build(pbm_a, NULL, (portid << 6) | SCHIZO_CE_INO);
1106 if (request_irq(irq, schizo_ce_intr,
1107 SA_SHIRQ, "SCHIZO CE", p) < 0) {
1108 prom_printf("SCHIZO%d: Cannot register CE interrupt.\n",
1109 p->index);
1110 prom_halt();
1111 }
1112 bucket = __bucket(irq);
1113 tmp = upa_readl(bucket->imap);
1114 upa_writel(tmp, (base + SCHIZO_PBM_B_REGS_OFF + schizo_imap_offset(SCHIZO_CE_INO) + 4));
1115
1116 irq = schizo_irq_build(pbm_a, NULL, (portid << 6) | SCHIZO_PCIERR_A_INO);
1117 if (request_irq(irq, schizo_pcierr_intr,
1118 SA_SHIRQ, "SCHIZO PCIERR", pbm_a) < 0) {
1119 prom_printf("SCHIZO%d(PBMA): Cannot register PciERR interrupt.\n",
1120 p->index);
1121 prom_halt();
1122 }
1123 bucket = __bucket(irq);
1124 tmp = upa_readl(bucket->imap);
1125 upa_writel(tmp, (base + SCHIZO_PBM_B_REGS_OFF + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1126
1127 irq = schizo_irq_build(pbm_a, NULL, (portid << 6) | SCHIZO_PCIERR_B_INO);
1128 if (request_irq(irq, schizo_pcierr_intr,
1129 SA_SHIRQ, "SCHIZO PCIERR", pbm_b) < 0) {
1130 prom_printf("SCHIZO%d(PBMB): Cannot register PciERR interrupt.\n",
1131 p->index);
1132 prom_halt();
1133 }
1134 bucket = __bucket(irq);
1135 tmp = upa_readl(bucket->imap);
1136 upa_writel(tmp, (base + SCHIZO_PBM_B_REGS_OFF + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1137
1138 irq = schizo_irq_build(pbm_a, NULL, (portid << 6) | SCHIZO_SERR_INO);
1139 if (request_irq(irq, schizo_safarierr_intr,
1140 SA_SHIRQ, "SCHIZO SERR", p) < 0) {
1141 prom_printf("SCHIZO%d(PBMB): Cannot register SafariERR interrupt.\n",
1142 p->index);
1143 prom_halt();
1144 }
1145 bucket = __bucket(irq);
1146 tmp = upa_readl(bucket->imap);
1147 upa_writel(tmp, (base + SCHIZO_PBM_B_REGS_OFF + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1148
1149 /* Enable UE and CE interrupts for controller. */
1150 schizo_write(base + SCHIZO_ECC_CTRL,
1151 (SCHIZO_ECCCTRL_EE |
1152 SCHIZO_ECCCTRL_UE |
1153 SCHIZO_ECCCTRL_CE));
1154
1155 /* Enable PCI Error interrupts and clear error
1156 * bits for each PBM.
1157 */
1158 tmp = schizo_read(base + SCHIZO_PCIA_CTRL);
1159 tmp |= (SCHIZO_PCICTRL_BUNUS |
1160 SCHIZO_PCICTRL_ESLCK |
1161 SCHIZO_PCICTRL_TTO_ERR |
1162 SCHIZO_PCICTRL_RTRY_ERR |
1163 SCHIZO_PCICTRL_DTO_ERR |
1164 SCHIZO_PCICTRL_SBH_ERR |
1165 SCHIZO_PCICTRL_SERR |
1166 SCHIZO_PCICTRL_SBH_INT |
1167 SCHIZO_PCICTRL_EEN);
1168 schizo_write(base + SCHIZO_PCIA_CTRL, tmp);
1169
1170 tmp = schizo_read(base + SCHIZO_PCIB_CTRL);
1171 tmp |= (SCHIZO_PCICTRL_BUNUS |
1172 SCHIZO_PCICTRL_ESLCK |
1173 SCHIZO_PCICTRL_TTO_ERR |
1174 SCHIZO_PCICTRL_RTRY_ERR |
1175 SCHIZO_PCICTRL_DTO_ERR |
1176 SCHIZO_PCICTRL_SBH_ERR |
1177 SCHIZO_PCICTRL_SERR |
1178 SCHIZO_PCICTRL_SBH_INT |
1179 SCHIZO_PCICTRL_EEN);
1180 schizo_write(base + SCHIZO_PCIB_CTRL, tmp);
1181
1182 schizo_write(base + SCHIZO_PBM_A_REGS_OFF + SCHIZO_PCI_AFSR,
1183 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1184 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1185 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1186 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1187 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1188 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1189 schizo_write(base + SCHIZO_PBM_B_REGS_OFF + SCHIZO_PCI_AFSR,
1190 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1191 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1192 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1193 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1194 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1195 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1196
1197 /* Make all Safari error conditions fatal except unmapped errors
1198 * which we make generate interrupts.
1199 */
1200 #if 1
1201 /* XXX Something wrong with some Excalibur systems
1202 * XXX Sun is shipping. The behavior on a 2-cpu
1203 * XXX machine is that both CPU1 parity error bits
1204 * XXX are set and are immediately set again when
1205 * XXX their error status bits are cleared. Just
1206 * XXX ignore them for now. -DaveM
1207 */
1208 schizo_write(base + SCHIZO_SAFARI_ERRCTRL,
1209 (SCHIZO_SAFERRCTRL_EN |
1210 (SAFARI_ERROR_BADCMD | SAFARI_ERROR_SSMDIS |
1211 SAFARI_ERROR_BADMA | SAFARI_ERROR_BADMB |
1212 SAFARI_ERROR_BADMC |
1213 SAFARI_ERROR_CIQTO |
1214 SAFARI_ERROR_LPQTO | SAFARI_ERROR_SFPQTO |
1215 SAFARI_ERROR_UFPQTO | SAFARI_ERROR_APERR |
1216 SAFARI_ERROR_BUSERR | SAFARI_ERROR_TIMEOUT |
1217 SAFARI_ERROR_ILL)));
1218 #else
1219 schizo_write(base + SCHIZO_SAFARI_ERRCTRL,
1220 (SCHIZO_SAFERRCTRL_EN |
1221 (SAFARI_ERROR_BADCMD | SAFARI_ERROR_SSMDIS |
1222 SAFARI_ERROR_BADMA | SAFARI_ERROR_BADMB |
1223 SAFARI_ERROR_BADMC |
1224 SAFARI_ERROR_CPU1PS | SAFARI_ERROR_CPU1PB |
1225 SAFARI_ERROR_CPU0PS | SAFARI_ERROR_CPU0PB |
1226 SAFARI_ERROR_CIQTO |
1227 SAFARI_ERROR_LPQTO | SAFARI_ERROR_SFPQTO |
1228 SAFARI_ERROR_UFPQTO | SAFARI_ERROR_APERR |
1229 SAFARI_ERROR_BUSERR | SAFARI_ERROR_TIMEOUT |
1230 SAFARI_ERROR_ILL)));
1231 #endif
1232
1233 schizo_write(base + SCHIZO_SAFARI_IRQCTRL,
1234 (SCHIZO_SAFIRQCTRL_EN | (SAFARI_ERROR_UNMAP)));
1235 }
1236
1237 /* We have to do the config space accesses by hand, thus... */
1238 #define PBM_BRIDGE_BUS 0x40
1239 #define PBM_BRIDGE_SUBORDINATE 0x41
1240 static void __init pbm_renumber(struct pci_pbm_info *pbm, u8 orig_busno)
1241 {
1242 u8 *addr, busno;
1243 int nbus;
1244
1245 busno = pci_highest_busnum;
1246 nbus = pbm->pci_last_busno - pbm->pci_first_busno;
1247
1248 addr = schizo_pci_config_mkaddr(pbm, orig_busno,
1249 0, PBM_BRIDGE_BUS);
1250 pci_config_write8(addr, busno);
1251 addr = schizo_pci_config_mkaddr(pbm, busno,
1252 0, PBM_BRIDGE_SUBORDINATE);
1253 pci_config_write8(addr, busno + nbus);
1254
1255 pbm->pci_first_busno = busno;
1256 pbm->pci_last_busno = busno + nbus;
1257 pci_highest_busnum = busno + nbus + 1;
1258
1259 do {
1260 pci_bus2pbm[busno++] = pbm;
1261 } while (nbus--);
1262 }
1263
1264 /* We have to do the config space accesses by hand here since
1265 * the pci_bus2pbm array is not ready yet.
1266 */
1267 static void __init pbm_pci_bridge_renumber(struct pci_pbm_info *pbm,
1268 u8 busno)
1269 {
1270 u32 devfn, l, class;
1271 u8 hdr_type;
1272 int is_multi = 0;
1273
1274 for(devfn = 0; devfn < 0xff; ++devfn) {
1275 u32 *dwaddr;
1276 u8 *baddr;
1277
1278 if (PCI_FUNC(devfn) != 0 && is_multi == 0)
1279 continue;
1280
1281 /* Anything there? */
1282 dwaddr = schizo_pci_config_mkaddr(pbm, busno, devfn, PCI_VENDOR_ID);
1283 l = 0xffffffff;
1284 pci_config_read32(dwaddr, &l);
1285 if (l == 0xffffffff || l == 0x00000000 ||
1286 l == 0x0000ffff || l == 0xffff0000) {
1287 is_multi = 0;
1288 continue;
1289 }
1290
1291 baddr = schizo_pci_config_mkaddr(pbm, busno, devfn, PCI_HEADER_TYPE);
1292 pci_config_read8(baddr, &hdr_type);
1293 if (PCI_FUNC(devfn) == 0)
1294 is_multi = hdr_type & 0x80;
1295
1296 dwaddr = schizo_pci_config_mkaddr(pbm, busno, devfn, PCI_CLASS_REVISION);
1297 class = 0xffffffff;
1298 pci_config_read32(dwaddr, &class);
1299 if ((class >> 16) == PCI_CLASS_BRIDGE_PCI) {
1300 u32 buses = 0xffffffff;
1301
1302 dwaddr = schizo_pci_config_mkaddr(pbm, busno, devfn,
1303 PCI_PRIMARY_BUS);
1304 pci_config_read32(dwaddr, &buses);
1305 pbm_pci_bridge_renumber(pbm, (buses >> 8) & 0xff);
1306 buses &= 0xff000000;
1307 pci_config_write32(dwaddr, buses);
1308 }
1309 }
1310 }
1311
1312 static void __init pbm_bridge_reconfigure(struct pci_controller_info *p)
1313 {
1314 struct pci_pbm_info *pbm;
1315 u8 *addr;
1316
1317 /* Clear out primary/secondary/subordinate bus numbers on
1318 * all PCI-to-PCI bridges under each PBM. The generic bus
1319 * probing will fix them up.
1320 */
1321 pbm_pci_bridge_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1322 pbm_pci_bridge_renumber(&p->pbm_A, p->pbm_A.pci_first_busno);
1323
1324 /* Move PBM A out of the way. */
1325 pbm = &p->pbm_A;
1326 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1327 0, PBM_BRIDGE_BUS);
1328 pci_config_write8(addr, 0xff);
1329 addr = schizo_pci_config_mkaddr(pbm, 0xff,
1330 0, PBM_BRIDGE_SUBORDINATE);
1331 pci_config_write8(addr, 0xff);
1332
1333 /* Now we can safely renumber both PBMs. */
1334 pbm_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1335 pbm_renumber(&p->pbm_A, 0xff);
1336 }
1337
1338 static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
1339 {
1340 u8 *addr;
1341
1342 /* Set cache-line size to 64 bytes, this is actually
1343 * a nop but I do it for completeness.
1344 */
1345 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1346 0, PCI_CACHE_LINE_SIZE);
1347 pci_config_write8(addr, 64 / sizeof(u32));
1348
1349 /* Set PBM latency timer to 64 PCI clocks. */
1350 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1351 0, PCI_LATENCY_TIMER);
1352 pci_config_write8(addr, 64);
1353 }
1354
1355 static void __init pbm_scan_bus(struct pci_controller_info *p,
1356 struct pci_pbm_info *pbm)
1357 {
1358 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
1359
1360 if (!cookie) {
1361 prom_printf("SCHIZO: Critical allocation failure.\n");
1362 prom_halt();
1363 }
1364
1365 /* All we care about is the PBM. */
1366 memset(cookie, 0, sizeof(*cookie));
1367 cookie->pbm = pbm;
1368
1369 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1370 p->pci_ops,
1371 pbm);
1372 pci_fixup_host_bridge_self(pbm->pci_bus);
1373 pbm->pci_bus->self->sysdata = cookie;
1374
1375 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1376 pci_record_assignments(pbm, pbm->pci_bus);
1377 pci_assign_unassigned(pbm, pbm->pci_bus);
1378 pci_fixup_irq(pbm, pbm->pci_bus);
1379 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1380 pci_setup_busmastering(pbm, pbm->pci_bus);
1381 }
1382
1383 static void __init schizo_scan_bus(struct pci_controller_info *p)
1384 {
1385 pbm_bridge_reconfigure(p);
1386 pbm_config_busmastering(&p->pbm_B);
1387 p->pbm_B.is_66mhz_capable = 0;
1388 pbm_config_busmastering(&p->pbm_A);
1389 p->pbm_A.is_66mhz_capable = 1;
1390 pbm_scan_bus(p, &p->pbm_B);
1391 pbm_scan_bus(p, &p->pbm_A);
1392
1393 /* After the PCI bus scan is complete, we can register
1394 * the error interrupt handlers.
1395 */
1396 schizo_register_error_handlers(p);
1397 }
1398
1399 static void __init schizo_base_address_update(struct pci_dev *pdev, int resource)
1400 {
1401 struct pcidev_cookie *pcp = pdev->sysdata;
1402 struct pci_pbm_info *pbm = pcp->pbm;
1403 struct resource *res, *root;
1404 u32 reg;
1405 int where, size, is_64bit;
1406
1407 res = &pdev->resource[resource];
1408 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1409
1410 is_64bit = 0;
1411 if (res->flags & IORESOURCE_IO)
1412 root = &pbm->io_space;
1413 else {
1414 root = &pbm->mem_space;
1415 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1416 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1417 is_64bit = 1;
1418 }
1419
1420 size = res->end - res->start;
1421 pci_read_config_dword(pdev, where, ®);
1422 reg = ((reg & size) |
1423 (((u32)(res->start - root->start)) & ~size));
1424 pci_write_config_dword(pdev, where, reg);
1425
1426 /* This knows that the upper 32-bits of the address
1427 * must be zero. Our PCI common layer enforces this.
1428 */
1429 if (is_64bit)
1430 pci_write_config_dword(pdev, where + 4, 0);
1431 }
1432
1433 static void __init schizo_resource_adjust(struct pci_dev *pdev,
1434 struct resource *res,
1435 struct resource *root)
1436 {
1437 res->start += root->start;
1438 res->end += root->start;
1439 }
1440
1441 /* Interrogate Safari match/mask registers to figure out where
1442 * PCI MEM, I/O, and Config space are for this PCI bus module.
1443 */
1444
1445 #define SCHIZO_PCI_A_MEM_MATCH 0x00040UL
1446 #define SCHIZO_PCI_A_MEM_MASK 0x00048UL
1447 #define SCHIZO_PCI_A_IO_MATCH 0x00050UL
1448 #define SCHIZO_PCI_A_IO_MASK 0x00058UL
1449 #define SCHIZO_PCI_B_MEM_MATCH 0x00060UL
1450 #define SCHIZO_PCI_B_MEM_MASK 0x00068UL
1451 #define SCHIZO_PCI_B_IO_MATCH 0x00070UL
1452 #define SCHIZO_PCI_B_IO_MASK 0x00078UL
1453
1454 /* VAL must be non-zero. */
1455 static unsigned long strip_to_lowest_bit_set(unsigned long val)
1456 {
1457 unsigned long tmp;
1458
1459 tmp = 1UL;
1460 while (!(tmp & val))
1461 tmp <<= 1UL;
1462
1463 return tmp;
1464 }
1465
1466 static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm,
1467 int is_pbm_a, unsigned long reg_base)
1468 {
1469 u64 mem_match, mem_mask;
1470 u64 io_match;
1471 u64 long a, b;
1472
1473 if (is_pbm_a) {
1474 mem_match = reg_base + SCHIZO_PCI_A_MEM_MATCH;
1475 io_match = reg_base + SCHIZO_PCI_A_IO_MATCH;
1476 } else {
1477 mem_match = reg_base + SCHIZO_PCI_B_MEM_MATCH;
1478 io_match = reg_base + SCHIZO_PCI_B_IO_MATCH;
1479 }
1480 mem_mask = mem_match + 0x8UL;
1481
1482 a = schizo_read(mem_match) & ~0x8000000000000000UL;
1483 b = strip_to_lowest_bit_set(schizo_read(mem_mask));
1484
1485 /* It should be 2GB in size. */
1486 pbm->mem_space.start = a;
1487 pbm->mem_space.end = a + (b - 1UL);
1488 pbm->mem_space.flags = IORESOURCE_MEM;
1489
1490 /* This 32MB area is divided into two pieces. The first
1491 * 16MB is Config space, the next 16MB is I/O space.
1492 */
1493
1494 a = schizo_read(io_match) & ~0x8000000000000000UL;
1495 pbm->config_space = a;
1496 printk("SCHIZO PBM%c: Local PCI config space at %016lx\n",
1497 (is_pbm_a ? 'A' : 'B'), pbm->config_space);
1498
1499 a += (16UL * 1024UL * 1024UL);
1500 pbm->io_space.start = a;
1501 pbm->io_space.end = a + ((16UL * 1024UL * 1024UL) - 1UL);
1502 pbm->io_space.flags = IORESOURCE_IO;
1503 }
1504
1505 static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1506 struct pci_pbm_info *pbm)
1507 {
1508 char *name = pbm->name;
1509
1510 sprintf(name, "SCHIZO%d PBM%c",
1511 p->index,
1512 (pbm == &p->pbm_A ? 'A' : 'B'));
1513 pbm->io_space.name = pbm->mem_space.name = name;
1514
1515 request_resource(&ioport_resource, &pbm->io_space);
1516 request_resource(&iomem_resource, &pbm->mem_space);
1517 pci_register_legacy_regions(&pbm->io_space,
1518 &pbm->mem_space);
1519 }
1520
1521 #define SCHIZO_STRBUF_CONTROL_A (SCHIZO_PBM_A_REGS_OFF + 0x02800UL)
1522 #define SCHIZO_STRBUF_FLUSH_A (SCHIZO_PBM_A_REGS_OFF + 0x02808UL)
1523 #define SCHIZO_STRBUF_FSYNC_A (SCHIZO_PBM_A_REGS_OFF + 0x02810UL)
1524 #define SCHIZO_STRBUF_CTXFLUSH_A (SCHIZO_PBM_A_REGS_OFF + 0x02818UL)
1525 #define SCHIZO_STRBUF_CTXMATCH_A (SCHIZO_PBM_A_REGS_OFF + 0x10000UL)
1526
1527 #define SCHIZO_STRBUF_CONTROL_B (SCHIZO_PBM_B_REGS_OFF + 0x02800UL)
1528 #define SCHIZO_STRBUF_FLUSH_B (SCHIZO_PBM_B_REGS_OFF + 0x02808UL)
1529 #define SCHIZO_STRBUF_FSYNC_B (SCHIZO_PBM_B_REGS_OFF + 0x02810UL)
1530 #define SCHIZO_STRBUF_CTXFLUSH_B (SCHIZO_PBM_B_REGS_OFF + 0x02818UL)
1531 #define SCHIZO_STRBUF_CTXMATCH_B (SCHIZO_PBM_B_REGS_OFF + 0x10000UL)
1532
1533 static void schizo_pbm_strbuf_init(struct pci_controller_info *p,
1534 struct pci_pbm_info *pbm,
1535 int is_pbm_a)
1536 {
1537 unsigned long base = p->controller_regs;
1538 u64 control;
1539
1540 /* SCHIZO has context flushing. */
1541 if (is_pbm_a) {
1542 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL_A;
1543 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH_A;
1544 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC_A;
1545 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH_A;
1546 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH_A;
1547 } else {
1548 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL_B;
1549 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH_B;
1550 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC_B;
1551 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH_B;
1552 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH_B;
1553 }
1554
1555 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1556 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1557 + 63UL)
1558 & ~63UL);
1559 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1560 __pa(pbm->stc.strbuf_flushflag);
1561
1562 /* Turn off LRU locking and diag mode, enable the
1563 * streaming buffer and leave the rerun-disable
1564 * setting however OBP set it.
1565 */
1566 control = schizo_read(pbm->stc.strbuf_control);
1567 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1568 SCHIZO_STRBUF_CTRL_LENAB |
1569 SCHIZO_STRBUF_CTRL_DENAB);
1570 control |= SCHIZO_STRBUF_CTRL_ENAB;
1571 schizo_write(pbm->stc.strbuf_control, control);
1572
1573 pbm->stc.strbuf_enabled = 1;
1574 }
1575
1576 #define SCHIZO_IOMMU_CONTROL_A (SCHIZO_PBM_A_REGS_OFF + 0x00200UL)
1577 #define SCHIZO_IOMMU_TSBBASE_A (SCHIZO_PBM_A_REGS_OFF + 0x00208UL)
1578 #define SCHIZO_IOMMU_FLUSH_A (SCHIZO_PBM_A_REGS_OFF + 0x00210UL)
1579 #define SCHIZO_IOMMU_CTXFLUSH_A (SCHIZO_PBM_A_REGS_OFF + 0x00218UL)
1580 #define SCHIZO_IOMMU_TAG_A (SCHIZO_PBM_A_REGS_OFF + 0x0a580UL)
1581 #define SCHIZO_IOMMU_DATA_A (SCHIZO_PBM_A_REGS_OFF + 0x0a600UL)
1582 #define SCHIZO_IOMMU_CONTROL_B (SCHIZO_PBM_B_REGS_OFF + 0x00200UL)
1583 #define SCHIZO_IOMMU_TSBBASE_B (SCHIZO_PBM_B_REGS_OFF + 0x00208UL)
1584 #define SCHIZO_IOMMU_FLUSH_B (SCHIZO_PBM_B_REGS_OFF + 0x00210UL)
1585 #define SCHIZO_IOMMU_CTXFLUSH_B (SCHIZO_PBM_B_REGS_OFF + 0x00218UL)
1586 #define SCHIZO_IOMMU_TAG_B (SCHIZO_PBM_B_REGS_OFF + 0x0a580UL)
1587 #define SCHIZO_IOMMU_DATA_B (SCHIZO_PBM_B_REGS_OFF + 0x0a600UL)
1588
1589 static void schizo_pbm_iommu_init(struct pci_controller_info *p,
1590 struct pci_pbm_info *pbm,
1591 int is_pbm_a)
1592 {
1593 struct pci_iommu *iommu = pbm->iommu;
1594 unsigned long tsbbase, i, tagbase, database;
1595 u64 control;
1596
1597 /* Setup initial software IOMMU state. */
1598 spin_lock_init(&iommu->lock);
1599 iommu->iommu_cur_ctx = 0;
1600
1601 /* Register addresses, SCHIZO has iommu ctx flushing. */
1602 if (is_pbm_a) {
1603 iommu->iommu_control = p->controller_regs + SCHIZO_IOMMU_CONTROL_A;
1604 iommu->iommu_tsbbase = p->controller_regs + SCHIZO_IOMMU_TSBBASE_A;
1605 iommu->iommu_flush = p->controller_regs + SCHIZO_IOMMU_FLUSH_A;
1606 iommu->iommu_ctxflush = p->controller_regs + SCHIZO_IOMMU_CTXFLUSH_A;
1607 } else {
1608 iommu->iommu_control = p->controller_regs + SCHIZO_IOMMU_CONTROL_B;
1609 iommu->iommu_tsbbase = p->controller_regs + SCHIZO_IOMMU_TSBBASE_B;
1610 iommu->iommu_flush = p->controller_regs + SCHIZO_IOMMU_FLUSH_B;
1611 iommu->iommu_ctxflush = p->controller_regs + SCHIZO_IOMMU_CTXFLUSH_B;
1612 }
1613
1614 /* We use the main control/status register of SCHIZO as the write
1615 * completion register.
1616 */
1617 iommu->write_complete_reg = p->controller_regs + 0x10000UL;
1618
1619 /*
1620 * Invalidate TLB Entries.
1621 */
1622 control = schizo_read(iommu->iommu_control);
1623 control |= SCHIZO_IOMMU_CTRL_DENAB;
1624 schizo_write(iommu->iommu_control, control);
1625
1626 if (is_pbm_a)
1627 tagbase = SCHIZO_IOMMU_TAG_A, database = SCHIZO_IOMMU_DATA_A;
1628 else
1629 tagbase = SCHIZO_IOMMU_TAG_B, database = SCHIZO_IOMMU_DATA_B;
1630 for(i = 0; i < 16; i++) {
1631 schizo_write(p->controller_regs + tagbase + (i * 8UL), 0);
1632 schizo_write(p->controller_regs + database + (i * 8UL), 0);
1633 }
1634
1635 /* Leave diag mode enabled for full-flushing done
1636 * in pci_iommu.c
1637 */
1638
1639 /* Using assumed page size 8K with 128K entries we need 1MB iommu page
1640 * table (128K ioptes * 8 bytes per iopte). This is
1641 * page order 7 on UltraSparc.
1642 */
1643 tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE));
1644 if (!tsbbase) {
1645 prom_printf("SCHIZO_IOMMU: Error, gfp(tsb) failed.\n");
1646 prom_halt();
1647 }
1648 iommu->page_table = (iopte_t *)tsbbase;
1649 iommu->page_table_sz_bits = 17;
1650 iommu->page_table_map_base = 0xc0000000;
1651 iommu->dma_addr_mask = 0xffffffff;
1652 memset((char *)tsbbase, 0, IO_TSB_SIZE);
1653
1654 /* We start with no consistent mappings. */
1655 iommu->lowest_consistent_map =
1656 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
1657
1658 for (i = 0; i < PBM_NCLUSTERS; i++) {
1659 iommu->alloc_info[i].flush = 0;
1660 iommu->alloc_info[i].next = 0;
1661 }
1662
1663 schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));
1664
1665 control = schizo_read(iommu->iommu_control);
1666 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1667 control |= (SCHIZO_IOMMU_TSBSZ_128K | SCHIZO_IOMMU_CTRL_ENAB);
1668 schizo_write(iommu->iommu_control, control);
1669 }
1670
1671 static void schizo_pbm_init(struct pci_controller_info *p,
1672 int prom_node, int is_pbm_a)
1673 {
1674 unsigned int busrange[2];
1675 struct pci_pbm_info *pbm;
1676 int err;
1677
1678 if (is_pbm_a)
1679 pbm = &p->pbm_A;
1680 else
1681 pbm = &p->pbm_B;
1682
1683 schizo_determine_mem_io_space(pbm, is_pbm_a, p->controller_regs);
1684 pbm_register_toplevel_resources(p, pbm);
1685
1686 pbm->parent = p;
1687 pbm->prom_node = prom_node;
1688 pbm->pci_first_slot = 1;
1689 prom_getstring(prom_node, "name",
1690 pbm->prom_name,
1691 sizeof(pbm->prom_name));
1692
1693 err = prom_getproperty(prom_node, "ranges",
1694 (char *) pbm->pbm_ranges,
1695 sizeof(pbm->pbm_ranges));
1696 if (err != -1)
1697 pbm->num_pbm_ranges =
1698 (err / sizeof(struct linux_prom_pci_ranges));
1699 else
1700 pbm->num_pbm_ranges = 0;
1701
1702 err = prom_getproperty(prom_node, "interrupt-map",
1703 (char *)pbm->pbm_intmap,
1704 sizeof(pbm->pbm_intmap));
1705 if (err != -1) {
1706 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1707 err = prom_getproperty(prom_node, "interrupt-map-mask",
1708 (char *)&pbm->pbm_intmask,
1709 sizeof(pbm->pbm_intmask));
1710 if (err == -1) {
1711 prom_printf("SCHIZO-PBM: Fatal error, no "
1712 "interrupt-map-mask.\n");
1713 prom_halt();
1714 }
1715 } else {
1716 pbm->num_pbm_intmap = 0;
1717 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1718 }
1719
1720 err = prom_getproperty(prom_node, "bus-range",
1721 (char *)&busrange[0],
1722 sizeof(busrange));
1723 if (err == 0 || err == -1) {
1724 prom_printf("SCHIZO-PBM: Fatal error, no bus-range.\n");
1725 prom_halt();
1726 }
1727 pbm->pci_first_busno = busrange[0];
1728 pbm->pci_last_busno = busrange[1];
1729
1730 schizo_pbm_iommu_init(p, pbm, is_pbm_a);
1731 schizo_pbm_strbuf_init(p, pbm, is_pbm_a);
1732 }
1733
1734 static void schizo_controller_hwinit(struct pci_controller_info *p)
1735 {
1736 unsigned long pbm_a_base, pbm_b_base;
1737 u64 tmp;
1738
1739 pbm_a_base = p->controller_regs + SCHIZO_PBM_A_REGS_OFF;
1740 pbm_b_base = p->controller_regs + SCHIZO_PBM_B_REGS_OFF;
1741
1742 /* Set IRQ retry to infinity. */
1743 schizo_write(pbm_a_base + 0x1a00UL, 0xff);
1744 schizo_write(pbm_b_base + 0x1a00UL, 0xff);
1745
1746 /* Enable arbiter for all PCI slots. */
1747 tmp = schizo_read(pbm_a_base + 0x2000UL);
1748 tmp |= 0x3fUL;
1749 schizo_write(pbm_a_base + 0x2000UL, tmp);
1750
1751 tmp = schizo_read(pbm_b_base + 0x2000UL);
1752 tmp |= 0x3fUL;
1753 schizo_write(pbm_b_base + 0x2000UL, tmp);
1754 }
1755
1756 void __init schizo_init(int node, char *model_name)
1757 {
1758 struct linux_prom64_registers pr_regs[3];
1759 struct pci_controller_info *p;
1760 struct pci_iommu *iommu;
1761 unsigned long flags;
1762 u32 portid;
1763 int is_pbm_a, err;
1764
1765 portid = prom_getintdefault(node, "portid", 0xff);
1766
1767 spin_lock_irqsave(&pci_controller_lock, flags);
1768 for(p = pci_controller_root; p; p = p->next) {
1769 if (p->portid == portid) {
1770 spin_unlock_irqrestore(&pci_controller_lock, flags);
1771 is_pbm_a = (p->pbm_A.prom_node == 0);
1772 schizo_pbm_init(p, node, is_pbm_a);
1773 return;
1774 }
1775 }
1776 spin_unlock_irqrestore(&pci_controller_lock, flags);
1777
1778 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1779 if (!p) {
1780 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1781 prom_halt();
1782 }
1783 memset(p, 0, sizeof(*p));
1784
1785 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1786 if (!iommu) {
1787 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1788 prom_halt();
1789 }
1790 memset(iommu, 0, sizeof(*iommu));
1791 p->pbm_A.iommu = iommu;
1792
1793 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1794 if (!iommu) {
1795 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1796 prom_halt();
1797 }
1798 memset(iommu, 0, sizeof(*iommu));
1799 p->pbm_B.iommu = iommu;
1800
1801 spin_lock_irqsave(&pci_controller_lock, flags);
1802 p->next = pci_controller_root;
1803 pci_controller_root = p;
1804 spin_unlock_irqrestore(&pci_controller_lock, flags);
1805
1806 p->portid = portid;
1807 p->index = pci_num_controllers++;
1808 p->pbms_same_domain = 0;
1809 p->scan_bus = schizo_scan_bus;
1810 p->irq_build = schizo_irq_build;
1811 p->base_address_update = schizo_base_address_update;
1812 p->resource_adjust = schizo_resource_adjust;
1813 p->pci_ops = &schizo_ops;
1814
1815 /* Three OBP regs:
1816 * 1) PBM controller regs
1817 * 2) Schizo front-end controller regs (same for both PBMs)
1818 * 3) PBM PCI config space
1819 */
1820 err = prom_getproperty(node, "reg",
1821 (char *)&pr_regs[0],
1822 sizeof(pr_regs));
1823 if (err == 0 || err == -1) {
1824 prom_printf("SCHIZO: Fatal error, no reg property.\n");
1825 prom_halt();
1826 }
1827
1828 p->controller_regs = pr_regs[1].phys_addr - 0x10000UL;
1829 printk("PCI: Found SCHIZO, control regs at %016lx\n",
1830 p->controller_regs);
1831
1832 /* Like PSYCHO we have a 2GB aligned area for memory space. */
1833 pci_memspace_mask = 0x7fffffffUL;
1834
1835 /* Init core controller. */
1836 schizo_controller_hwinit(p);
1837
1838 is_pbm_a = ((pr_regs[0].phys_addr & 0x00700000) == 0x00600000);
1839 schizo_pbm_init(p, node, is_pbm_a);
1840 }
1841