File: /usr/src/linux/arch/sparc64/kernel/sbus.c
1 /* $Id: sbus.c,v 1.16 2001/08/24 19:36:58 kanoj Exp $
2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/spinlock.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13
14 #include <asm/page.h>
15 #include <asm/sbus.h>
16 #include <asm/io.h>
17 #include <asm/upa.h>
18 #include <asm/cache.h>
19 #include <asm/dma.h>
20 #include <asm/irq.h>
21 #include <asm/starfire.h>
22
23 #include "iommu_common.h"
24
25 /* These should be allocated on an SMP_CACHE_BYTES
26 * aligned boundry for optimal performance.
27 *
28 * On SYSIO, using an 8K page size we have 1GB of SBUS
29 * DMA space mapped. We divide this space into equally
30 * sized clusters. Currently we allow clusters up to a
31 * size of 1MB. If anything begins to generate DMA
32 * mapping requests larger than this we will need to
33 * increase things a bit.
34 */
35
36 #define NCLUSTERS 8UL
37 #define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
38 #define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
39 #define CLUSTER_MASK (CLUSTER_SIZE - 1)
40 #define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
41 #define MAP_BASE ((u32)0xc0000000)
42
43 struct sbus_iommu {
44 /*0x00*/spinlock_t lock;
45
46 /*0x08*/iopte_t *page_table;
47 /*0x10*/unsigned long strbuf_regs;
48 /*0x18*/unsigned long iommu_regs;
49 /*0x20*/unsigned long sbus_control_reg;
50
51 /*0x28*/volatile unsigned long strbuf_flushflag;
52
53 /* If NCLUSTERS is ever decresed to 4 or lower,
54 * you must increase the size of the type of
55 * these counters. You have been duly warned. -DaveM
56 */
57 /*0x30*/struct {
58 u16 next;
59 u16 flush;
60 } alloc_info[NCLUSTERS];
61
62 /* The lowest used consistent mapping entry. Since
63 * we allocate consistent maps out of cluster 0 this
64 * is relative to the beginning of closter 0.
65 */
66 /*0x50*/u32 lowest_consistent_map;
67 };
68
69 /* Offsets from iommu_regs */
70 #define SYSIO_IOMMUREG_BASE 0x2400UL
71 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
72 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
73 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
74 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
75 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
76 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
77 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
78 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
79
80 #define IOMMU_DRAM_VALID (1UL << 30UL)
81
82 static void __iommu_flushall(struct sbus_iommu *iommu)
83 {
84 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
85 int entry;
86
87 for (entry = 0; entry < 16; entry++) {
88 upa_writeq(0, tag);
89 tag += 8UL;
90 }
91 upa_readq(iommu->sbus_control_reg);
92
93 for (entry = 0; entry < NCLUSTERS; entry++) {
94 iommu->alloc_info[entry].flush =
95 iommu->alloc_info[entry].next;
96 }
97 }
98
99 static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
100 {
101 while (npages--)
102 upa_writeq(base + (npages << IO_PAGE_SHIFT),
103 iommu->iommu_regs + IOMMU_FLUSH);
104 upa_readq(iommu->sbus_control_reg);
105 }
106
107 /* Offsets from strbuf_regs */
108 #define SYSIO_STRBUFREG_BASE 0x2800UL
109 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
110 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
111 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
112 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
113 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
114 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
115 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
116
117 #define STRBUF_TAG_VALID 0x02UL
118
119 static void strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
120 {
121 iommu->strbuf_flushflag = 0UL;
122 while (npages--)
123 upa_writeq(base + (npages << IO_PAGE_SHIFT),
124 iommu->strbuf_regs + STRBUF_PFLUSH);
125
126 /* Whoopee cushion! */
127 upa_writeq(__pa(&iommu->strbuf_flushflag),
128 iommu->strbuf_regs + STRBUF_FSYNC);
129 upa_readq(iommu->sbus_control_reg);
130 while (iommu->strbuf_flushflag == 0UL)
131 membar("#LoadLoad");
132 }
133
134 static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
135 {
136 iopte_t *iopte, *limit, *first;
137 unsigned long cnum, ent, flush_point;
138
139 cnum = 0;
140 while ((1UL << cnum) < npages)
141 cnum++;
142 iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
143
144 if (cnum == 0)
145 limit = (iommu->page_table +
146 iommu->lowest_consistent_map);
147 else
148 limit = (iopte + CLUSTER_NPAGES);
149
150 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
151 flush_point = iommu->alloc_info[cnum].flush;
152
153 first = iopte;
154 for (;;) {
155 if (iopte_val(*iopte) == 0UL) {
156 if ((iopte + (1 << cnum)) >= limit)
157 ent = 0;
158 else
159 ent = ent + 1;
160 iommu->alloc_info[cnum].next = ent;
161 if (ent == flush_point)
162 __iommu_flushall(iommu);
163 break;
164 }
165 iopte += (1 << cnum);
166 ent++;
167 if (iopte >= limit) {
168 iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
169 ent = 0;
170 }
171 if (ent == flush_point)
172 __iommu_flushall(iommu);
173 if (iopte == first)
174 goto bad;
175 }
176
177 /* I've got your streaming cluster right here buddy boy... */
178 return iopte;
179
180 bad:
181 printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
182 npages);
183 return NULL;
184 }
185
186 static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
187 {
188 unsigned long cnum, ent;
189 iopte_t *iopte;
190
191 cnum = 0;
192 while ((1UL << cnum) < npages)
193 cnum++;
194 ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
195 iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
196 iopte_val(*iopte) = 0UL;
197
198 /* If the global flush might not have caught this entry,
199 * adjust the flush point such that we will flush before
200 * ever trying to reuse it.
201 */
202 #define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
203 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
204 iommu->alloc_info[cnum].flush = ent;
205 #undef between
206 }
207
208 /* We allocate consistent mappings from the end of cluster zero. */
209 static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
210 {
211 iopte_t *iopte;
212
213 iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
214 while (iopte > iommu->page_table) {
215 iopte--;
216 if (!(iopte_val(*iopte) & IOPTE_VALID)) {
217 unsigned long tmp = npages;
218
219 while (--tmp) {
220 iopte--;
221 if (iopte_val(*iopte) & IOPTE_VALID)
222 break;
223 }
224 if (tmp == 0) {
225 u32 entry = (iopte - iommu->page_table);
226
227 if (entry < iommu->lowest_consistent_map)
228 iommu->lowest_consistent_map = entry;
229 return iopte;
230 }
231 }
232 }
233 return NULL;
234 }
235
236 static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
237 {
238 iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
239
240 if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
241 iopte_t *walk = iopte + npages;
242 iopte_t *limit;
243
244 limit = iommu->page_table + CLUSTER_NPAGES;
245 while (walk < limit) {
246 if (iopte_val(*walk) != 0UL)
247 break;
248 walk++;
249 }
250 iommu->lowest_consistent_map =
251 (walk - iommu->page_table);
252 }
253
254 while (npages--)
255 *iopte++ = __iopte(0UL);
256 }
257
258 void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
259 {
260 unsigned long order, first_page, flags;
261 struct sbus_iommu *iommu;
262 iopte_t *iopte;
263 void *ret;
264 int npages;
265
266 if (size <= 0 || sdev == NULL || dvma_addr == NULL)
267 return NULL;
268
269 size = IO_PAGE_ALIGN(size);
270 order = get_order(size);
271 if (order >= 10)
272 return NULL;
273 first_page = __get_free_pages(GFP_KERNEL, order);
274 if (first_page == 0UL)
275 return NULL;
276 memset((char *)first_page, 0, PAGE_SIZE << order);
277
278 iommu = sdev->bus->iommu;
279
280 spin_lock_irqsave(&iommu->lock, flags);
281 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
282 if (iopte == NULL) {
283 spin_unlock_irqrestore(&iommu->lock, flags);
284 free_pages(first_page, order);
285 return NULL;
286 }
287
288 /* Ok, we're committed at this point. */
289 *dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
290 ret = (void *) first_page;
291 npages = size >> IO_PAGE_SHIFT;
292 while (npages--) {
293 *iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
294 (__pa(first_page) & IOPTE_PAGE));
295 first_page += IO_PAGE_SIZE;
296 }
297 iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
298 spin_unlock_irqrestore(&iommu->lock, flags);
299
300 return ret;
301 }
302
303 void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
304 {
305 unsigned long order, npages;
306 struct sbus_iommu *iommu;
307
308 if (size <= 0 || sdev == NULL || cpu == NULL)
309 return;
310
311 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
312 iommu = sdev->bus->iommu;
313
314 spin_lock_irq(&iommu->lock);
315 free_consistent_cluster(iommu, dvma, npages);
316 iommu_flush(iommu, dvma, npages);
317 spin_unlock_irq(&iommu->lock);
318
319 order = get_order(size);
320 if (order < 10)
321 free_pages((unsigned long)cpu, order);
322 }
323
324 dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
325 {
326 struct sbus_iommu *iommu = sdev->bus->iommu;
327 unsigned long npages, pbase, flags;
328 iopte_t *iopte;
329 u32 dma_base, offset;
330 unsigned long iopte_bits;
331
332 if (dir == SBUS_DMA_NONE)
333 BUG();
334
335 pbase = (unsigned long) ptr;
336 offset = (u32) (pbase & ~IO_PAGE_MASK);
337 size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
338 pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
339
340 spin_lock_irqsave(&iommu->lock, flags);
341 npages = size >> IO_PAGE_SHIFT;
342 iopte = alloc_streaming_cluster(iommu, npages);
343 if (iopte == NULL)
344 goto bad;
345 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
346 npages = size >> IO_PAGE_SHIFT;
347 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
348 if (dir != SBUS_DMA_TODEVICE)
349 iopte_bits |= IOPTE_WRITE;
350 while (npages--) {
351 *iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
352 pbase += IO_PAGE_SIZE;
353 }
354 npages = size >> IO_PAGE_SHIFT;
355 spin_unlock_irqrestore(&iommu->lock, flags);
356
357 return (dma_base | offset);
358
359 bad:
360 spin_unlock_irqrestore(&iommu->lock, flags);
361 BUG();
362 return 0;
363 }
364
365 void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
366 {
367 struct sbus_iommu *iommu = sdev->bus->iommu;
368 u32 dma_base = dma_addr & IO_PAGE_MASK;
369 unsigned long flags;
370
371 size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
372
373 spin_lock_irqsave(&iommu->lock, flags);
374 free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
375 strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT);
376 spin_unlock_irqrestore(&iommu->lock, flags);
377 }
378
379 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, unsigned long iopte_bits)
380 {
381 struct scatterlist *dma_sg = sg;
382 int i;
383
384 for (i = 0; i < nused; i++) {
385 unsigned long pteval = ~0UL;
386 u32 dma_npages;
387
388 dma_npages = ((dma_sg->dvma_address & (IO_PAGE_SIZE - 1UL)) +
389 dma_sg->dvma_length +
390 ((u32)(IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
391 do {
392 unsigned long offset;
393 signed int len;
394
395 /* If we are here, we know we have at least one
396 * more page to map. So walk forward until we
397 * hit a page crossing, and begin creating new
398 * mappings from that spot.
399 */
400 for (;;) {
401 unsigned long tmp;
402
403 tmp = (unsigned long) __pa(sg->address);
404 len = sg->length;
405 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
406 pteval = tmp & IO_PAGE_MASK;
407 offset = tmp & (IO_PAGE_SIZE - 1UL);
408 break;
409 }
410 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
411 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
412 offset = 0UL;
413 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
414 break;
415 }
416 sg++;
417 }
418
419 pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
420 while (len > 0) {
421 *iopte++ = __iopte(pteval);
422 pteval += IO_PAGE_SIZE;
423 len -= (IO_PAGE_SIZE - offset);
424 offset = 0;
425 dma_npages--;
426 }
427
428 pteval = (pteval & IOPTE_PAGE) + len;
429 sg++;
430
431 /* Skip over any tail mappings we've fully mapped,
432 * adjusting pteval along the way. Stop when we
433 * detect a page crossing event.
434 */
435 while ((pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
436 pteval == __pa(sg->address) &&
437 ((pteval ^
438 (__pa(sg->address) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
439 pteval += sg->length;
440 sg++;
441 }
442 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
443 pteval = ~0UL;
444 } while (dma_npages != 0);
445 dma_sg++;
446 }
447 }
448
449 int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
450 {
451 struct sbus_iommu *iommu = sdev->bus->iommu;
452 unsigned long flags, npages;
453 iopte_t *iopte;
454 u32 dma_base;
455 struct scatterlist *sgtmp;
456 int used;
457 unsigned long iopte_bits;
458
459 if (dir == SBUS_DMA_NONE)
460 BUG();
461
462 /* Fast path single entry scatterlists. */
463 if (nents == 1) {
464 sg->dvma_address = sbus_map_single(sdev, sg->address, sg->length, dir);
465 sg->dvma_length = sg->length;
466 return 1;
467 }
468
469 npages = prepare_sg(sg, nents);
470
471 spin_lock_irqsave(&iommu->lock, flags);
472 iopte = alloc_streaming_cluster(iommu, npages);
473 if (iopte == NULL)
474 goto bad;
475 dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
476
477 /* Normalize DVMA addresses. */
478 sgtmp = sg;
479 used = nents;
480
481 while (used && sgtmp->dvma_length) {
482 sgtmp->dvma_address += dma_base;
483 sgtmp++;
484 used--;
485 }
486 used = nents - used;
487
488 iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
489 if (dir != SBUS_DMA_TODEVICE)
490 iopte_bits |= IOPTE_WRITE;
491
492 fill_sg(iopte, sg, used, iopte_bits);
493 #ifdef VERIFY_SG
494 verify_sglist(sg, nents, iopte, npages);
495 #endif
496 spin_unlock_irqrestore(&iommu->lock, flags);
497
498 return used;
499
500 bad:
501 spin_unlock_irqrestore(&iommu->lock, flags);
502 BUG();
503 return 0;
504 }
505
506 void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
507 {
508 unsigned long size, flags;
509 struct sbus_iommu *iommu;
510 u32 dvma_base;
511 int i;
512
513 /* Fast path single entry scatterlists. */
514 if (nents == 1) {
515 sbus_unmap_single(sdev, sg->dvma_address, sg->dvma_length, direction);
516 return;
517 }
518
519 dvma_base = sg[0].dvma_address & IO_PAGE_MASK;
520 for (i = 0; i < nents; i++) {
521 if (sg[i].dvma_length == 0)
522 break;
523 }
524 i--;
525 size = IO_PAGE_ALIGN(sg[i].dvma_address + sg[i].dvma_length) - dvma_base;
526
527 iommu = sdev->bus->iommu;
528 spin_lock_irqsave(&iommu->lock, flags);
529 free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
530 strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT);
531 spin_unlock_irqrestore(&iommu->lock, flags);
532 }
533
534 void sbus_dma_sync_single(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
535 {
536 struct sbus_iommu *iommu = sdev->bus->iommu;
537 unsigned long flags;
538
539 size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
540
541 spin_lock_irqsave(&iommu->lock, flags);
542 strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT);
543 spin_unlock_irqrestore(&iommu->lock, flags);
544 }
545
546 void sbus_dma_sync_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
547 {
548 struct sbus_iommu *iommu = sdev->bus->iommu;
549 unsigned long flags, size;
550 u32 base;
551 int i;
552
553 base = sg[0].dvma_address & IO_PAGE_MASK;
554 for (i = 0; i < nents; i++) {
555 if (sg[i].dvma_length == 0)
556 break;
557 }
558 i--;
559 size = IO_PAGE_ALIGN(sg[i].dvma_address + sg[i].dvma_length) - base;
560
561 spin_lock_irqsave(&iommu->lock, flags);
562 strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT);
563 spin_unlock_irqrestore(&iommu->lock, flags);
564 }
565
566 /* Enable 64-bit DVMA mode for the given device. */
567 void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
568 {
569 struct sbus_iommu *iommu = sdev->bus->iommu;
570 int slot = sdev->slot;
571 unsigned long cfg_reg;
572 u64 val;
573
574 cfg_reg = iommu->sbus_control_reg;
575 switch (slot) {
576 case 0:
577 cfg_reg += 0x20UL;
578 break;
579 case 1:
580 cfg_reg += 0x28UL;
581 break;
582 case 2:
583 cfg_reg += 0x30UL;
584 break;
585 case 3:
586 cfg_reg += 0x38UL;
587 break;
588 case 13:
589 cfg_reg += 0x40UL;
590 break;
591 case 14:
592 cfg_reg += 0x48UL;
593 break;
594 case 15:
595 cfg_reg += 0x50UL;
596 break;
597
598 default:
599 return;
600 };
601
602 val = upa_readq(cfg_reg);
603 if (val & (1UL << 14UL)) {
604 /* Extended transfer mode already enabled. */
605 return;
606 }
607
608 val |= (1UL << 14UL);
609
610 if (bursts & DMA_BURST8)
611 val |= (1UL << 1UL);
612 if (bursts & DMA_BURST16)
613 val |= (1UL << 2UL);
614 if (bursts & DMA_BURST32)
615 val |= (1UL << 3UL);
616 if (bursts & DMA_BURST64)
617 val |= (1UL << 4UL);
618 upa_writeq(val, cfg_reg);
619 }
620
621 /* SBUS SYSIO INO number to Sparc PIL level. */
622 static unsigned char sysio_ino_to_pil[] = {
623 0, 1, 2, 7, 5, 7, 8, 9, /* SBUS slot 0 */
624 0, 1, 2, 7, 5, 7, 8, 9, /* SBUS slot 1 */
625 0, 1, 2, 7, 5, 7, 8, 9, /* SBUS slot 2 */
626 0, 1, 2, 7, 5, 7, 8, 9, /* SBUS slot 3 */
627 3, /* Onboard SCSI */
628 5, /* Onboard Ethernet */
629 /*XXX*/ 8, /* Onboard BPP */
630 0, /* Bogon */
631 13, /* Audio */
632 /*XXX*/15, /* PowerFail */
633 0, /* Bogon */
634 0, /* Bogon */
635 12, /* Zilog Serial Channels (incl. Keyboard/Mouse lines) */
636 11, /* Floppy */
637 0, /* Spare Hardware (bogon for now) */
638 0, /* Keyboard (bogon for now) */
639 0, /* Mouse (bogon for now) */
640 0, /* Serial (bogon for now) */
641 0, 0, /* Bogon, Bogon */
642 10, /* Timer 0 */
643 11, /* Timer 1 */
644 0, 0, /* Bogon, Bogon */
645 15, /* Uncorrectable SBUS Error */
646 15, /* Correctable SBUS Error */
647 15, /* SBUS Error */
648 /*XXX*/ 0, /* Power Management (bogon for now) */
649 };
650
651 /* INO number to IMAP register offset for SYSIO external IRQ's.
652 * This should conform to both Sunfire/Wildfire server and Fusion
653 * desktop designs.
654 */
655 #define SYSIO_IMAP_SLOT0 0x2c04UL
656 #define SYSIO_IMAP_SLOT1 0x2c0cUL
657 #define SYSIO_IMAP_SLOT2 0x2c14UL
658 #define SYSIO_IMAP_SLOT3 0x2c1cUL
659 #define SYSIO_IMAP_SCSI 0x3004UL
660 #define SYSIO_IMAP_ETH 0x300cUL
661 #define SYSIO_IMAP_BPP 0x3014UL
662 #define SYSIO_IMAP_AUDIO 0x301cUL
663 #define SYSIO_IMAP_PFAIL 0x3024UL
664 #define SYSIO_IMAP_KMS 0x302cUL
665 #define SYSIO_IMAP_FLPY 0x3034UL
666 #define SYSIO_IMAP_SHW 0x303cUL
667 #define SYSIO_IMAP_KBD 0x3044UL
668 #define SYSIO_IMAP_MS 0x304cUL
669 #define SYSIO_IMAP_SER 0x3054UL
670 #define SYSIO_IMAP_TIM0 0x3064UL
671 #define SYSIO_IMAP_TIM1 0x306cUL
672 #define SYSIO_IMAP_UE 0x3074UL
673 #define SYSIO_IMAP_CE 0x307cUL
674 #define SYSIO_IMAP_SBERR 0x3084UL
675 #define SYSIO_IMAP_PMGMT 0x308cUL
676 #define SYSIO_IMAP_GFX 0x3094UL
677 #define SYSIO_IMAP_EUPA 0x309cUL
678
679 #define bogon ((unsigned long) -1)
680 static unsigned long sysio_irq_offsets[] = {
681 /* SBUS Slot 0 --> 3, level 1 --> 7 */
682 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
683 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
684 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
685 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
686 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
687 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
688 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
689 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
690
691 /* Onboard devices (not relevant/used on SunFire). */
692 SYSIO_IMAP_SCSI,
693 SYSIO_IMAP_ETH,
694 SYSIO_IMAP_BPP,
695 bogon,
696 SYSIO_IMAP_AUDIO,
697 SYSIO_IMAP_PFAIL,
698 bogon,
699 bogon,
700 SYSIO_IMAP_KMS,
701 SYSIO_IMAP_FLPY,
702 SYSIO_IMAP_SHW,
703 SYSIO_IMAP_KBD,
704 SYSIO_IMAP_MS,
705 SYSIO_IMAP_SER,
706 bogon,
707 bogon,
708 SYSIO_IMAP_TIM0,
709 SYSIO_IMAP_TIM1,
710 bogon,
711 bogon,
712 SYSIO_IMAP_UE,
713 SYSIO_IMAP_CE,
714 SYSIO_IMAP_SBERR,
715 SYSIO_IMAP_PMGMT,
716 };
717
718 #undef bogon
719
720 #define NUM_SYSIO_OFFSETS (sizeof(sysio_irq_offsets) / sizeof(sysio_irq_offsets[0]))
721
722 /* Convert Interrupt Mapping register pointer to assosciated
723 * Interrupt Clear register pointer, SYSIO specific version.
724 */
725 #define SYSIO_ICLR_UNUSED0 0x3400UL
726 #define SYSIO_ICLR_SLOT0 0x340cUL
727 #define SYSIO_ICLR_SLOT1 0x344cUL
728 #define SYSIO_ICLR_SLOT2 0x348cUL
729 #define SYSIO_ICLR_SLOT3 0x34ccUL
730 static unsigned long sysio_imap_to_iclr(unsigned long imap)
731 {
732 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
733 return imap + diff;
734 }
735
736 unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
737 {
738 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
739 struct sbus_iommu *iommu = sbus->iommu;
740 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
741 unsigned long imap, iclr;
742 int pil, sbus_level = 0;
743
744 pil = sysio_ino_to_pil[ino];
745 if (!pil) {
746 printk("sbus_irq_build: Bad SYSIO INO[%x]\n", ino);
747 panic("Bad SYSIO IRQ translations...");
748 }
749 imap = sysio_irq_offsets[ino];
750 if (imap == ((unsigned long)-1)) {
751 prom_printf("get_irq_translations: Bad SYSIO INO[%x] cpu[%d]\n",
752 ino, pil);
753 prom_halt();
754 }
755 imap += reg_base;
756
757 /* SYSIO inconsistancy. For external SLOTS, we have to select
758 * the right ICLR register based upon the lower SBUS irq level
759 * bits.
760 */
761 if (ino >= 0x20) {
762 iclr = sysio_imap_to_iclr(imap);
763 } else {
764 int sbus_slot = (ino & 0x18)>>3;
765
766 sbus_level = ino & 0x7;
767
768 switch(sbus_slot) {
769 case 0:
770 iclr = reg_base + SYSIO_ICLR_SLOT0;
771 break;
772 case 1:
773 iclr = reg_base + SYSIO_ICLR_SLOT1;
774 break;
775 case 2:
776 iclr = reg_base + SYSIO_ICLR_SLOT2;
777 break;
778 default:
779 case 3:
780 iclr = reg_base + SYSIO_ICLR_SLOT3;
781 break;
782 };
783
784 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
785 }
786 return build_irq(pil, sbus_level, iclr, imap);
787 }
788
789 /* Error interrupt handling. */
790 #define SYSIO_UE_AFSR 0x0030UL
791 #define SYSIO_UE_AFAR 0x0038UL
792 #define SYSIO_UEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
793 #define SYSIO_UEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
794 #define SYSIO_UEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
795 #define SYSIO_UEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
796 #define SYSIO_UEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
797 #define SYSIO_UEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
798 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000 /* Reserved */
799 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000 /* Doubleword Offset */
800 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000 /* Bad transfer size is 2**SIZE */
801 #define SYSIO_UEAFSR_MID 0x000003e000000000 /* UPA MID causing the fault */
802 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffff /* Reserved */
803 static void sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
804 {
805 struct sbus_bus *sbus = dev_id;
806 struct sbus_iommu *iommu = sbus->iommu;
807 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
808 unsigned long afsr_reg, afar_reg;
809 unsigned long afsr, afar, error_bits;
810 int reported;
811
812 afsr_reg = reg_base + SYSIO_UE_AFSR;
813 afar_reg = reg_base + SYSIO_UE_AFAR;
814
815 /* Latch error status. */
816 afsr = upa_readq(afsr_reg);
817 afar = upa_readq(afar_reg);
818
819 /* Clear primary/secondary error status bits. */
820 error_bits = afsr &
821 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
822 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
823 upa_writeq(error_bits, afsr_reg);
824
825 /* Log the error. */
826 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
827 sbus->portid,
828 (((error_bits & SYSIO_UEAFSR_PPIO) ?
829 "PIO" :
830 ((error_bits & SYSIO_UEAFSR_PDRD) ?
831 "DVMA Read" :
832 ((error_bits & SYSIO_UEAFSR_PDWR) ?
833 "DVMA Write" : "???")))));
834 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
835 sbus->portid,
836 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
837 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
838 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
839 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
840 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
841 reported = 0;
842 if (afsr & SYSIO_UEAFSR_SPIO) {
843 reported++;
844 printk("(PIO)");
845 }
846 if (afsr & SYSIO_UEAFSR_SDRD) {
847 reported++;
848 printk("(DVMA Read)");
849 }
850 if (afsr & SYSIO_UEAFSR_SDWR) {
851 reported++;
852 printk("(DVMA Write)");
853 }
854 if (!reported)
855 printk("(none)");
856 printk("]\n");
857 }
858
859 #define SYSIO_CE_AFSR 0x0040UL
860 #define SYSIO_CE_AFAR 0x0048UL
861 #define SYSIO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
862 #define SYSIO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
863 #define SYSIO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
864 #define SYSIO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
865 #define SYSIO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
866 #define SYSIO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
867 #define SYSIO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */
868 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */
869 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000 /* Double Offset */
870 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000 /* Bad transfer size is 2**SIZE */
871 #define SYSIO_CEAFSR_MID 0x000003e000000000 /* UPA MID causing the fault */
872 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffff /* Reserved */
873 static void sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
874 {
875 struct sbus_bus *sbus = dev_id;
876 struct sbus_iommu *iommu = sbus->iommu;
877 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
878 unsigned long afsr_reg, afar_reg;
879 unsigned long afsr, afar, error_bits;
880 int reported;
881
882 afsr_reg = reg_base + SYSIO_CE_AFSR;
883 afar_reg = reg_base + SYSIO_CE_AFAR;
884
885 /* Latch error status. */
886 afsr = upa_readq(afsr_reg);
887 afar = upa_readq(afar_reg);
888
889 /* Clear primary/secondary error status bits. */
890 error_bits = afsr &
891 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
892 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
893 upa_writeq(error_bits, afsr_reg);
894
895 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
896 sbus->portid,
897 (((error_bits & SYSIO_CEAFSR_PPIO) ?
898 "PIO" :
899 ((error_bits & SYSIO_CEAFSR_PDRD) ?
900 "DVMA Read" :
901 ((error_bits & SYSIO_CEAFSR_PDWR) ?
902 "DVMA Write" : "???")))));
903
904 /* XXX Use syndrome and afar to print out module string just like
905 * XXX UDB CE trap handler does... -DaveM
906 */
907 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
908 sbus->portid,
909 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
910 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
911 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
912 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
913 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
914
915 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
916 reported = 0;
917 if (afsr & SYSIO_CEAFSR_SPIO) {
918 reported++;
919 printk("(PIO)");
920 }
921 if (afsr & SYSIO_CEAFSR_SDRD) {
922 reported++;
923 printk("(DVMA Read)");
924 }
925 if (afsr & SYSIO_CEAFSR_SDWR) {
926 reported++;
927 printk("(DVMA Write)");
928 }
929 if (!reported)
930 printk("(none)");
931 printk("]\n");
932 }
933
934 #define SYSIO_SBUS_AFSR 0x2010UL
935 #define SYSIO_SBUS_AFAR 0x2018UL
936 #define SYSIO_SBAFSR_PLE 0x8000000000000000 /* Primary Late PIO Error */
937 #define SYSIO_SBAFSR_PTO 0x4000000000000000 /* Primary SBUS Timeout */
938 #define SYSIO_SBAFSR_PBERR 0x2000000000000000 /* Primary SBUS Error ACK */
939 #define SYSIO_SBAFSR_SLE 0x1000000000000000 /* Secondary Late PIO Error */
940 #define SYSIO_SBAFSR_STO 0x0800000000000000 /* Secondary SBUS Timeout */
941 #define SYSIO_SBAFSR_SBERR 0x0400000000000000 /* Secondary SBUS Error ACK */
942 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000 /* Reserved */
943 #define SYSIO_SBAFSR_RD 0x0000800000000000 /* Primary was late PIO read */
944 #define SYSIO_SBAFSR_RESV2 0x0000600000000000 /* Reserved */
945 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000 /* Size of transfer */
946 #define SYSIO_SBAFSR_MID 0x000003e000000000 /* MID causing the error */
947 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffff /* Reserved */
948 static void sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
949 {
950 struct sbus_bus *sbus = dev_id;
951 struct sbus_iommu *iommu = sbus->iommu;
952 unsigned long afsr_reg, afar_reg, reg_base;
953 unsigned long afsr, afar, error_bits;
954 int reported;
955
956 reg_base = iommu->sbus_control_reg - 0x2000UL;
957 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
958 afar_reg = reg_base + SYSIO_SBUS_AFAR;
959
960 afsr = upa_readq(afsr_reg);
961 afar = upa_readq(afar_reg);
962
963 /* Clear primary/secondary error status bits. */
964 error_bits = afsr &
965 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
966 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
967 upa_writeq(error_bits, afsr_reg);
968
969 /* Log the error. */
970 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
971 sbus->portid,
972 (((error_bits & SYSIO_SBAFSR_PLE) ?
973 "Late PIO Error" :
974 ((error_bits & SYSIO_SBAFSR_PTO) ?
975 "Time Out" :
976 ((error_bits & SYSIO_SBAFSR_PBERR) ?
977 "Error Ack" : "???")))),
978 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
979 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
980 sbus->portid,
981 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
982 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
983 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
984 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
985 reported = 0;
986 if (afsr & SYSIO_SBAFSR_SLE) {
987 reported++;
988 printk("(Late PIO Error)");
989 }
990 if (afsr & SYSIO_SBAFSR_STO) {
991 reported++;
992 printk("(Time Out)");
993 }
994 if (afsr & SYSIO_SBAFSR_SBERR) {
995 reported++;
996 printk("(Error Ack)");
997 }
998 if (!reported)
999 printk("(none)");
1000 printk("]\n");
1001
1002 /* XXX check iommu/strbuf for further error status XXX */
1003 }
1004
1005 #define ECC_CONTROL 0x0020UL
1006 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000 /* Enable ECC Checking */
1007 #define SYSIO_ECNTRL_UEEN 0x4000000000000000 /* Enable UE Interrupts */
1008 #define SYSIO_ECNTRL_CEEN 0x2000000000000000 /* Enable CE Interrupts */
1009
1010 #define SYSIO_UE_INO 0x34
1011 #define SYSIO_CE_INO 0x35
1012 #define SYSIO_SBUSERR_INO 0x36
1013
1014 static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
1015 {
1016 struct sbus_iommu *iommu = sbus->iommu;
1017 unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
1018 unsigned int irq;
1019 u64 control;
1020
1021 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
1022 if (request_irq(irq, sysio_ue_handler,
1023 SA_SHIRQ, "SYSIO UE", sbus) < 0) {
1024 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
1025 sbus->portid);
1026 prom_halt();
1027 }
1028
1029 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
1030 if (request_irq(irq, sysio_ce_handler,
1031 SA_SHIRQ, "SYSIO CE", sbus) < 0) {
1032 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
1033 sbus->portid);
1034 prom_halt();
1035 }
1036
1037 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
1038 if (request_irq(irq, sysio_sbus_error_handler,
1039 SA_SHIRQ, "SYSIO SBUS Error", sbus) < 0) {
1040 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
1041 sbus->portid);
1042 prom_halt();
1043 }
1044
1045 /* Now turn the error interrupts on and also enable ECC checking. */
1046 upa_writeq((SYSIO_ECNTRL_ECCEN |
1047 SYSIO_ECNTRL_UEEN |
1048 SYSIO_ECNTRL_CEEN),
1049 reg_base + ECC_CONTROL);
1050
1051 control = upa_readq(iommu->sbus_control_reg);
1052 control |= 0x100UL; /* SBUS Error Interrupt Enable */
1053 upa_writeq(control, iommu->sbus_control_reg);
1054 }
1055
1056 /* Boot time initialization. */
1057 void __init sbus_iommu_init(int prom_node, struct sbus_bus *sbus)
1058 {
1059 struct linux_prom64_registers rprop;
1060 struct sbus_iommu *iommu;
1061 unsigned long regs, tsb_base;
1062 u64 control;
1063 int err, i;
1064
1065 sbus->portid = prom_getintdefault(sbus->prom_node,
1066 "upa-portid", -1);
1067
1068 err = prom_getproperty(prom_node, "reg",
1069 (char *)&rprop, sizeof(rprop));
1070 if (err < 0) {
1071 prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n");
1072 prom_halt();
1073 }
1074 regs = rprop.phys_addr;
1075
1076 iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
1077 if (iommu == NULL) {
1078 prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
1079 prom_halt();
1080 }
1081
1082 /* Align on E$ line boundry. */
1083 iommu = (struct sbus_iommu *)
1084 (((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
1085 ~(SMP_CACHE_BYTES - 1UL));
1086
1087 memset(iommu, 0, sizeof(*iommu));
1088
1089 /* We start with no consistent mappings. */
1090 iommu->lowest_consistent_map = CLUSTER_NPAGES;
1091
1092 for (i = 0; i < NCLUSTERS; i++) {
1093 iommu->alloc_info[i].flush = 0;
1094 iommu->alloc_info[i].next = 0;
1095 }
1096
1097 /* Setup spinlock. */
1098 spin_lock_init(&iommu->lock);
1099
1100 /* Init register offsets. */
1101 iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
1102 iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
1103
1104 /* The SYSIO SBUS control register is used for dummy reads
1105 * in order to ensure write completion.
1106 */
1107 iommu->sbus_control_reg = regs + 0x2000UL;
1108
1109 /* Link into SYSIO software state. */
1110 sbus->iommu = iommu;
1111
1112 printk("SYSIO: UPA portID %x, at %016lx\n",
1113 sbus->portid, regs);
1114
1115 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
1116 control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
1117 control = ((7UL << 16UL) |
1118 (0UL << 2UL) |
1119 (1UL << 1UL) |
1120 (1UL << 0UL));
1121
1122 /* Using the above configuration we need 1MB iommu page
1123 * table (128K ioptes * 8 bytes per iopte). This is
1124 * page order 7 on UltraSparc.
1125 */
1126 tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
1127 if (tsb_base == 0UL) {
1128 prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
1129 prom_halt();
1130 }
1131
1132 iommu->page_table = (iopte_t *) tsb_base;
1133 memset(iommu->page_table, 0, IO_TSB_SIZE);
1134
1135 upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
1136
1137 /* Clean out any cruft in the IOMMU using
1138 * diagnostic accesses.
1139 */
1140 for (i = 0; i < 16; i++) {
1141 unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
1142 unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
1143
1144 dram += (unsigned long)i * 8UL;
1145 tag += (unsigned long)i * 8UL;
1146 upa_writeq(0, dram);
1147 upa_writeq(0, tag);
1148 }
1149 upa_readq(iommu->sbus_control_reg);
1150
1151 /* Give the TSB to SYSIO. */
1152 upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
1153
1154 /* Setup streaming buffer, DE=1 SB_EN=1 */
1155 control = (1UL << 1UL) | (1UL << 0UL);
1156 upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
1157
1158 /* Clear out the tags using diagnostics. */
1159 for (i = 0; i < 16; i++) {
1160 unsigned long ptag, ltag;
1161
1162 ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
1163 ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
1164 ptag += (unsigned long)i * 8UL;
1165 ltag += (unsigned long)i * 8UL;
1166
1167 upa_writeq(0UL, ptag);
1168 upa_writeq(0UL, ltag);
1169 }
1170
1171 /* Enable DVMA arbitration for all devices/slots. */
1172 control = upa_readq(iommu->sbus_control_reg);
1173 control |= 0x3fUL;
1174 upa_writeq(control, iommu->sbus_control_reg);
1175
1176 /* Now some Xfire specific grot... */
1177 if (this_is_starfire)
1178 sbus->starfire_cookie = starfire_hookup(sbus->portid);
1179 else
1180 sbus->starfire_cookie = NULL;
1181
1182 sysio_register_error_handlers(sbus);
1183 }
1184