File: /usr/src/linux/arch/sparc64/kernel/smp.c
1 /* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/mm.h>
9 #include <linux/pagemap.h>
10 #include <linux/threads.h>
11 #include <linux/smp.h>
12 #include <linux/smp_lock.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18
19 #include <asm/head.h>
20 #include <asm/ptrace.h>
21 #include <asm/atomic.h>
22
23 #include <asm/irq.h>
24 #include <asm/page.h>
25 #include <asm/pgtable.h>
26 #include <asm/oplib.h>
27 #include <asm/hardirq.h>
28 #include <asm/softirq.h>
29 #include <asm/uaccess.h>
30 #include <asm/timer.h>
31 #include <asm/starfire.h>
32
33 #define __KERNEL_SYSCALLS__
34 #include <linux/unistd.h>
35
36 extern int linux_num_cpus;
37 extern void calibrate_delay(void);
38 extern unsigned prom_cpu_nodes[];
39
40 struct cpuinfo_sparc cpu_data[NR_CPUS] __attribute__ ((aligned (64)));
41
42 volatile int __cpu_number_map[NR_CPUS] __attribute__ ((aligned (64)));
43 volatile int __cpu_logical_map[NR_CPUS] __attribute__ ((aligned (64)));
44
45 /* Please don't make this stuff initdata!!! --DaveM */
46 static unsigned char boot_cpu_id = 0;
47 static int smp_activated = 0;
48
49 /* Kernel spinlock */
50 spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED;
51
52 volatile int smp_processors_ready = 0;
53 unsigned long cpu_present_map = 0;
54 int smp_num_cpus = 1;
55 int smp_threads_ready = 0;
56
57 void __init smp_setup(char *str, int *ints)
58 {
59 /* XXX implement me XXX */
60 }
61
62 static int max_cpus = NR_CPUS;
63 static int __init maxcpus(char *str)
64 {
65 get_option(&str, &max_cpus);
66 return 1;
67 }
68
69 __setup("maxcpus=", maxcpus);
70
71 int smp_info(char *buf)
72 {
73 int len = 7, i;
74
75 strcpy(buf, "State:\n");
76 for (i = 0; i < NR_CPUS; i++)
77 if (cpu_present_map & (1UL << i))
78 len += sprintf(buf + len,
79 "CPU%d:\t\tonline\n", i);
80 return len;
81 }
82
83 int smp_bogo(char *buf)
84 {
85 int len = 0, i;
86
87 for (i = 0; i < NR_CPUS; i++)
88 if (cpu_present_map & (1UL << i))
89 len += sprintf(buf + len,
90 "Cpu%dBogo\t: %lu.%02lu\n"
91 "Cpu%dClkTck\t: %016lx\n",
92 i, cpu_data[i].udelay_val / (500000/HZ),
93 (cpu_data[i].udelay_val / (5000/HZ)) % 100,
94 i, cpu_data[i].clock_tick);
95 return len;
96 }
97
98 void __init smp_store_cpu_info(int id)
99 {
100 int i, no;
101
102 /* multiplier and counter set by
103 smp_setup_percpu_timer() */
104 cpu_data[id].udelay_val = loops_per_jiffy;
105
106 for (no = 0; no < linux_num_cpus; no++)
107 if (linux_cpus[no].mid == id)
108 break;
109
110 cpu_data[id].clock_tick = prom_getintdefault(linux_cpus[no].prom_node,
111 "clock-frequency", 0);
112
113 cpu_data[id].pgcache_size = 0;
114 cpu_data[id].pte_cache[0] = NULL;
115 cpu_data[id].pte_cache[1] = NULL;
116 cpu_data[id].pgdcache_size = 0;
117 cpu_data[id].pgd_cache = NULL;
118 cpu_data[id].idle_volume = 1;
119
120 for (i = 0; i < 16; i++)
121 cpu_data[id].irq_worklists[i] = 0;
122 }
123
124 void __init smp_commence(void)
125 {
126 }
127
128 static void smp_setup_percpu_timer(void);
129
130 static volatile unsigned long callin_flag = 0;
131
132 extern void inherit_locked_prom_mappings(int save_p);
133 extern void cpu_probe(void);
134
135 void __init smp_callin(void)
136 {
137 int cpuid = hard_smp_processor_id();
138 unsigned long pstate;
139
140 inherit_locked_prom_mappings(0);
141
142 __flush_cache_all();
143 __flush_tlb_all();
144
145 cpu_probe();
146
147 /* Guarentee that the following sequences execute
148 * uninterrupted.
149 */
150 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
151 "wrpr %0, %1, %%pstate"
152 : "=r" (pstate)
153 : "i" (PSTATE_IE));
154
155 /* Set things up so user can access tick register for profiling
156 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
157 * read back of %tick after writing it.
158 */
159 __asm__ __volatile__("
160 sethi %%hi(0x80000000), %%g1
161 ba,pt %%xcc, 1f
162 sllx %%g1, 32, %%g1
163 .align 64
164 1: rd %%tick, %%g2
165 add %%g2, 6, %%g2
166 andn %%g2, %%g1, %%g2
167 wrpr %%g2, 0, %%tick
168 rdpr %%tick, %%g0"
169 : /* no outputs */
170 : /* no inputs */
171 : "g1", "g2");
172
173 if (SPARC64_USE_STICK) {
174 /* Let the user get at STICK too. */
175 __asm__ __volatile__("
176 sethi %%hi(0x80000000), %%g1
177 sllx %%g1, 32, %%g1
178 rd %%asr24, %%g2
179 andn %%g2, %%g1, %%g2
180 wr %%g2, 0, %%asr24"
181 : /* no outputs */
182 : /* no inputs */
183 : "g1", "g2");
184 }
185
186 /* Restore PSTATE_IE. */
187 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
188 : /* no outputs */
189 : "r" (pstate));
190
191 smp_setup_percpu_timer();
192
193 __sti();
194
195 calibrate_delay();
196 smp_store_cpu_info(cpuid);
197 callin_flag = 1;
198 __asm__ __volatile__("membar #Sync\n\t"
199 "flush %%g6" : : : "memory");
200
201 /* Clear this or we will die instantly when we
202 * schedule back to this idler...
203 */
204 current->thread.flags &= ~(SPARC_FLAG_NEWCHILD);
205
206 /* Attach to the address space of init_task. */
207 atomic_inc(&init_mm.mm_count);
208 current->active_mm = &init_mm;
209
210 while (!smp_processors_ready)
211 membar("#LoadLoad");
212 }
213
214 extern int cpu_idle(void);
215 extern void init_IRQ(void);
216
217 void initialize_secondary(void)
218 {
219 }
220
221 int start_secondary(void *unused)
222 {
223 trap_init();
224 init_IRQ();
225 smp_callin();
226 return cpu_idle();
227 }
228
229 void cpu_panic(void)
230 {
231 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
232 panic("SMP bolixed\n");
233 }
234
235 extern struct prom_cpuinfo linux_cpus[64];
236
237 extern unsigned long sparc64_cpu_startup;
238
239 /* The OBP cpu startup callback truncates the 3rd arg cookie to
240 * 32-bits (I think) so to be safe we have it read the pointer
241 * contained here so we work on >4GB machines. -DaveM
242 */
243 static struct task_struct *cpu_new_task = NULL;
244
245 void __init smp_boot_cpus(void)
246 {
247 int cpucount = 0, i;
248
249 printk("Entering UltraSMPenguin Mode...\n");
250 __sti();
251 smp_store_cpu_info(boot_cpu_id);
252 init_idle();
253
254 if (linux_num_cpus == 1)
255 return;
256
257 for (i = 0; i < NR_CPUS; i++) {
258 if (i == boot_cpu_id)
259 continue;
260
261 if ((cpucount + 1) == max_cpus)
262 break;
263 if (cpu_present_map & (1UL << i)) {
264 unsigned long entry = (unsigned long)(&sparc64_cpu_startup);
265 unsigned long cookie = (unsigned long)(&cpu_new_task);
266 struct task_struct *p;
267 int timeout;
268 int no;
269
270 prom_printf("Starting CPU %d... ", i);
271 kernel_thread(start_secondary, NULL, CLONE_PID);
272 cpucount++;
273
274 p = init_task.prev_task;
275 init_tasks[cpucount] = p;
276
277 p->processor = i;
278 p->has_cpu = 1; /* we schedule the first task manually */
279
280 del_from_runqueue(p);
281 unhash_process(p);
282
283 callin_flag = 0;
284 for (no = 0; no < linux_num_cpus; no++)
285 if (linux_cpus[no].mid == i)
286 break;
287 cpu_new_task = p;
288 prom_startcpu(linux_cpus[no].prom_node,
289 entry, cookie);
290 for (timeout = 0; timeout < 5000000; timeout++) {
291 if (callin_flag)
292 break;
293 udelay(100);
294 }
295 if (callin_flag) {
296 __cpu_number_map[i] = cpucount;
297 __cpu_logical_map[cpucount] = i;
298 prom_cpu_nodes[i] = linux_cpus[no].prom_node;
299 prom_printf("OK\n");
300 } else {
301 cpucount--;
302 printk("Processor %d is stuck.\n", i);
303 prom_printf("FAILED\n");
304 }
305 }
306 if (!callin_flag) {
307 cpu_present_map &= ~(1UL << i);
308 __cpu_number_map[i] = -1;
309 }
310 }
311 cpu_new_task = NULL;
312 if (cpucount == 0) {
313 printk("Error: only one processor found.\n");
314 cpu_present_map = (1UL << smp_processor_id());
315 } else {
316 unsigned long bogosum = 0;
317
318 for (i = 0; i < NR_CPUS; i++) {
319 if (cpu_present_map & (1UL << i))
320 bogosum += cpu_data[i].udelay_val;
321 }
322 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
323 cpucount + 1,
324 bogosum/(500000/HZ),
325 (bogosum/(5000/HZ))%100);
326 smp_activated = 1;
327 smp_num_cpus = cpucount + 1;
328 }
329 smp_processors_ready = 1;
330 membar("#StoreStore | #StoreLoad");
331 }
332
333 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
334 {
335 u64 result, target;
336 int stuck, tmp;
337
338 if (this_is_starfire) {
339 /* map to real upaid */
340 cpu = (((cpu & 0x3c) << 1) |
341 ((cpu & 0x40) >> 4) |
342 (cpu & 0x3));
343 }
344
345 target = (cpu << 14) | 0x70;
346 again:
347 /* Ok, this is the real Spitfire Errata #54.
348 * One must read back from a UDB internal register
349 * after writes to the UDB interrupt dispatch, but
350 * before the membar Sync for that write.
351 * So we use the high UDB control register (ASI 0x7f,
352 * ADDR 0x20) for the dummy read. -DaveM
353 */
354 tmp = 0x40;
355 __asm__ __volatile__("
356 wrpr %1, %2, %%pstate
357 stxa %4, [%0] %3
358 stxa %5, [%0+%8] %3
359 add %0, %8, %0
360 stxa %6, [%0+%8] %3
361 membar #Sync
362 stxa %%g0, [%7] %3
363 membar #Sync
364 mov 0x20, %%g1
365 ldxa [%%g1] 0x7f, %%g0
366 membar #Sync"
367 : "=r" (tmp)
368 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
369 "r" (data0), "r" (data1), "r" (data2), "r" (target), "r" (0x10), "0" (tmp)
370 : "g1");
371
372 /* NOTE: PSTATE_IE is still clear. */
373 stuck = 100000;
374 do {
375 __asm__ __volatile__("ldxa [%%g0] %1, %0"
376 : "=r" (result)
377 : "i" (ASI_INTR_DISPATCH_STAT));
378 if (result == 0) {
379 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
380 : : "r" (pstate));
381 return;
382 }
383 stuck -= 1;
384 if (stuck == 0)
385 break;
386 } while (result & 0x1);
387 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
388 : : "r" (pstate));
389 if (stuck == 0) {
390 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
391 smp_processor_id(), result);
392 } else {
393 udelay(2);
394 goto again;
395 }
396 }
397
398 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, unsigned long mask)
399 {
400 int ncpus = smp_num_cpus - 1;
401 int i;
402 u64 pstate;
403
404 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
405 for (i = 0; (i < NR_CPUS) && ncpus; i++) {
406 if (mask & (1UL << i)) {
407 spitfire_xcall_helper(data0, data1, data2, pstate, i);
408 ncpus--;
409 }
410 }
411 }
412
413 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
414 * packet, but we have no use for that. However we do take advantage of
415 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
416 */
417 #if NR_CPUS > 32
418 #error Fixup cheetah_xcall_deliver Dave...
419 #endif
420 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, unsigned long mask)
421 {
422 u64 pstate;
423 int nack_busy_id;
424
425 if (!mask)
426 return;
427
428 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
429
430 retry:
431 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
432 : : "r" (pstate), "i" (PSTATE_IE));
433
434 /* Setup the dispatch data registers. */
435 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
436 "stxa %1, [%4] %6\n\t"
437 "stxa %2, [%5] %6\n\t"
438 "membar #Sync\n\t"
439 : /* no outputs */
440 : "r" (data0), "r" (data1), "r" (data2),
441 "r" (0x40), "r" (0x50), "r" (0x60),
442 "i" (ASI_INTR_W));
443
444 nack_busy_id = 0;
445 {
446 int i, ncpus = smp_num_cpus - 1;
447
448 for (i = 0; (i < NR_CPUS) && ncpus; i++) {
449 if (mask & (1UL << i)) {
450 u64 target = (i << 14) | 0x70;
451
452 target |= (nack_busy_id++ << 24);
453 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
454 "membar #Sync\n\t"
455 : /* no outputs */
456 : "r" (target), "i" (ASI_INTR_W));
457 ncpus--;
458 }
459 }
460 }
461
462 /* Now, poll for completion. */
463 {
464 u64 dispatch_stat;
465 long stuck;
466
467 stuck = 100000 * nack_busy_id;
468 do {
469 __asm__ __volatile__("ldxa [%%g0] %1, %0"
470 : "=r" (dispatch_stat)
471 : "i" (ASI_INTR_DISPATCH_STAT));
472 if (dispatch_stat == 0UL) {
473 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
474 : : "r" (pstate));
475 return;
476 }
477 if (!--stuck)
478 break;
479 } while (dispatch_stat & 0x5555555555555555UL);
480
481 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
482 : : "r" (pstate));
483
484 if ((stuck & ~(0x5555555555555555UL)) == 0) {
485 /* Busy bits will not clear, continue instead
486 * of freezing up on this cpu.
487 */
488 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
489 smp_processor_id(), dispatch_stat);
490 } else {
491 int i, this_busy_nack = 0;
492
493 /* Delay some random time with interrupts enabled
494 * to prevent deadlock.
495 */
496 udelay(2 * nack_busy_id);
497
498 /* Clear out the mask bits for cpus which did not
499 * NACK us.
500 */
501 for (i = 0; i < NR_CPUS; i++) {
502 if (mask & (1UL << i)) {
503 if ((dispatch_stat & (0x2 << this_busy_nack)) == 0)
504 mask &= ~(1UL << i);
505 this_busy_nack += 2;
506 }
507 }
508
509 goto retry;
510 }
511 }
512 }
513
514 /* Send cross call to all processors mentioned in MASK
515 * except self.
516 */
517 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, unsigned long mask)
518 {
519 if (smp_processors_ready) {
520 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
521
522 mask &= ~(1UL<<smp_processor_id());
523
524 if (tlb_type == spitfire)
525 spitfire_xcall_deliver(data0, data1, data2, mask);
526 else
527 cheetah_xcall_deliver(data0, data1, data2, mask);
528
529 /* NOTE: Caller runs local copy on master. */
530 }
531 }
532
533 /* Send cross call to all processors except self. */
534 #define smp_cross_call(func, ctx, data1, data2) \
535 smp_cross_call_masked(func, ctx, data1, data2, cpu_present_map)
536
537 struct call_data_struct {
538 void (*func) (void *info);
539 void *info;
540 atomic_t finished;
541 int wait;
542 };
543
544 extern unsigned long xcall_call_function;
545
546 int smp_call_function(void (*func)(void *info), void *info,
547 int nonatomic, int wait)
548 {
549 struct call_data_struct data;
550 int cpus = smp_num_cpus - 1;
551
552 if (!cpus)
553 return 0;
554
555 data.func = func;
556 data.info = info;
557 atomic_set(&data.finished, 0);
558 data.wait = wait;
559
560 smp_cross_call(&xcall_call_function,
561 0, (u64) &data, 0);
562 if (wait) {
563 while (atomic_read(&data.finished) != cpus)
564 barrier();
565 }
566
567 return 0;
568 }
569
570 void smp_call_function_client(struct call_data_struct *call_data)
571 {
572 call_data->func(call_data->info);
573 if (call_data->wait)
574 atomic_inc(&call_data->finished);
575 }
576
577 extern unsigned long xcall_flush_tlb_page;
578 extern unsigned long xcall_flush_tlb_mm;
579 extern unsigned long xcall_flush_tlb_range;
580 extern unsigned long xcall_flush_tlb_all;
581 extern unsigned long xcall_tlbcachesync;
582 extern unsigned long xcall_flush_cache_all;
583 extern unsigned long xcall_report_regs;
584 extern unsigned long xcall_receive_signal;
585
586 void smp_receive_signal(int cpu)
587 {
588 if (smp_processors_ready) {
589 unsigned long mask = 1UL << cpu;
590
591 if ((cpu_present_map & mask) != 0) {
592 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
593
594 if (tlb_type == spitfire)
595 spitfire_xcall_deliver(data0, 0, 0, mask);
596 else
597 cheetah_xcall_deliver(data0, 0, 0, mask);
598 }
599 }
600 }
601
602 void smp_report_regs(void)
603 {
604 smp_cross_call(&xcall_report_regs, 0, 0, 0);
605 }
606
607 void smp_flush_cache_all(void)
608 {
609 smp_cross_call(&xcall_flush_cache_all, 0, 0, 0);
610 __flush_cache_all();
611 }
612
613 void smp_flush_tlb_all(void)
614 {
615 smp_cross_call(&xcall_flush_tlb_all, 0, 0, 0);
616 __flush_tlb_all();
617 }
618
619 /* We know that the window frames of the user have been flushed
620 * to the stack before we get here because all callers of us
621 * are flush_tlb_*() routines, and these run after flush_cache_*()
622 * which performs the flushw.
623 *
624 * The SMP TLB coherency scheme we use works as follows:
625 *
626 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
627 * space has (potentially) executed on, this is the heuristic
628 * we use to avoid doing cross calls.
629 *
630 * Also, for flushing from kswapd and also for clones, we
631 * use cpu_vm_mask as the list of cpus to make run the TLB.
632 *
633 * 2) TLB context numbers are shared globally across all processors
634 * in the system, this allows us to play several games to avoid
635 * cross calls.
636 *
637 * One invariant is that when a cpu switches to a process, and
638 * that processes tsk->active_mm->cpu_vm_mask does not have the
639 * current cpu's bit set, that tlb context is flushed locally.
640 *
641 * If the address space is non-shared (ie. mm->count == 1) we avoid
642 * cross calls when we want to flush the currently running process's
643 * tlb state. This is done by clearing all cpu bits except the current
644 * processor's in current->active_mm->cpu_vm_mask and performing the
645 * flush locally only. This will force any subsequent cpus which run
646 * this task to flush the context from the local tlb if the process
647 * migrates to another cpu (again).
648 *
649 * 3) For shared address spaces (threads) and swapping we bite the
650 * bullet for most cases and perform the cross call (but only to
651 * the cpus listed in cpu_vm_mask).
652 *
653 * The performance gain from "optimizing" away the cross call for threads is
654 * questionable (in theory the big win for threads is the massive sharing of
655 * address space state across processors).
656 */
657 void smp_flush_tlb_mm(struct mm_struct *mm)
658 {
659 /*
660 * This code is called from two places, dup_mmap and exit_mmap. In the
661 * former case, we really need a flush. In the later case, the callers
662 * are single threaded exec_mmap (really need a flush), multithreaded
663 * exec_mmap case (do not need to flush, since the caller gets a new
664 * context via activate_mm), and all other callers of mmput() whence
665 * the flush can be optimized since the associated threads are dead and
666 * the mm is being torn down (__exit_mm and other mmput callers) or the
667 * owning thread is dissociating itself from the mm. The
668 * (atomic_read(&mm->mm_users) == 0) check ensures real work is done
669 * for single thread exec and dup_mmap cases. An alternate check might
670 * have been (current->mm != mm).
671 * Kanoj Sarcar
672 */
673 if (atomic_read(&mm->mm_users) == 0)
674 return;
675
676 {
677 u32 ctx = CTX_HWBITS(mm->context);
678 int cpu = smp_processor_id();
679
680 if (atomic_read(&mm->mm_users) == 1) {
681 /* See smp_flush_tlb_page for info about this. */
682 mm->cpu_vm_mask = (1UL << cpu);
683 goto local_flush_and_out;
684 }
685
686 smp_cross_call_masked(&xcall_flush_tlb_mm,
687 ctx, 0, 0,
688 mm->cpu_vm_mask);
689
690 local_flush_and_out:
691 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
692 }
693 }
694
695 void smp_flush_tlb_range(struct mm_struct *mm, unsigned long start,
696 unsigned long end)
697 {
698 {
699 u32 ctx = CTX_HWBITS(mm->context);
700 int cpu = smp_processor_id();
701
702 start &= PAGE_MASK;
703 end = PAGE_ALIGN(end);
704
705 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) {
706 mm->cpu_vm_mask = (1UL << cpu);
707 goto local_flush_and_out;
708 }
709
710 smp_cross_call_masked(&xcall_flush_tlb_range,
711 ctx, start, end,
712 mm->cpu_vm_mask);
713
714 local_flush_and_out:
715 __flush_tlb_range(ctx, start, SECONDARY_CONTEXT, end, PAGE_SIZE, (end-start));
716 }
717 }
718
719 void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page)
720 {
721 {
722 u32 ctx = CTX_HWBITS(mm->context);
723 int cpu = smp_processor_id();
724
725 page &= PAGE_MASK;
726 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) {
727 /* By virtue of being the current address space, and
728 * having the only reference to it, the following operation
729 * is safe.
730 *
731 * It would not be a win to perform the xcall tlb flush in
732 * this case, because even if we switch back to one of the
733 * other processors in cpu_vm_mask it is almost certain that
734 * all TLB entries for this context will be replaced by the
735 * time that happens.
736 */
737 mm->cpu_vm_mask = (1UL << cpu);
738 goto local_flush_and_out;
739 } else {
740 /* By virtue of running under the mm->page_table_lock,
741 * and mmu_context.h:switch_mm doing the same, the following
742 * operation is safe.
743 */
744 if (mm->cpu_vm_mask == (1UL << cpu))
745 goto local_flush_and_out;
746 }
747
748 /* OK, we have to actually perform the cross call. Most likely
749 * this is a cloned mm or kswapd is kicking out pages for a task
750 * which has run recently on another cpu.
751 */
752 smp_cross_call_masked(&xcall_flush_tlb_page,
753 ctx, page, 0,
754 mm->cpu_vm_mask);
755 if (!(mm->cpu_vm_mask & (1UL << cpu)))
756 return;
757
758 local_flush_and_out:
759 __flush_tlb_page(ctx, page, SECONDARY_CONTEXT);
760 }
761 }
762
763 /* CPU capture. */
764 /* #define CAPTURE_DEBUG */
765 extern unsigned long xcall_capture;
766
767 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
768 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
769 static unsigned long penguins_are_doing_time = 0;
770
771 void smp_capture(void)
772 {
773 if (smp_processors_ready) {
774 int result = __atomic_add(1, &smp_capture_depth);
775
776 membar("#StoreStore | #LoadStore");
777 if (result == 1) {
778 int ncpus = smp_num_cpus;
779
780 #ifdef CAPTURE_DEBUG
781 printk("CPU[%d]: Sending penguins to jail...",
782 smp_processor_id());
783 #endif
784 penguins_are_doing_time = 1;
785 membar("#StoreStore | #LoadStore");
786 atomic_inc(&smp_capture_registry);
787 smp_cross_call(&xcall_capture, 0, 0, 0);
788 while (atomic_read(&smp_capture_registry) != ncpus)
789 membar("#LoadLoad");
790 #ifdef CAPTURE_DEBUG
791 printk("done\n");
792 #endif
793 }
794 }
795 }
796
797 void smp_release(void)
798 {
799 if (smp_processors_ready) {
800 if (atomic_dec_and_test(&smp_capture_depth)) {
801 #ifdef CAPTURE_DEBUG
802 printk("CPU[%d]: Giving pardon to imprisoned penguins\n",
803 smp_processor_id());
804 #endif
805 penguins_are_doing_time = 0;
806 membar("#StoreStore | #StoreLoad");
807 atomic_dec(&smp_capture_registry);
808 }
809 }
810 }
811
812 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
813 * can service tlb flush xcalls...
814 */
815 extern void prom_world(int);
816 extern void save_alternate_globals(unsigned long *);
817 extern void restore_alternate_globals(unsigned long *);
818 void smp_penguin_jailcell(void)
819 {
820 unsigned long global_save[24];
821
822 __asm__ __volatile__("flushw");
823 save_alternate_globals(global_save);
824 prom_world(1);
825 atomic_inc(&smp_capture_registry);
826 membar("#StoreLoad | #StoreStore");
827 while (penguins_are_doing_time)
828 membar("#LoadLoad");
829 restore_alternate_globals(global_save);
830 atomic_dec(&smp_capture_registry);
831 prom_world(0);
832 }
833
834 extern unsigned long xcall_promstop;
835
836 void smp_promstop_others(void)
837 {
838 if (smp_processors_ready)
839 smp_cross_call(&xcall_promstop, 0, 0, 0);
840 }
841
842 extern void sparc64_do_profile(unsigned long pc, unsigned long o7);
843
844 static unsigned long current_tick_offset;
845
846 #define prof_multiplier(__cpu) cpu_data[(__cpu)].multiplier
847 #define prof_counter(__cpu) cpu_data[(__cpu)].counter
848
849 void smp_percpu_timer_interrupt(struct pt_regs *regs)
850 {
851 unsigned long compare, tick, pstate;
852 int cpu = smp_processor_id();
853 int user = user_mode(regs);
854
855 /*
856 * Check for level 14 softint.
857 */
858 {
859 unsigned long tick_mask;
860
861 if (SPARC64_USE_STICK)
862 tick_mask = (1UL << 16);
863 else
864 tick_mask = (1UL << 0);
865
866 if (!(get_softint() & tick_mask)) {
867 extern void handler_irq(int, struct pt_regs *);
868
869 handler_irq(14, regs);
870 return;
871 }
872 clear_softint(tick_mask);
873 }
874
875 do {
876 if (!user)
877 sparc64_do_profile(regs->tpc, regs->u_regs[UREG_RETPC]);
878 if (!--prof_counter(cpu)) {
879 if (cpu == boot_cpu_id) {
880 irq_enter(cpu, 0);
881
882 kstat.irqs[cpu][0]++;
883 timer_tick_interrupt(regs);
884
885 irq_exit(cpu, 0);
886 }
887
888 update_process_times(user);
889
890 prof_counter(cpu) = prof_multiplier(cpu);
891 }
892
893 /* Guarentee that the following sequences execute
894 * uninterrupted.
895 */
896 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
897 "wrpr %0, %1, %%pstate"
898 : "=r" (pstate)
899 : "i" (PSTATE_IE));
900
901 /* Workaround for Spitfire Errata (#54 I think??), I discovered
902 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
903 * number 103640.
904 *
905 * On Blackbird writes to %tick_cmpr can fail, the
906 * workaround seems to be to execute the wr instruction
907 * at the start of an I-cache line, and perform a dummy
908 * read back from %tick_cmpr right after writing to it. -DaveM
909 *
910 * Just to be anal we add a workaround for Spitfire
911 * Errata 50 by preventing pipeline bypasses on the
912 * final read of the %tick register into a compare
913 * instruction. The Errata 50 description states
914 * that %tick is not prone to this bug, but I am not
915 * taking any chances.
916 */
917 if (!SPARC64_USE_STICK) {
918 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
919 "ba,pt %%xcc, 1f\n\t"
920 " add %0, %2, %0\n\t"
921 ".align 64\n"
922 "1: wr %0, 0x0, %%tick_cmpr\n\t"
923 "rd %%tick_cmpr, %%g0\n\t"
924 "rd %%tick, %1\n\t"
925 "mov %1, %1"
926 : "=&r" (compare), "=r" (tick)
927 : "r" (current_tick_offset));
928 } else {
929 __asm__ __volatile__("rd %%asr25, %0\n\t"
930 "add %0, %2, %0\n\t"
931 "wr %0, 0x0, %%asr25\n\t"
932 "rd %%asr24, %1\n\t"
933 : "=&r" (compare), "=r" (tick)
934 : "r" (current_tick_offset));
935 }
936
937 /* Restore PSTATE_IE. */
938 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
939 : /* no outputs */
940 : "r" (pstate));
941 } while (tick >= compare);
942 }
943
944 static void __init smp_setup_percpu_timer(void)
945 {
946 int cpu = smp_processor_id();
947 unsigned long pstate;
948
949 prof_counter(cpu) = prof_multiplier(cpu) = 1;
950
951 /* Guarentee that the following sequences execute
952 * uninterrupted.
953 */
954 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
955 "wrpr %0, %1, %%pstate"
956 : "=r" (pstate)
957 : "i" (PSTATE_IE));
958
959 /* Workaround for Spitfire Errata (#54 I think??), I discovered
960 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
961 * number 103640.
962 *
963 * On Blackbird writes to %tick_cmpr can fail, the
964 * workaround seems to be to execute the wr instruction
965 * at the start of an I-cache line, and perform a dummy
966 * read back from %tick_cmpr right after writing to it. -DaveM
967 */
968 if (!SPARC64_USE_STICK) {
969 __asm__ __volatile__("
970 rd %%tick, %%g1
971 ba,pt %%xcc, 1f
972 add %%g1, %0, %%g1
973 .align 64
974 1: wr %%g1, 0x0, %%tick_cmpr
975 rd %%tick_cmpr, %%g0"
976 : /* no outputs */
977 : "r" (current_tick_offset)
978 : "g1");
979 } else {
980 __asm__ __volatile__("
981 rd %%asr24, %%g1
982 add %%g1, %0, %%g1
983 wr %%g1, 0x0, %%asr25"
984 : /* no outputs */
985 : "r" (current_tick_offset)
986 : "g1");
987 }
988
989 /* Restore PSTATE_IE. */
990 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
991 : /* no outputs */
992 : "r" (pstate));
993 }
994
995 void __init smp_tick_init(void)
996 {
997 int i;
998
999 boot_cpu_id = hard_smp_processor_id();
1000 current_tick_offset = timer_tick_offset;
1001 cpu_present_map = 0;
1002 for (i = 0; i < linux_num_cpus; i++)
1003 cpu_present_map |= (1UL << linux_cpus[i].mid);
1004 for (i = 0; i < NR_CPUS; i++) {
1005 __cpu_number_map[i] = -1;
1006 __cpu_logical_map[i] = -1;
1007 }
1008 __cpu_number_map[boot_cpu_id] = 0;
1009 prom_cpu_nodes[boot_cpu_id] = linux_cpus[0].prom_node;
1010 __cpu_logical_map[0] = boot_cpu_id;
1011 current->processor = boot_cpu_id;
1012 prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1013 }
1014
1015 static inline unsigned long find_flush_base(unsigned long size)
1016 {
1017 struct page *p = mem_map;
1018 unsigned long found, base;
1019
1020 size = PAGE_ALIGN(size);
1021 found = size;
1022 base = (unsigned long) page_address(p);
1023 while (found != 0) {
1024 /* Failure. */
1025 if (p >= (mem_map + max_mapnr))
1026 return 0UL;
1027 if (PageReserved(p)) {
1028 found = size;
1029 base = (unsigned long) page_address(p);
1030 } else {
1031 found -= PAGE_SIZE;
1032 }
1033 p++;
1034 }
1035 return base;
1036 }
1037
1038 /* /proc/profile writes can call this, don't __init it please. */
1039 int setup_profiling_timer(unsigned int multiplier)
1040 {
1041 unsigned long flags;
1042 int i;
1043
1044 if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1045 return -EINVAL;
1046
1047 save_and_cli(flags);
1048 for (i = 0; i < NR_CPUS; i++) {
1049 if (cpu_present_map & (1UL << i))
1050 prof_multiplier(i) = multiplier;
1051 }
1052 current_tick_offset = (timer_tick_offset / multiplier);
1053 restore_flags(flags);
1054
1055 return 0;
1056 }
1057