File: /usr/src/linux/drivers/atm/ambassador.h
1 /*
2 Madge Ambassador ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
21 */
22
23 #ifndef AMBASSADOR_H
24 #define AMBASSADOR_H
25
26 #include <linux/config.h>
27
28 #ifdef CONFIG_ATM_AMBASSADOR_DEBUG
29 #define DEBUG_AMBASSADOR
30 #endif
31
32 #define DEV_LABEL "amb"
33
34 #ifndef PCI_VENDOR_ID_MADGE
35 #define PCI_VENDOR_ID_MADGE 0x10B6
36 #endif
37 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR
38 #define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001
39 #endif
40 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD
41 #define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002
42 #endif
43
44 // diagnostic output
45
46 #define PRINTK(severity,format,args...) \
47 printk(severity DEV_LABEL ": " format "\n" , ## args)
48
49 #ifdef DEBUG_AMBASSADOR
50
51 #define DBG_ERR 0x0001
52 #define DBG_WARN 0x0002
53 #define DBG_INFO 0x0004
54 #define DBG_INIT 0x0008
55 #define DBG_LOAD 0x0010
56 #define DBG_VCC 0x0020
57 #define DBG_QOS 0x0040
58 #define DBG_CMD 0x0080
59 #define DBG_TX 0x0100
60 #define DBG_RX 0x0200
61 #define DBG_SKB 0x0400
62 #define DBG_POOL 0x0800
63 #define DBG_IRQ 0x1000
64 #define DBG_FLOW 0x2000
65 #define DBG_REGS 0x4000
66 #define DBG_DATA 0x8000
67 #define DBG_MASK 0xffff
68
69 /* the ## prevents the annoying double expansion of the macro arguments */
70 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
71 #define PRINTDB(bits,format,args...) \
72 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
73 #define PRINTDM(bits,format,args...) \
74 ( (debug & (bits)) ? printk (format , ## args) : 1 )
75 #define PRINTDE(bits,format,args...) \
76 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
77 #define PRINTD(bits,format,args...) \
78 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
79
80 #else
81
82 #define PRINTD(bits,format,args...)
83 #define PRINTDB(bits,format,args...)
84 #define PRINTDM(bits,format,args...)
85 #define PRINTDE(bits,format,args...)
86
87 #endif
88
89 #define PRINTDD(bits,format,args...)
90 #define PRINTDDB(sec,fmt,args...)
91 #define PRINTDDM(sec,fmt,args...)
92 #define PRINTDDE(sec,fmt,args...)
93
94 // tunable values (?)
95
96 /* MUST be powers of two -- why ? */
97 #define COM_Q_ENTRIES 8
98 #define TX_Q_ENTRIES 32
99 #define RX_Q_ENTRIES 64
100
101 // fixed values
102
103 // guessing
104 #define AMB_EXTENT 0x80
105
106 // Minimum allowed size for an Ambassador queue
107 #define MIN_QUEUE_SIZE 2
108
109 // Ambassador microcode allows 1 to 4 pools, we use 4 (simpler)
110 #define NUM_RX_POOLS 4
111
112 // minimum RX buffers required to cope with replenishing delay
113 #define MIN_RX_BUFFERS 1
114
115 // minimum PCI latency we will tolerate (32 IS TOO SMALL)
116 #define MIN_PCI_LATENCY 64 // 255
117
118 // VCs supported by card (VPI always 0)
119 #define NUM_VPI_BITS 0
120 #define NUM_VCI_BITS 10
121 #define NUM_VCS 1024
122
123 /* The status field bits defined so far. */
124 #define RX_ERR 0x8000 // always present if there is an error (hmm)
125 #define CRC_ERR 0x4000 // AAL5 CRC error
126 #define LEN_ERR 0x2000 // overlength frame
127 #define ABORT_ERR 0x1000 // zero length field in received frame
128 #define UNUSED_ERR 0x0800 // buffer returned unused
129
130 // Adaptor commands
131
132 #define SRB_OPEN_VC 0
133 /* par_0: dwordswap(VC_number) */
134 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
135 /* flags: */
136
137 /* LANE: 0x0004 */
138 /* NOT_UBR: 0x0008 */
139 /* ABR: 0x0010 */
140
141 /* RxPool0: 0x0000 */
142 /* RxPool1: 0x0020 */
143 /* RxPool2: 0x0040 */
144 /* RxPool3: 0x0060 */
145
146 /* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
147
148 #define SRB_CLOSE_VC 1
149 /* par_0: dwordswap(VC_number) */
150
151 #define SRB_GET_BIA 2
152 /* returns */
153 /* par_0: dwordswap(half BIA) */
154 /* par_1: dwordswap(half BIA) */
155
156 #define SRB_GET_SUNI_STATS 3
157 /* par_0: dwordswap(physical_host_address) */
158
159 #define SRB_SET_BITS_8 4
160 #define SRB_SET_BITS_16 5
161 #define SRB_SET_BITS_32 6
162 #define SRB_CLEAR_BITS_8 7
163 #define SRB_CLEAR_BITS_16 8
164 #define SRB_CLEAR_BITS_32 9
165 /* par_0: dwordswap(ATMizer address) */
166 /* par_1: dwordswap(mask) */
167
168 #define SRB_SET_8 10
169 #define SRB_SET_16 11
170 #define SRB_SET_32 12
171 /* par_0: dwordswap(ATMizer address) */
172 /* par_1: dwordswap(data) */
173
174 #define SRB_GET_32 13
175 /* par_0: dwordswap(ATMizer address) */
176 /* returns */
177 /* par_1: dwordswap(ATMizer data) */
178
179 #define SRB_GET_VERSION 14
180 /* returns */
181 /* par_0: dwordswap(Major Version) */
182 /* par_1: dwordswap(Minor Version) */
183
184 #define SRB_FLUSH_BUFFER_Q 15
185 /* Only flags to define which buffer pool; all others must be zero */
186 /* par_0: dwordswap(flags<<16) or wordswap(flags)*/
187
188 #define SRB_GET_DMA_SPEEDS 16
189 /* returns */
190 /* par_0: dwordswap(Read speed (bytes/sec)) */
191 /* par_1: dwordswap(Write speed (bytes/sec)) */
192
193 #define SRB_MODIFY_VC_RATE 17
194 /* par_0: dwordswap(VC_number) */
195 /* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
196
197 #define SRB_MODIFY_VC_FLAGS 18
198 /* par_0: dwordswap(VC_number) */
199 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
200
201 /* flags: */
202
203 /* LANE: 0x0004 */
204 /* NOT_UBR: 0x0008 */
205 /* ABR: 0x0010 */
206
207 /* RxPool0: 0x0000 */
208 /* RxPool1: 0x0020 */
209 /* RxPool2: 0x0040 */
210 /* RxPool3: 0x0060 */
211
212 #define SRB_RATE_SHIFT 16
213 #define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5)
214 #define SRB_FLAGS_SHIFT 16
215
216 #define SRB_STOP_TASKING 19
217 #define SRB_START_TASKING 20
218 #define SRB_SHUT_DOWN 21
219 #define MAX_SRB 21
220
221 #define SRB_COMPLETE 0xffffffff
222
223 #define TX_FRAME 0x80000000
224
225 // number of types of SRB MUST be a power of two -- why?
226 #define NUM_OF_SRB 32
227
228 // number of bits of period info for rate
229 #define MAX_RATE_BITS 6
230
231 #define TX_UBR 0x0000
232 #define TX_UBR_CAPPED 0x0008
233 #define TX_ABR 0x0018
234 #define TX_FRAME_NOTCAP 0x0000
235 #define TX_FRAME_CAPPED 0x8000
236
237 #define FP_155_RATE 0x24b1
238 #define FP_25_RATE 0x1f9d
239
240 /* #define VERSION_NUMBER 0x01000000 // initial release */
241 /* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */
242 /* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */
243
244 /* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */
245 /* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */
246 /* remove race conditions on basic interface */
247 /* indicate to the host that diagnostics */
248 /* have finished; if failed, how and what */
249 /* failed */
250 /* fix host memory test to fix PLX bug */
251 /* allow flash upgrade and BIA upgrade directly */
252 /* */
253 #define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */
254 /* Change in download algorithm */
255
256 #define DMA_VALID 0xb728e149 /* completely random */
257
258 #define FLASH_BASE 0xa0c00000
259 #define FLASH_SIZE 0x00020000 /* 128K */
260 #define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */
261 #define BIA_ADDRESS ((void *)0xa0c1c000)
262 #define PLX_BASE 0xe0000000
263
264 typedef enum {
265 host_memory_test = 1,
266 read_adapter_memory,
267 write_adapter_memory,
268 adapter_start,
269 get_version_number,
270 interrupt_host,
271 flash_erase_sector,
272 adap_download_block = 0x20,
273 adap_erase_flash,
274 adap_run_in_iram,
275 adap_end_download
276 } loader_command;
277
278 #define BAD_COMMAND (-1)
279 #define COMMAND_IN_PROGRESS 1
280 #define COMMAND_PASSED_TEST 2
281 #define COMMAND_FAILED_TEST 3
282 #define COMMAND_READ_DATA_OK 4
283 #define COMMAND_READ_BAD_ADDRESS 5
284 #define COMMAND_WRITE_DATA_OK 6
285 #define COMMAND_WRITE_BAD_ADDRESS 7
286 #define COMMAND_WRITE_FLASH_FAILURE 8
287 #define COMMAND_COMPLETE 9
288 #define COMMAND_FLASH_ERASE_FAILURE 10
289 #define COMMAND_WRITE_BAD_DATA 11
290
291 /* bit fields for mailbox[0] return values */
292
293 #define GPINT_TST_FAILURE 0x00000001
294 #define SUNI_DATA_PATTERN_FAILURE 0x00000002
295 #define SUNI_DATA_BITS_FAILURE 0x00000004
296 #define SUNI_UTOPIA_FAILURE 0x00000008
297 #define SUNI_FIFO_FAILURE 0x00000010
298 #define SRAM_FAILURE 0x00000020
299 #define SELF_TEST_FAILURE 0x0000003f
300
301 /* mailbox[1] = 0 in progress, -1 on completion */
302 /* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */
303 /* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */
304 /* mailbox[4],mailbox[5],mailbox[6] random failure values */
305
306 /* PLX/etc. memory map including command structure */
307
308 /* These registers may also be memory mapped in PCI memory */
309
310 #define UNUSED_LOADER_MAILBOXES 6
311
312 typedef struct {
313 u32 stuff[16];
314 union {
315 struct {
316 u32 result;
317 u32 ready;
318 u32 stuff[UNUSED_LOADER_MAILBOXES];
319 } loader;
320 struct {
321 u32 cmd_address;
322 u32 tx_address;
323 u32 rx_address[NUM_RX_POOLS];
324 u32 gen_counter;
325 u32 spare;
326 } adapter;
327 } mb;
328 u32 doorbell;
329 u32 interrupt;
330 u32 interrupt_control;
331 u32 reset_control;
332 } amb_mem;
333
334 /* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */
335 #define AMB_RESET_BITS 0x40000000
336 #define AMB_INTERRUPT_BITS 0x00000300
337 #define AMB_DOORBELL_BITS 0x00030000
338
339 /* loader commands */
340
341 #define MAX_COMMAND_DATA 13
342 #define MAX_TRANSFER_DATA 11
343
344 typedef struct {
345 u32 address;
346 u32 count;
347 u32 data[MAX_TRANSFER_DATA];
348 } transfer_block;
349
350 typedef struct {
351 u32 result;
352 u32 command;
353 union {
354 transfer_block transfer;
355 u32 version;
356 u32 start;
357 u32 data[MAX_COMMAND_DATA];
358 } payload;
359 u32 valid;
360 } loader_block;
361
362 /* command queue */
363
364 /* Again all data are BIG ENDIAN */
365
366 typedef struct {
367 union {
368 struct {
369 u32 vc;
370 u32 flags;
371 u32 rate;
372 } open;
373 struct {
374 u32 vc;
375 u32 rate;
376 } modify_rate;
377 struct {
378 u32 vc;
379 u32 flags;
380 } modify_flags;
381 struct {
382 u32 vc;
383 } close;
384 struct {
385 u32 lower4;
386 u32 upper2;
387 } bia;
388 struct {
389 u32 address;
390 } suni;
391 struct {
392 u32 major;
393 u32 minor;
394 } version;
395 struct {
396 u32 read;
397 u32 write;
398 } speed;
399 struct {
400 u32 flags;
401 } flush;
402 struct {
403 u32 address;
404 u32 data;
405 } memory;
406 u32 par[3];
407 } args;
408 u32 request;
409 } command;
410
411 /* transmit queues and associated structures */
412
413 /* The hosts transmit structure. All BIG ENDIAN; host address
414 restricted to first 1GByte, but address passed to the card must
415 have the top MS bit or'ed in. -- check this */
416
417 /* TX is described by 1+ tx_frags followed by a tx_frag_end */
418
419 typedef struct {
420 u32 bytes;
421 u32 address;
422 } tx_frag;
423
424 /* apart from handle the fields here are for the adapter to play with
425 and should be set to zero */
426
427 typedef struct {
428 u32 handle;
429 u16 vc;
430 u16 next_descriptor_length;
431 u32 next_descriptor;
432 #ifdef AMB_NEW_MICROCODE
433 u8 cpcs_uu;
434 u8 cpi;
435 u16 pad;
436 #endif
437 } tx_frag_end;
438
439 typedef struct {
440 tx_frag tx_frag;
441 tx_frag_end tx_frag_end;
442 struct sk_buff * skb;
443 } tx_simple;
444
445 #if 0
446 typedef union {
447 tx_frag fragment;
448 tx_frag_end end_of_list;
449 } tx_descr;
450 #endif
451
452 /* this "points" to the sequence of fragments and trailer */
453
454 typedef struct {
455 u16 vc;
456 u16 tx_descr_length;
457 u32 tx_descr_addr;
458 } tx_in;
459
460 /* handle is the handle from tx_in */
461
462 typedef struct {
463 u32 handle;
464 } tx_out;
465
466 /* receive frame structure */
467
468 /* All BIG ENDIAN; handle is as passed from host; length is zero for
469 aborted frames, and frames with errors. Header is actually VC
470 number, lec-id is NOT yet supported. */
471
472 typedef struct {
473 u32 handle;
474 u16 vc;
475 u16 lec_id; // unused
476 u16 status;
477 u16 length;
478 } rx_out;
479
480 /* buffer supply structure */
481
482 typedef struct {
483 u32 handle;
484 u32 host_address;
485 } rx_in;
486
487 /* This first structure is the area in host memory where the adapter
488 writes its pointer values. These pointer values are BIG ENDIAN and
489 reside in the same 4MB 'page' as this structure. The host gives the
490 adapter the address of this block by sending a doorbell interrupt
491 to the adapter after downloading the code and setting it going. The
492 addresses have the top 10 bits set to 1010000010b -- really?
493
494 The host must initialise these before handing the block to the
495 adapter. */
496
497 typedef struct {
498 u32 command_start; /* SRB commands completions */
499 u32 command_end; /* SRB commands completions */
500 u32 tx_start;
501 u32 tx_end;
502 u32 txcom_start; /* tx completions */
503 u32 txcom_end; /* tx completions */
504 struct {
505 u32 buffer_start;
506 u32 buffer_end;
507 u32 buffer_q_get;
508 u32 buffer_q_end;
509 u32 buffer_aptr;
510 u32 rx_start; /* rx completions */
511 u32 rx_end;
512 u32 rx_ptr;
513 u32 buffer_size; /* size of host buffer */
514 } rec_struct[NUM_RX_POOLS];
515 #ifdef AMB_NEW_MICROCODE
516 u16 init_flags;
517 u16 talk_block_spare;
518 #endif
519 } adap_talk_block;
520
521 /* This structure must be kept in line with the vcr image in sarmain.h
522
523 This is the structure in the host filled in by the adapter by
524 GET_SUNI_STATS */
525
526 typedef struct {
527 u8 racp_chcs;
528 u8 racp_uhcs;
529 u16 spare;
530 u32 racp_rcell;
531 u32 tacp_tcell;
532 u32 flags;
533 u32 dropped_cells;
534 u32 dropped_frames;
535 } suni_stats;
536
537 typedef enum {
538 dead
539 } amb_flags;
540
541 #define NEXTQ(current,start,limit) \
542 ( (current)+1 < (limit) ? (current)+1 : (start) )
543
544 typedef struct {
545 command * start;
546 command * in;
547 command * out;
548 command * limit;
549 } amb_cq_ptrs;
550
551 typedef struct {
552 spinlock_t lock;
553 unsigned int pending;
554 unsigned int high;
555 unsigned int filled;
556 unsigned int maximum; // size - 1 (q implementation)
557 amb_cq_ptrs ptrs;
558 } amb_cq;
559
560 typedef struct {
561 spinlock_t lock;
562 unsigned int pending;
563 unsigned int high;
564 unsigned int filled;
565 unsigned int maximum; // size - 1 (q implementation)
566 struct {
567 tx_in * start;
568 tx_in * ptr;
569 tx_in * limit;
570 } in;
571 struct {
572 tx_out * start;
573 tx_out * ptr;
574 tx_out * limit;
575 } out;
576 } amb_txq;
577
578 typedef struct {
579 spinlock_t lock;
580 unsigned int pending;
581 unsigned int low;
582 unsigned int emptied;
583 unsigned int maximum; // size - 1 (q implementation)
584 struct {
585 rx_in * start;
586 rx_in * ptr;
587 rx_in * limit;
588 } in;
589 struct {
590 rx_out * start;
591 rx_out * ptr;
592 rx_out * limit;
593 } out;
594 unsigned int buffers_wanted;
595 unsigned int buffer_size;
596 } amb_rxq;
597
598 typedef struct {
599 unsigned long tx_ok;
600 struct {
601 unsigned long ok;
602 unsigned long error;
603 unsigned long badcrc;
604 unsigned long toolong;
605 unsigned long aborted;
606 unsigned long unused;
607 } rx;
608 } amb_stats;
609
610 // a single struct pointed to by atm_vcc->dev_data
611
612 typedef struct {
613 u8 tx_vc_bits:7;
614 u8 tx_present:1;
615 } amb_tx_info;
616
617 typedef struct {
618 unsigned char pool;
619 } amb_rx_info;
620
621 typedef struct {
622 amb_rx_info rx_info;
623 u16 tx_frame_bits;
624 unsigned int tx_rate;
625 unsigned int rx_rate;
626 } amb_vcc;
627
628 struct amb_dev {
629 u8 irq;
630 u8 flags;
631 u32 iobase;
632 u32 * membase;
633
634 #ifdef FILL_RX_POOLS_IN_BH
635 struct tq_struct bh;
636 #endif
637
638 amb_cq cq;
639 amb_txq txq;
640 amb_rxq rxq[NUM_RX_POOLS];
641
642 struct semaphore vcc_sf;
643 amb_tx_info txer[NUM_VCS];
644 struct atm_vcc * rxer[NUM_VCS];
645 unsigned int tx_avail;
646 unsigned int rx_avail;
647
648 amb_stats stats;
649
650 struct atm_dev * atm_dev;
651 struct pci_dev * pci_dev;
652 struct amb_dev * prev;
653 };
654
655 typedef struct amb_dev amb_dev;
656
657 #define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data)
658 #define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data)
659
660 /* the microcode */
661
662 typedef struct {
663 u32 start;
664 unsigned int count;
665 } region;
666
667 static region ucode_regions[];
668 static u32 ucode_data[];
669 static u32 ucode_start;
670
671 /* rate rounding */
672
673 typedef enum {
674 round_up,
675 round_down,
676 round_nearest
677 } rounding;
678
679 #endif
680