File: /usr/src/linux/arch/alpha/kernel/pci_iommu.c
1 /*
2 * linux/arch/alpha/kernel/pci_iommu.c
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/mm.h>
7 #include <linux/pci.h>
8 #include <linux/slab.h>
9 #include <linux/bootmem.h>
10
11 #include <asm/io.h>
12 #include <asm/hwrpb.h>
13
14 #include "proto.h"
15 #include "pci_impl.h"
16
17
18 #define DEBUG_ALLOC 0
19 #if DEBUG_ALLOC > 0
20 # define DBGA(args...) printk(KERN_DEBUG ##args)
21 #else
22 # define DBGA(args...)
23 #endif
24 #if DEBUG_ALLOC > 1
25 # define DBGA2(args...) printk(KERN_DEBUG ##args)
26 #else
27 # define DBGA2(args...)
28 #endif
29
30 #define DEBUG_NODIRECT 0
31
32
33 static inline unsigned long
34 mk_iommu_pte(unsigned long paddr)
35 {
36 return (paddr >> (PAGE_SHIFT-1)) | 1;
37 }
38
39 static inline long
40 calc_npages(long bytes)
41 {
42 return (bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
43 }
44
45
46 struct pci_iommu_arena *
47 iommu_arena_new(struct pci_controller *hose, dma_addr_t base,
48 unsigned long window_size, unsigned long align)
49 {
50 unsigned long mem_size;
51 struct pci_iommu_arena *arena;
52
53 mem_size = window_size / (PAGE_SIZE / sizeof(unsigned long));
54
55 /* Note that the TLB lookup logic uses bitwise concatenation,
56 not addition, so the required arena alignment is based on
57 the size of the window. Retain the align parameter so that
58 particular systems can over-align the arena. */
59 if (align < mem_size)
60 align = mem_size;
61
62 arena = alloc_bootmem(sizeof(*arena));
63 arena->ptes = __alloc_bootmem(mem_size, align, 0);
64
65 spin_lock_init(&arena->lock);
66 arena->hose = hose;
67 arena->dma_base = base;
68 arena->size = window_size;
69 arena->next_entry = 0;
70
71 /* Align allocations to a multiple of a page size. Not needed
72 unless there are chip bugs. */
73 arena->align_entry = 1;
74
75 return arena;
76 }
77
78 /* Must be called with the arena lock held */
79 static long
80 iommu_arena_find_pages(struct pci_iommu_arena *arena, long n, long mask)
81 {
82 unsigned long *ptes;
83 long i, p, nent;
84
85 /* Search forward for the first mask-aligned sequence of N free ptes */
86 ptes = arena->ptes;
87 nent = arena->size >> PAGE_SHIFT;
88 p = (arena->next_entry + mask) & ~mask;
89 i = 0;
90 while (i < n && p+i < nent) {
91 if (ptes[p+i])
92 p = (p + i + 1 + mask) & ~mask, i = 0;
93 else
94 i = i + 1;
95 }
96
97 if (i < n) {
98 /* Reached the end. Flush the TLB and restart the
99 search from the beginning. */
100 alpha_mv.mv_pci_tbi(arena->hose, 0, -1);
101
102 p = 0, i = 0;
103 while (i < n && p+i < nent) {
104 if (ptes[p+i])
105 p = (p + i + 1 + mask) & ~mask, i = 0;
106 else
107 i = i + 1;
108 }
109
110 if (i < n)
111 return -1;
112 }
113
114 /* Success. It's the responsibility of the caller to mark them
115 in use before releasing the lock */
116 return p;
117 }
118
119 long
120 iommu_arena_alloc(struct pci_iommu_arena *arena, long n)
121 {
122 unsigned long flags;
123 unsigned long *ptes;
124 long i, p, mask;
125
126 spin_lock_irqsave(&arena->lock, flags);
127
128 /* Search for N empty ptes */
129 ptes = arena->ptes;
130 mask = arena->align_entry - 1;
131 p = iommu_arena_find_pages(arena, n, mask);
132 if (p < 0) {
133 spin_unlock_irqrestore(&arena->lock, flags);
134 return -1;
135 }
136
137 /* Success. Mark them all in use, ie not zero and invalid
138 for the iommu tlb that could load them from under us.
139 The chip specific bits will fill this in with something
140 kosher when we return. */
141 for (i = 0; i < n; ++i)
142 ptes[p+i] = IOMMU_INVALID_PTE;
143
144 arena->next_entry = p + n;
145 spin_unlock_irqrestore(&arena->lock, flags);
146
147 return p;
148 }
149
150 static void
151 iommu_arena_free(struct pci_iommu_arena *arena, long ofs, long n)
152 {
153 unsigned long *p;
154 long i;
155
156 p = arena->ptes + ofs;
157 for (i = 0; i < n; ++i)
158 p[i] = 0;
159 }
160
161 /* Map a single buffer of the indicated size for PCI DMA in streaming
162 mode. The 32-bit PCI bus mastering address to use is returned.
163 Once the device is given the dma address, the device owns this memory
164 until either pci_unmap_single or pci_dma_sync_single is performed. */
165
166 dma_addr_t
167 pci_map_single(struct pci_dev *pdev, void *cpu_addr, long size, int direction)
168 {
169 struct pci_controller *hose = pdev ? pdev->sysdata : pci_isa_hose;
170 dma_addr_t max_dma = pdev ? pdev->dma_mask : 0x00ffffff;
171 struct pci_iommu_arena *arena;
172 long npages, dma_ofs, i;
173 unsigned long paddr;
174 dma_addr_t ret;
175
176 if (direction == PCI_DMA_NONE)
177 BUG();
178
179 paddr = virt_to_phys(cpu_addr);
180
181 #if !DEBUG_NODIRECT
182 /* First check to see if we can use the direct map window. */
183 if (paddr + size + __direct_map_base - 1 <= max_dma
184 && paddr + size <= __direct_map_size) {
185 ret = paddr + __direct_map_base;
186
187 DBGA2("pci_map_single: [%p,%lx] -> direct %x from %p\n",
188 cpu_addr, size, ret, __builtin_return_address(0));
189
190 return ret;
191 }
192 #endif
193
194 /* If the machine doesn't define a pci_tbi routine, we have to
195 assume it doesn't support sg mapping. */
196 if (! alpha_mv.mv_pci_tbi) {
197 printk(KERN_WARNING "pci_map_single failed: no hw sg\n");
198 return 0;
199 }
200
201 arena = hose->sg_pci;
202 if (!arena || arena->dma_base + arena->size > max_dma)
203 arena = hose->sg_isa;
204
205 npages = calc_npages((paddr & ~PAGE_MASK) + size);
206 dma_ofs = iommu_arena_alloc(arena, npages);
207 if (dma_ofs < 0) {
208 printk(KERN_WARNING "pci_map_single failed: "
209 "could not allocate dma page tables\n");
210 return 0;
211 }
212
213 paddr &= PAGE_MASK;
214 for (i = 0; i < npages; ++i, paddr += PAGE_SIZE)
215 arena->ptes[i + dma_ofs] = mk_iommu_pte(paddr);
216
217 ret = arena->dma_base + dma_ofs * PAGE_SIZE;
218 ret += (unsigned long)cpu_addr & ~PAGE_MASK;
219
220 DBGA("pci_map_single: [%p,%lx] np %ld -> sg %x from %p\n",
221 cpu_addr, size, npages, ret, __builtin_return_address(0));
222
223 return ret;
224 }
225
226
227 /* Unmap a single streaming mode DMA translation. The DMA_ADDR and
228 SIZE must match what was provided for in a previous pci_map_single
229 call. All other usages are undefined. After this call, reads by
230 the cpu to the buffer are guarenteed to see whatever the device
231 wrote there. */
232
233 void
234 pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr, long size,
235 int direction)
236 {
237 unsigned long flags;
238 struct pci_controller *hose = pdev ? pdev->sysdata : pci_isa_hose;
239 struct pci_iommu_arena *arena;
240 long dma_ofs, npages;
241
242 if (direction == PCI_DMA_NONE)
243 BUG();
244
245 #if !DEBUG_NODIRECT
246 if (dma_addr >= __direct_map_base
247 && dma_addr < __direct_map_base + __direct_map_size) {
248 /* Nothing to do. */
249
250 DBGA2("pci_unmap_single: direct [%x,%lx] from %p\n",
251 dma_addr, size, __builtin_return_address(0));
252
253 return;
254 }
255 #endif
256
257 arena = hose->sg_pci;
258 if (!arena || dma_addr < arena->dma_base)
259 arena = hose->sg_isa;
260
261 dma_ofs = (dma_addr - arena->dma_base) >> PAGE_SHIFT;
262 if (dma_ofs * PAGE_SIZE >= arena->size) {
263 printk(KERN_ERR "Bogus pci_unmap_single: dma_addr %x "
264 " base %x size %x\n", dma_addr, arena->dma_base,
265 arena->size);
266 return;
267 BUG();
268 }
269
270 npages = calc_npages((dma_addr & ~PAGE_MASK) + size);
271
272 spin_lock_irqsave(&arena->lock, flags);
273
274 iommu_arena_free(arena, dma_ofs, npages);
275
276
277 /*
278 If we're freeing ptes above the `next_entry' pointer (they
279 may have snuck back into the TLB since the last wrap flush),
280 we need to flush the TLB before reallocating the latter.
281 */
282 if (dma_ofs >= arena->next_entry)
283 alpha_mv.mv_pci_tbi(hose, dma_addr, dma_addr + size - 1);
284
285 spin_unlock_irqrestore(&arena->lock, flags);
286
287 DBGA("pci_unmap_single: sg [%x,%lx] np %ld from %p\n",
288 dma_addr, size, npages, __builtin_return_address(0));
289 }
290
291
292 /* Allocate and map kernel buffer using consistent mode DMA for PCI
293 device. Returns non-NULL cpu-view pointer to the buffer if
294 successful and sets *DMA_ADDRP to the pci side dma address as well,
295 else DMA_ADDRP is undefined. */
296
297 void *
298 pci_alloc_consistent(struct pci_dev *pdev, long size, dma_addr_t *dma_addrp)
299 {
300 void *cpu_addr;
301 long order = get_order(size);
302
303 cpu_addr = (void *)__get_free_pages(GFP_ATOMIC, order);
304 if (! cpu_addr) {
305 printk(KERN_INFO "pci_alloc_consistent: "
306 "get_free_pages failed from %p\n",
307 __builtin_return_address(0));
308 /* ??? Really atomic allocation? Otherwise we could play
309 with vmalloc and sg if we can't find contiguous memory. */
310 return NULL;
311 }
312 memset(cpu_addr, 0, size);
313
314 *dma_addrp = pci_map_single(pdev, cpu_addr, size,
315 PCI_DMA_BIDIRECTIONAL);
316 if (*dma_addrp == 0) {
317 free_pages((unsigned long)cpu_addr, order);
318 return NULL;
319 }
320
321 DBGA2("pci_alloc_consistent: %lx -> [%p,%x] from %p\n",
322 size, cpu_addr, *dma_addrp, __builtin_return_address(0));
323
324 return cpu_addr;
325 }
326
327
328 /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
329 be values that were returned from pci_alloc_consistent. SIZE must
330 be the same as what as passed into pci_alloc_consistent.
331 References to the memory and mappings assosciated with CPU_ADDR or
332 DMA_ADDR past this call are illegal. */
333
334 void
335 pci_free_consistent(struct pci_dev *pdev, long size, void *cpu_addr,
336 dma_addr_t dma_addr)
337 {
338 pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL);
339 free_pages((unsigned long)cpu_addr, get_order(size));
340
341 DBGA2("pci_free_consistent: [%x,%lx] from %p\n",
342 dma_addr, size, __builtin_return_address(0));
343 }
344
345
346 /* Classify the elements of the scatterlist. Write dma_address
347 of each element with:
348 0 : Followers all physically adjacent.
349 1 : Followers all virtually adjacent.
350 -1 : Not leader, physically adjacent to previous.
351 -2 : Not leader, virtually adjacent to previous.
352 Write dma_length of each leader with the combined lengths of
353 the mergable followers. */
354
355 static void
356 sg_classify(struct scatterlist *sg, struct scatterlist *end, int virt_ok)
357 {
358 unsigned long next_vaddr;
359 struct scatterlist *leader;
360 long leader_flag, leader_length;
361
362 leader = sg;
363 leader_flag = 0;
364 leader_length = leader->length;
365 next_vaddr = (unsigned long)leader->address + leader_length;
366
367 for (++sg; sg < end; ++sg) {
368 unsigned long addr, len;
369 addr = (unsigned long) sg->address;
370 len = sg->length;
371
372 if (next_vaddr == addr) {
373 sg->dma_address = -1;
374 leader_length += len;
375 } else if (((next_vaddr | addr) & ~PAGE_MASK) == 0 && virt_ok) {
376 sg->dma_address = -2;
377 leader_flag = 1;
378 leader_length += len;
379 } else {
380 leader->dma_address = leader_flag;
381 leader->dma_length = leader_length;
382 leader = sg;
383 leader_flag = 0;
384 leader_length = len;
385 }
386
387 next_vaddr = addr + len;
388 }
389
390 leader->dma_address = leader_flag;
391 leader->dma_length = leader_length;
392 }
393
394 /* Given a scatterlist leader, choose an allocation method and fill
395 in the blanks. */
396
397 static inline int
398 sg_fill(struct scatterlist *leader, struct scatterlist *end,
399 struct scatterlist *out, struct pci_iommu_arena *arena,
400 dma_addr_t max_dma)
401 {
402 unsigned long paddr = virt_to_phys(leader->address);
403 long size = leader->dma_length;
404 struct scatterlist *sg;
405 unsigned long *ptes;
406 long npages, dma_ofs, i;
407
408 #if !DEBUG_NODIRECT
409 /* If everything is physically contiguous, and the addresses
410 fall into the direct-map window, use it. */
411 if (leader->dma_address == 0
412 && paddr + size + __direct_map_base - 1 <= max_dma
413 && paddr + size <= __direct_map_size) {
414 out->dma_address = paddr + __direct_map_base;
415 out->dma_length = size;
416
417 DBGA(" sg_fill: [%p,%lx] -> direct %x\n",
418 leader->address, size, out->dma_address);
419
420 return 0;
421 }
422 #endif
423
424 /* Otherwise, we'll use the iommu to make the pages virtually
425 contiguous. */
426
427 paddr &= ~PAGE_MASK;
428 npages = calc_npages(paddr + size);
429 dma_ofs = iommu_arena_alloc(arena, npages);
430 if (dma_ofs < 0) {
431 /* If we attempted a direct map above but failed, die. */
432 if (leader->dma_address == 0)
433 return -1;
434
435 /* Otherwise, break up the remaining virtually contiguous
436 hunks into individual direct maps. */
437 sg_classify(leader, end, 0);
438 /* Retry. */
439 return sg_fill(leader, end, out, arena, max_dma);
440 }
441
442 out->dma_address = arena->dma_base + dma_ofs*PAGE_SIZE + paddr;
443 out->dma_length = size;
444
445 DBGA(" sg_fill: [%p,%lx] -> sg %x np %ld\n",
446 leader->address, size, out->dma_address, npages);
447
448 /* All virtually contiguous. We need to find the length of each
449 physically contiguous subsegment to fill in the ptes. */
450 ptes = &arena->ptes[dma_ofs];
451 sg = leader;
452 do {
453 #if DEBUG_ALLOC > 0
454 struct scatterlist *last_sg = sg;
455 #endif
456
457 size = sg->length;
458 paddr = virt_to_phys(sg->address);
459
460 while (sg+1 < end && (int) sg[1].dma_address == -1) {
461 size += sg[1].length;
462 sg++;
463 }
464
465 npages = calc_npages((paddr & ~PAGE_MASK) + size);
466
467 paddr &= PAGE_MASK;
468 for (i = 0; i < npages; ++i, paddr += PAGE_SIZE)
469 *ptes++ = mk_iommu_pte(paddr);
470
471 #if DEBUG_ALLOC > 0
472 DBGA(" (%ld) [%p,%x] np %ld\n",
473 last_sg - leader, last_sg->address,
474 last_sg->length, npages);
475 while (++last_sg <= sg) {
476 DBGA(" (%ld) [%p,%x] cont\n",
477 last_sg - leader, last_sg->address,
478 last_sg->length);
479 }
480 #endif
481 } while (++sg < end && (int) sg->dma_address < 0);
482
483 return 1;
484 }
485
486 int
487 pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg, int nents,
488 int direction)
489 {
490 struct scatterlist *start, *end, *out;
491 struct pci_controller *hose;
492 struct pci_iommu_arena *arena;
493 dma_addr_t max_dma;
494
495 if (direction == PCI_DMA_NONE)
496 BUG();
497
498 /* Fast path single entry scatterlists. */
499 if (nents == 1) {
500 sg->dma_length = sg->length;
501 sg->dma_address
502 = pci_map_single(pdev, sg->address, sg->length, direction);
503 return sg->dma_address != 0;
504 }
505
506 start = sg;
507 end = sg + nents;
508
509 /* First, prepare information about the entries. */
510 sg_classify(sg, end, alpha_mv.mv_pci_tbi != 0);
511
512 /* Second, figure out where we're going to map things. */
513 if (alpha_mv.mv_pci_tbi) {
514 hose = pdev ? pdev->sysdata : pci_isa_hose;
515 max_dma = pdev ? pdev->dma_mask : 0x00ffffff;
516 arena = hose->sg_pci;
517 if (!arena || arena->dma_base + arena->size > max_dma)
518 arena = hose->sg_isa;
519 } else {
520 max_dma = -1;
521 arena = NULL;
522 hose = NULL;
523 }
524
525 /* Third, iterate over the scatterlist leaders and allocate
526 dma space as needed. */
527 for (out = sg; sg < end; ++sg) {
528 if ((int) sg->dma_address < 0)
529 continue;
530 if (sg_fill(sg, end, out, arena, max_dma) < 0)
531 goto error;
532 out++;
533 }
534
535 /* Mark the end of the list for pci_unmap_sg. */
536 if (out < end)
537 out->dma_length = 0;
538
539 if (out - start == 0)
540 printk(KERN_WARNING "pci_map_sg failed: no entries?\n");
541 DBGA("pci_map_sg: %ld entries\n", out - start);
542
543 return out - start;
544
545 error:
546 printk(KERN_WARNING "pci_map_sg failed: "
547 "could not allocate dma page tables\n");
548
549 /* Some allocation failed while mapping the scatterlist
550 entries. Unmap them now. */
551 if (out > start)
552 pci_unmap_sg(pdev, start, out - start, direction);
553 return 0;
554 }
555
556
557 /* Unmap a set of streaming mode DMA translations. Again, cpu read
558 rules concerning calls here are the same as for pci_unmap_single()
559 above. */
560
561 void
562 pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg, int nents,
563 int direction)
564 {
565 unsigned long flags;
566 struct pci_controller *hose;
567 struct pci_iommu_arena *arena;
568 struct scatterlist *end;
569 dma_addr_t max_dma;
570 dma_addr_t fbeg, fend;
571
572 if (direction == PCI_DMA_NONE)
573 BUG();
574
575 if (! alpha_mv.mv_pci_tbi)
576 return;
577
578 hose = pdev ? pdev->sysdata : pci_isa_hose;
579 max_dma = pdev ? pdev->dma_mask : 0x00ffffff;
580 arena = hose->sg_pci;
581 if (!arena || arena->dma_base + arena->size > max_dma)
582 arena = hose->sg_isa;
583
584 fbeg = -1, fend = 0;
585
586 spin_lock_irqsave(&arena->lock, flags);
587
588 for (end = sg + nents; sg < end; ++sg) {
589 unsigned long addr, size;
590 long npages, ofs;
591 dma_addr_t tend;
592
593 addr = sg->dma_address;
594 size = sg->dma_length;
595 if (!size)
596 break;
597
598 #if !DEBUG_NODIRECT
599 if (addr >= __direct_map_base
600 && addr < __direct_map_base + __direct_map_size) {
601 /* Nothing to do. */
602 DBGA(" (%ld) direct [%lx,%lx]\n",
603 sg - end + nents, addr, size);
604 continue;
605 }
606 #endif
607
608 DBGA(" (%ld) sg [%lx,%lx]\n",
609 sg - end + nents, addr, size);
610
611 npages = calc_npages((addr & ~PAGE_MASK) + size);
612 ofs = (addr - arena->dma_base) >> PAGE_SHIFT;
613 iommu_arena_free(arena, ofs, npages);
614
615 tend = addr + size - 1;
616 if (fbeg > addr) fbeg = addr;
617 if (fend < tend) fend = tend;
618 }
619
620 /*
621 If we're freeing ptes above the `next_entry' pointer (they
622 may have snuck back into the TLB since the last wrap flush),
623 we need to flush the TLB before reallocating the latter.
624 */
625 if ((fend - arena->dma_base) >> PAGE_SHIFT >= arena->next_entry)
626 alpha_mv.mv_pci_tbi(hose, fbeg, fend);
627
628 spin_unlock_irqrestore(&arena->lock, flags);
629
630 DBGA("pci_unmap_sg: %d entries\n", nents - (end - sg));
631 }
632
633 /* Return whether the given PCI device DMA address mask can be
634 supported properly. */
635
636 int
637 pci_dma_supported(struct pci_dev *pdev, dma_addr_t mask)
638 {
639 struct pci_controller *hose;
640 struct pci_iommu_arena *arena;
641
642 #if !DEBUG_NODIRECT
643 /* If there exists a direct map, and the mask fits either
644 MAX_DMA_ADDRESS defined such that GFP_DMA does something
645 useful, or the total system memory as shifted by the
646 map base. */
647 if (__direct_map_size != 0
648 && (__direct_map_base + MAX_DMA_ADDRESS-IDENT_ADDR-1 <= mask
649 || __direct_map_base + (max_low_pfn<<PAGE_SHIFT)-1 <= mask))
650 return 1;
651 #endif
652
653 /* Check that we have a scatter-gather arena that fits. */
654 hose = pdev ? pdev->sysdata : pci_isa_hose;
655 arena = hose->sg_isa;
656 if (arena && arena->dma_base + arena->size - 1 <= mask)
657 return 1;
658 arena = hose->sg_pci;
659 if (arena && arena->dma_base + arena->size - 1 <= mask)
660 return 1;
661
662 return 0;
663 }
664
665
666 /*
667 * AGP GART extensions to the IOMMU
668 */
669 int
670 iommu_reserve(struct pci_iommu_arena *arena, long pg_count, long align_mask)
671 {
672 unsigned long flags;
673 unsigned long *ptes;
674 long i, p;
675
676 if (!arena) return -EINVAL;
677
678 spin_lock_irqsave(&arena->lock, flags);
679
680 /* Search for N empty ptes. */
681 ptes = arena->ptes;
682 p = iommu_arena_find_pages(arena, pg_count, align_mask);
683 if (p < 0) {
684 spin_unlock_irqrestore(&arena->lock, flags);
685 return -1;
686 }
687
688 /* Success. Mark them all reserved (ie not zero and invalid)
689 for the iommu tlb that could load them from under us.
690 They will be filled in with valid bits by _bind() */
691 for (i = 0; i < pg_count; ++i)
692 ptes[p+i] = IOMMU_RESERVED_PTE;
693
694 arena->next_entry = p + pg_count;
695 spin_unlock_irqrestore(&arena->lock, flags);
696
697 return p;
698 }
699
700 int
701 iommu_release(struct pci_iommu_arena *arena, long pg_start, long pg_count)
702 {
703 unsigned long *ptes;
704 long i;
705
706 if (!arena) return -EINVAL;
707
708 ptes = arena->ptes;
709
710 /* Make sure they're all reserved first... */
711 for(i = pg_start; i < pg_start + pg_count; i++)
712 if (ptes[i] != IOMMU_RESERVED_PTE)
713 return -EBUSY;
714
715 iommu_arena_free(arena, pg_start, pg_count);
716 return 0;
717 }
718
719 int
720 iommu_bind(struct pci_iommu_arena *arena, long pg_start, long pg_count,
721 unsigned long *physaddrs)
722 {
723 unsigned long flags;
724 unsigned long *ptes;
725 long i, j;
726
727 if (!arena) return -EINVAL;
728
729 spin_lock_irqsave(&arena->lock, flags);
730
731 ptes = arena->ptes;
732
733 for(j = pg_start; j < pg_start + pg_count; j++) {
734 if (ptes[j] != IOMMU_RESERVED_PTE) {
735 spin_unlock_irqrestore(&arena->lock, flags);
736 return -EBUSY;
737 }
738 }
739
740 for(i = 0, j = pg_start; i < pg_count; i++, j++)
741 ptes[j] = mk_iommu_pte(physaddrs[i]);
742
743 spin_unlock_irqrestore(&arena->lock, flags);
744
745 return 0;
746 }
747
748 int
749 iommu_unbind(struct pci_iommu_arena *arena, long pg_start, long pg_count)
750 {
751 unsigned long *p;
752 long i;
753
754 if (!arena) return -EINVAL;
755
756 p = arena->ptes + pg_start;
757 for(i = 0; i < pg_count; i++)
758 p[i] = IOMMU_RESERVED_PTE;
759
760 return 0;
761 }
762