File: /usr/src/linux/drivers/atm/iphase.h
1 /******************************************************************************
2 Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Interphase Corporation <www.iphase.com>
5 Version: 1.0
6 iphase.h: This is the header file for iphase.c.
7 *******************************************************************************
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The followings are the change log and history:
25
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
31 Add the CBR support.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
37 Add SMP support.
38
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
40
41 *******************************************************************************/
42
43 #ifndef IPHASE_H
44 #define IPHASE_H
45
46 #include <linux/config.h>
47
48 /************************ IADBG DEFINE *********************************/
49 /* IADebugFlag Bit Map */
50 #define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
51 #define IF_IADBG_TX 0x00000002 // debug TX
52 #define IF_IADBG_RX 0x00000004 // debug RX
53 #define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
54 #define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
55 #define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
56 #define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
57 #define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
58 #define IF_IADBG_ERR 0x00000100 // debug system error
59 #define IF_IADBG_EVENT 0x00000200 // debug event
60 #define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
61 #define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
62 #define IF_IADBG_LOUD 0x00004000 // debugging info
63 #define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
64 #define IF_IADBG_CBR 0x00100000 //
65 #define IF_IADBG_UBR 0x00200000 //
66 #define IF_IADBG_ABR 0x00400000 //
67 #define IF_IADBG_DESC 0x01000000 //
68 #define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
69 #define IF_IADBG_RESET 0x04000000
70
71 extern unsigned int IADebugFlag;
72
73 #define IF_IADBG(f) if (IADebugFlag & (f))
74
75 #ifdef CONFIG_ATM_IA_DEBUG /* Debug build */
76
77 #define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
78 #define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
79 #define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
80
81 #define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
82 #define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
83 #define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
84 #define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
85 #define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
86
87 #define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
88 #define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
89 #define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
90
91 #define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
92 #define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
93 #define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
94 #define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
95
96 #define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
97 #define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
98 #define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
99 #define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
100 #define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
101
102 #else /* free build */
103 #define IF_LOUD(A)
104 #define IF_VERY_LOUD(A)
105 #define IF_INIT_ADAPTER(A)
106 #define IF_INIT(A)
107 #define IF_SUNI_STAT(A)
108 #define IF_PVC_CHKPKT(A)
109 #define IF_QUERY_INFO(A)
110 #define IF_COPY_OVER(A)
111 #define IF_HANG(A)
112 #define IF_INTR(A)
113 #define IF_DIS_INTR(A)
114 #define IF_EN_INTR(A)
115 #define IF_TX(A)
116 #define IF_RX(A)
117 #define IF_TXDEBUG(A)
118 #define IF_VC(A)
119 #define IF_ERR(A)
120 #define IF_CBR(A)
121 #define IF_UBR(A)
122 #define IF_ABR(A)
123 #define IF_SHUTDOWN(A)
124 #define DbgPrint(A)
125 #define IF_EVENT(A)
126 #define IF_TXPKT(A)
127 #define IF_RXPKT(A)
128 #endif /* CONFIG_ATM_IA_DEBUG */
129
130 #define isprint(a) ((a >=' ')&&(a <= '~'))
131 #define ATM_DESC(skb) (skb->protocol)
132 #define IA_SKB_STATE(skb) (skb->protocol)
133 #define IA_DLED 1
134 #define IA_TX_DONE 2
135
136 /* iadbg defines */
137 #define IA_CMD 0x7749
138 typedef struct {
139 int cmd;
140 int sub_cmd;
141 int len;
142 u32 maddr;
143 int status;
144 void *buf;
145 } IA_CMDBUF, *PIA_CMDBUF;
146
147 /* cmds */
148 #define MEMDUMP 0x01
149
150 /* sub_cmds */
151 #define MEMDUMP_SEGREG 0x2
152 #define MEMDUMP_DEV 0x1
153 #define MEMDUMP_REASSREG 0x3
154 #define MEMDUMP_FFL 0x4
155 #define READ_REG 0x5
156 #define WAKE_DBG_WAIT 0x6
157
158 /************************ IADBG DEFINE END ***************************/
159
160 #define Boolean(x) ((x) ? 1 : 0)
161 #define NR_VCI 1024 /* number of VCIs */
162 #define NR_VCI_LD 10 /* log2(NR_VCI) */
163 #define NR_VCI_4K 4096 /* number of VCIs */
164 #define NR_VCI_4K_LD 12 /* log2(NR_VCI) */
165 #define MEM_VALID 0xfffffff0 /* mask base address with this */
166
167 #ifndef PCI_VENDOR_ID_IPHASE
168 #define PCI_VENDOR_ID_IPHASE 0x107e
169 #endif
170 #ifndef PCI_DEVICE_ID_IPHASE_5575
171 #define PCI_DEVICE_ID_IPHASE_5575 0x0008
172 #endif
173 #define DEV_LABEL "ia"
174 #define PCR 207692
175 #define ICR 100000
176 #define MCR 0
177 #define TBE 1000
178 #define FRTT 1
179 #define RIF 2
180 #define RDF 4
181 #define NRMCODE 5 /* 0 - 7 */
182 #define TRMCODE 3 /* 0 - 7 */
183 #define CDFCODE 6
184 #define ATDFCODE 2 /* 0 - 15 */
185
186 /*---------------------- Packet/Cell Memory ------------------------*/
187 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
188 #define DFL_TX_BUF_SZ 10240 /* 10 K buffers */
189 #define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
190 - descriptor 0 unused */
191 #define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
192 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
193 #define DFL_RX_BUF_SZ 10240 /* 10k buffers */
194 #define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
195 - descriptor 0 unused */
196
197 struct cpcs_trailer
198 {
199 u_short control;
200 u_short length;
201 u_int crc32;
202 };
203
204 struct ia_vcc
205 {
206 int rxing;
207 int txing;
208 int NumCbrEntry;
209 u32 pcr;
210 u32 saved_tx_quota;
211 int flow_inc;
212 struct sk_buff_head txing_skb;
213 int ltimeout;
214 u8 vc_desc_cnt;
215
216 };
217
218 struct abr_vc_table
219 {
220 u_char status;
221 u_char rdf;
222 u_short air;
223 u_int res[3];
224 u_int req_rm_cell_data1;
225 u_int req_rm_cell_data2;
226 u_int add_rm_cell_data1;
227 u_int add_rm_cell_data2;
228 };
229
230 /* 32 byte entries */
231 struct main_vc
232 {
233 u_short type;
234 #define ABR 0x8000
235 #define UBR 0xc000
236 #define CBR 0x0000
237 /* ABR fields */
238 u_short nrm;
239 u_short trm;
240 u_short rm_timestamp_hi;
241 u_short rm_timestamp_lo:8,
242 crm:8;
243 u_short remainder; /* ABR and UBR fields - last 10 bits*/
244 u_short next_vc_sched;
245 u_short present_desc; /* all classes */
246 u_short last_cell_slot; /* ABR and UBR */
247 u_short pcr;
248 u_short fraction;
249 u_short icr;
250 u_short atdf;
251 u_short mcr;
252 u_short acr;
253 u_short unack:8,
254 status:8; /* all classes */
255 #define UIOLI 0x80
256 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
257 #define ABR_STATE 0x02
258
259 };
260
261
262 /* 8 byte entries */
263 struct ext_vc
264 {
265 u_short atm_hdr1;
266 u_short atm_hdr2;
267 u_short last_desc;
268 u_short out_of_rate_link; /* reserved for UBR and CBR */
269 };
270
271
272 #define DLE_ENTRIES 256
273 #define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
274 #define TX_DLE_PSI 0x0001
275
276 /* Descriptor List Entries (DLE) */
277 struct dle
278 {
279 u32 sys_pkt_addr;
280 u32 local_pkt_addr;
281 u32 bytes;
282 u16 prq_wr_ptr_data;
283 u16 mode;
284 };
285
286 struct dle_q
287 {
288 struct dle *start;
289 struct dle *end;
290 struct dle *read;
291 struct dle *write;
292 };
293
294 struct free_desc_q
295 {
296 int desc; /* Descriptor number */
297 struct free_desc_q *next;
298 };
299
300 struct tx_buf_desc {
301 unsigned short desc_mode;
302 unsigned short vc_index;
303 unsigned short res1; /* reserved field */
304 unsigned short bytes;
305 unsigned short buf_start_hi;
306 unsigned short buf_start_lo;
307 unsigned short res2[10]; /* reserved field */
308 };
309
310
311 struct rx_buf_desc {
312 unsigned short desc_mode;
313 unsigned short vc_index;
314 unsigned short vpi;
315 unsigned short bytes;
316 unsigned short buf_start_hi;
317 unsigned short buf_start_lo;
318 unsigned short dma_start_hi;
319 unsigned short dma_start_lo;
320 unsigned short crc_upper;
321 unsigned short crc_lower;
322 unsigned short res:8, timeout:8;
323 unsigned short res2[5]; /* reserved field */
324 };
325
326 /*--------SAR stuff ---------------------*/
327
328 #define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
329 #define MAC1_LEN 4
330 #define MAC2_LEN 2
331
332 /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
333 #define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
334 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
335 #define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
336 #define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
337 #define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
338 #define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
339 #define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
340 #define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
341
342 /*------------ Bus interface control registers -----------------*/
343 #define IPHASE5575_BUS_CONTROL_REG 0x00
344 #define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
345 #define IPHASE5575_MAC1 0x02
346 #define IPHASE5575_REV 0x03
347 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
348 #define IPHASE5575_EXT_RESET 0x04
349 #define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
350 #define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
351 #define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
352 #define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
353 #define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
354 #define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
355 #define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
356 #define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
357
358 /* Bus Interface Control Register bits */
359 #define CTRL_FE_RST 0x80000000
360 #define CTRL_LED 0x40000000
361 #define CTRL_25MBPHY 0x10000000
362 #define CTRL_ENCMBMEM 0x08000000
363 #define CTRL_ENOFFSEG 0x01000000
364 #define CTRL_ERRMASK 0x00400000
365 #define CTRL_DLETMASK 0x00100000
366 #define CTRL_DLERMASK 0x00080000
367 #define CTRL_FEMASK 0x00040000
368 #define CTRL_SEGMASK 0x00020000
369 #define CTRL_REASSMASK 0x00010000
370 #define CTRL_CSPREEMPT 0x00002000
371 #define CTRL_B128 0x00000200
372 #define CTRL_B64 0x00000100
373 #define CTRL_B48 0x00000080
374 #define CTRL_B32 0x00000040
375 #define CTRL_B16 0x00000020
376 #define CTRL_B8 0x00000010
377
378 /* Bus Interface Status Register bits */
379 #define STAT_CMEMSIZ 0xc0000000
380 #define STAT_ADPARCK 0x20000000
381 #define STAT_RESVD 0x1fffff80
382 #define STAT_ERRINT 0x00000040
383 #define STAT_MARKINT 0x00000020
384 #define STAT_DLETINT 0x00000010
385 #define STAT_DLERINT 0x00000008
386 #define STAT_FEINT 0x00000004
387 #define STAT_SEGINT 0x00000002
388 #define STAT_REASSINT 0x00000001
389
390
391 /*--------------- Segmentation control registers -----------------*/
392 /* The segmentation registers are 16 bits access and the addresses
393 are defined as such so the addresses are the actual "offsets" */
394 #define IDLEHEADHI 0x00
395 #define IDLEHEADLO 0x01
396 #define MAXRATE 0x02
397 /* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */
398 #define RATE155 0x64b1 // 16 bits float format
399 #define MAX_ATM_155 352768 // Cells/second p.118
400 #define RATE25 0x5f9d
401
402 #define STPARMS 0x03
403 #define STPARMS_1K 0x008c
404 #define STPARMS_2K 0x0049
405 #define STPARMS_4K 0x0026
406 #define COMP_EN 0x4000
407 #define CBR_EN 0x2000
408 #define ABR_EN 0x0800
409 #define UBR_EN 0x0400
410
411 #define ABRUBR_ARB 0x04
412 #define RM_TYPE 0x05
413 /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
414 #define RM_TYPE_4_0 0x0100
415
416 #define SEG_COMMAND_REG 0x17
417 /* Values for the command register */
418 #define RESET_SEG 0x0055
419 #define RESET_SEG_STATE 0x00aa
420 #define RESET_TX_CELL_CTR 0x00cc
421
422 #define CBR_PTR_BASE 0x20
423 #define ABR_SBPTR_BASE 0x22
424 #define UBR_SBPTR_BASE 0x23
425 #define ABRWQ_BASE 0x26
426 #define UBRWQ_BASE 0x27
427 #define VCT_BASE 0x28
428 #define VCTE_BASE 0x29
429 #define CBR_TAB_BEG 0x2c
430 #define CBR_TAB_END 0x2d
431 #define PRQ_ST_ADR 0x30
432 #define PRQ_ED_ADR 0x31
433 #define PRQ_RD_PTR 0x32
434 #define PRQ_WR_PTR 0x33
435 #define TCQ_ST_ADR 0x34
436 #define TCQ_ED_ADR 0x35
437 #define TCQ_RD_PTR 0x36
438 #define TCQ_WR_PTR 0x37
439 #define SEG_QUEUE_BASE 0x40
440 #define SEG_DESC_BASE 0x41
441 #define MODE_REG_0 0x45
442 #define T_ONLINE 0x0002 /* (i)chipSAR is online */
443
444 #define MODE_REG_1 0x46
445 #define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
446
447 #define SEG_INTR_STATUS_REG 0x47
448 #define SEG_MASK_REG 0x48
449 #define TRANSMIT_DONE 0x0200
450 #define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
451 status registers as well as the mask register */
452
453 #define CELL_CTR_HIGH_AUTO 0x49
454 #define CELL_CTR_HIGH_NOAUTO 0xc9
455 #define CELL_CTR_LO_AUTO 0x4a
456 #define CELL_CTR_LO_NOAUTO 0xca
457
458 /* Diagnostic registers */
459 #define NEXTDESC 0x59
460 #define NEXTVC 0x5a
461 #define PSLOTCNT 0x5d
462 #define NEWDN 0x6a
463 #define NEWVC 0x6b
464 #define SBPTR 0x6c
465 #define ABRWQ_WRPTR 0x6f
466 #define ABRWQ_RDPTR 0x70
467 #define UBRWQ_WRPTR 0x71
468 #define UBRWQ_RDPTR 0x72
469 #define CBR_VC 0x73
470 #define ABR_SBVC 0x75
471 #define UBR_SBVC 0x76
472 #define ABRNEXTLINK 0x78
473 #define UBRNEXTLINK 0x79
474
475
476 /*----------------- Reassembly control registers ---------------------*/
477 /* The reassembly registers are 16 bits access and the addresses
478 are defined as such so the addresses are the actual "offsets" */
479 #define MODE_REG 0x00
480 #define R_ONLINE 0x0002 /* (i)chip is online */
481 #define IGN_RAW_FL 0x0004
482
483 #define PROTOCOL_ID 0x01
484 #define REASS_MASK_REG 0x02
485 #define REASS_INTR_STATUS_REG 0x03
486 /* Interrupt Status register bits */
487 #define RX_PKT_CTR_OF 0x8000
488 #define RX_ERR_CTR_OF 0x4000
489 #define RX_CELL_CTR_OF 0x1000
490 #define RX_FREEQ_EMPT 0x0200
491 #define RX_EXCPQ_FL 0x0080
492 #define RX_RAWQ_FL 0x0010
493 #define RX_EXCP_RCVD 0x0008
494 #define RX_PKT_RCVD 0x0004
495 #define RX_RAW_RCVD 0x0001
496
497 #define DRP_PKT_CNTR 0x04
498 #define ERR_CNTR 0x05
499 #define RAW_BASE_ADR 0x08
500 #define CELL_CTR0 0x0c
501 #define CELL_CTR1 0x0d
502 #define REASS_COMMAND_REG 0x0f
503 /* Values for command register */
504 #define RESET_REASS 0x0055
505 #define RESET_REASS_STATE 0x00aa
506 #define RESET_DRP_PKT_CNTR 0x00f1
507 #define RESET_ERR_CNTR 0x00f2
508 #define RESET_CELL_CNTR 0x00f8
509 #define RESET_REASS_ALL_REGS 0x00ff
510
511 #define REASS_DESC_BASE 0x10
512 #define VC_LKUP_BASE 0x11
513 #define REASS_TABLE_BASE 0x12
514 #define REASS_QUEUE_BASE 0x13
515 #define PKT_TM_CNT 0x16
516 #define TMOUT_RANGE 0x17
517 #define INTRVL_CNTR 0x18
518 #define TMOUT_INDX 0x19
519 #define VP_LKUP_BASE 0x1c
520 #define VP_FILTER 0x1d
521 #define ABR_LKUP_BASE 0x1e
522 #define FREEQ_ST_ADR 0x24
523 #define FREEQ_ED_ADR 0x25
524 #define FREEQ_RD_PTR 0x26
525 #define FREEQ_WR_PTR 0x27
526 #define PCQ_ST_ADR 0x28
527 #define PCQ_ED_ADR 0x29
528 #define PCQ_RD_PTR 0x2a
529 #define PCQ_WR_PTR 0x2b
530 #define EXCP_Q_ST_ADR 0x2c
531 #define EXCP_Q_ED_ADR 0x2d
532 #define EXCP_Q_RD_PTR 0x2e
533 #define EXCP_Q_WR_PTR 0x2f
534 #define CC_FIFO_ST_ADR 0x34
535 #define CC_FIFO_ED_ADR 0x35
536 #define CC_FIFO_RD_PTR 0x36
537 #define CC_FIFO_WR_PTR 0x37
538 #define STATE_REG 0x38
539 #define BUF_SIZE 0x42
540 #define XTRA_RM_OFFSET 0x44
541 #define DRP_PKT_CNTR_NC 0x84
542 #define ERR_CNTR_NC 0x85
543 #define CELL_CNTR0_NC 0x8c
544 #define CELL_CNTR1_NC 0x8d
545
546 /* State Register bits */
547 #define EXCPQ_EMPTY 0x0040
548 #define PCQ_EMPTY 0x0010
549 #define FREEQ_EMPTY 0x0004
550
551
552 /*----------------- Front End registers/ DMA control --------------*/
553 /* There is a lot of documentation error regarding these offsets ???
554 eg:- 2 offsets given 800, a00 for rx counter
555 similarly many others
556 Remember again that the offsets are to be 4*register number, so
557 correct the #defines here
558 */
559 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
560 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
561 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
562 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
563
564 /*--------------------------- RAM ---------------------------*/
565 /* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */
566
567 /* Segmentation Control Memory map */
568 #define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
569 #define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
570 #define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
571 #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
572 #define UBR_SCHED_TABLE 0x3000 /* UBR Table */
573 #define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
574 #define ABR_SCHED_TABLE 0x5000 /* ABR Table */
575 #define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
576 #define EXT_VC_TABLE 0x6000 /* Extended VC Table */
577 #define MAIN_VC_TABLE 0x8000 /* Main VC Table */
578 #define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */
579 #define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
580 Buffer Descriptor Table */
581
582 /* These are used as table offsets in Descriptor Table address generation */
583 #define DESC_MODE 0x0
584 #define VC_INDEX 0x1
585 #define BYTE_CNT 0x3
586 #define PKT_START_HI 0x4
587 #define PKT_START_LO 0x5
588
589 /* Descriptor Mode Word Bits */
590 #define EOM_EN 0x0800
591 #define AAL5 0x0100
592 #define APP_CRC32 0x0400
593 #define CMPL_INT 0x1000
594
595 #define TABLE_ADDRESS(db, dn, to) \
596 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
597
598 /* Reassembly Control Memory Map */
599 #define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
600 #define VP_TABLE 0x5c00 /* VP Table */
601 #define EXCEPTION_Q 0x5e00 /* Exception Queue */
602 #define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
603 #define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
604 #define REASS_TABLE 0x7000 /* Reassembly Table */
605 #define RX_VC_TABLE 0x7800 /* VC Table */
606 #define ABR_VC_TABLE 0x8000 /* ABR VC Table */
607 #define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
608 Buffer Descriptor Table */
609 #define VP_TABLE_SZ 256 /* Number of entries in VPTable */
610 #define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
611 #define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
612 /* Buffer Descriptor Table */
613 #define RX_ACT 0x8000
614 #define RX_VPVC 0x4000
615 #define RX_CNG 0x0040
616 #define RX_CER 0x0008
617 #define RX_PTE 0x0004
618 #define RX_OFL 0x0002
619 #define NUM_RX_EXCP 32
620
621 /* Reassembly Table */
622 #define NO_AAL5_PKT 0x0000
623 #define AAL5_PKT_REASSEMBLED 0x4000
624 #define AAL5_PKT_TERMINATED 0x8000
625 #define RAW_PKT 0xc000
626 #define REASS_ABR 0x2000
627
628 /*-------------------- Base Registers --------------------*/
629 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
630 #define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
631 #define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
632 #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
633 #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
634
635 typedef volatile u_int freg_t;
636 typedef u_int rreg_t;
637
638 typedef struct _ffredn_t {
639 freg_t idlehead_high; /* Idle cell header (high) */
640 freg_t idlehead_low; /* Idle cell header (low) */
641 freg_t maxrate; /* Maximum rate */
642 freg_t stparms; /* Traffic Management Parameters */
643 freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
644 freg_t rm_type; /* */
645 u_int filler5[0x17 - 0x06];
646 freg_t cmd_reg; /* Command register */
647 u_int filler18[0x20 - 0x18];
648 freg_t cbr_base; /* CBR Pointer Base */
649 freg_t vbr_base; /* VBR Pointer Base */
650 freg_t abr_base; /* ABR Pointer Base */
651 freg_t ubr_base; /* UBR Pointer Base */
652 u_int filler24;
653 freg_t vbrwq_base; /* VBR Wait Queue Base */
654 freg_t abrwq_base; /* ABR Wait Queue Base */
655 freg_t ubrwq_base; /* UBR Wait Queue Base */
656 freg_t vct_base; /* Main VC Table Base */
657 freg_t vcte_base; /* Extended Main VC Table Base */
658 u_int filler2a[0x2C - 0x2A];
659 freg_t cbr_tab_beg; /* CBR Table Begin */
660 freg_t cbr_tab_end; /* CBR Table End */
661 freg_t cbr_pointer; /* CBR Pointer */
662 u_int filler2f[0x30 - 0x2F];
663 freg_t prq_st_adr; /* Packet Ready Queue Start Address */
664 freg_t prq_ed_adr; /* Packet Ready Queue End Address */
665 freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
666 freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
667 freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
668 freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
669 freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
670 freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
671 u_int filler38[0x40 - 0x38];
672 freg_t queue_base; /* Base address for PRQ and TCQ */
673 freg_t desc_base; /* Base address of descriptor table */
674 u_int filler42[0x45 - 0x42];
675 freg_t mode_reg_0; /* Mode register 0 */
676 freg_t mode_reg_1; /* Mode register 1 */
677 freg_t intr_status_reg;/* Interrupt Status register */
678 freg_t mask_reg; /* Mask Register */
679 freg_t cell_ctr_high1; /* Total cell transfer count (high) */
680 freg_t cell_ctr_lo1; /* Total cell transfer count (low) */
681 freg_t state_reg; /* Status register */
682 u_int filler4c[0x58 - 0x4c];
683 freg_t curr_desc_num; /* Contains the current descriptor num */
684 freg_t next_desc; /* Next descriptor */
685 freg_t next_vc; /* Next VC */
686 u_int filler5b[0x5d - 0x5b];
687 freg_t present_slot_cnt;/* Present slot count */
688 u_int filler5e[0x6a - 0x5e];
689 freg_t new_desc_num; /* New descriptor number */
690 freg_t new_vc; /* New VC */
691 freg_t sched_tbl_ptr; /* Schedule table pointer */
692 freg_t vbrwq_wptr; /* VBR wait queue write pointer */
693 freg_t vbrwq_rptr; /* VBR wait queue read pointer */
694 freg_t abrwq_wptr; /* ABR wait queue write pointer */
695 freg_t abrwq_rptr; /* ABR wait queue read pointer */
696 freg_t ubrwq_wptr; /* UBR wait queue write pointer */
697 freg_t ubrwq_rptr; /* UBR wait queue read pointer */
698 freg_t cbr_vc; /* CBR VC */
699 freg_t vbr_sb_vc; /* VBR SB VC */
700 freg_t abr_sb_vc; /* ABR SB VC */
701 freg_t ubr_sb_vc; /* UBR SB VC */
702 freg_t vbr_next_link; /* VBR next link */
703 freg_t abr_next_link; /* ABR next link */
704 freg_t ubr_next_link; /* UBR next link */
705 u_int filler7a[0x7c-0x7a];
706 freg_t out_rate_head; /* Out of rate head */
707 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
708 freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
709 freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
710 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
711 } ffredn_t;
712
713 typedef struct _rfredn_t {
714 rreg_t mode_reg_0; /* Mode register 0 */
715 rreg_t protocol_id; /* Protocol ID */
716 rreg_t mask_reg; /* Mask Register */
717 rreg_t intr_status_reg;/* Interrupt status register */
718 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
719 rreg_t err_cntr; /* Error Counter (cleared on read) */
720 u_int filler6[0x08 - 0x06];
721 rreg_t raw_base_adr; /* Base addr for raw cell Q */
722 u_int filler2[0x0c - 0x09];
723 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
724 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
725 u_int filler3[0x0f - 0x0e];
726 rreg_t cmd_reg; /* Command register */
727 rreg_t desc_base; /* Base address for description table */
728 rreg_t vc_lkup_base; /* Base address for VC lookup table */
729 rreg_t reass_base; /* Base address for reassembler table */
730 rreg_t queue_base; /* Base address for Communication queue */
731 u_int filler14[0x16 - 0x14];
732 rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
733 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
734 rreg_t intrvl_cntr; /* Packet aging interval counter */
735 rreg_t tmout_indx; /* index of pkt being tested for aging */
736 u_int filler1a[0x1c - 0x1a];
737 rreg_t vp_lkup_base; /* Base address for VP lookup table */
738 rreg_t vp_filter; /* VP filter register */
739 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
740 u_int filler1f[0x24 - 0x1f];
741 rreg_t fdq_st_adr; /* Free desc queue start address */
742 rreg_t fdq_ed_adr; /* Free desc queue end address */
743 rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
744 rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
745 rreg_t pcq_st_adr; /* Packet Complete queue start address */
746 rreg_t pcq_ed_adr; /* Packet Complete queue end address */
747 rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
748 rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
749 rreg_t excp_st_adr; /* Exception queue start address */
750 rreg_t excp_ed_adr; /* Exception queue end address */
751 rreg_t excp_rd_ptr; /* Exception queue read pointer */
752 rreg_t excp_wr_ptr; /* Exception queue write pointer */
753 u_int filler30[0x34 - 0x30];
754 rreg_t raw_st_adr; /* Raw Cell start address */
755 rreg_t raw_ed_adr; /* Raw Cell end address */
756 rreg_t raw_rd_ptr; /* Raw Cell read pointer */
757 rreg_t raw_wr_ptr; /* Raw Cell write pointer */
758 rreg_t state_reg; /* State Register */
759 u_int filler39[0x42 - 0x39];
760 rreg_t buf_size; /* Buffer size */
761 u_int filler43;
762 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
763 u_int filler45[0x84 - 0x45];
764 rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
765 rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
766 u_int filler86[0x8c - 0x86];
767 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
768 rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */
769 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
770 } rfredn_t;
771
772 typedef struct {
773 /* Atlantic */
774 ffredn_t ffredn; /* F FRED */
775 rfredn_t rfredn; /* R FRED */
776 } ia_regs_t;
777
778 typedef struct {
779 u_short f_vc_type; /* VC type */
780 u_short f_nrm; /* Nrm */
781 u_short f_nrmexp; /* Nrm Exp */
782 u_short reserved6; /* */
783 u_short f_crm; /* Crm */
784 u_short reserved10; /* Reserved */
785 u_short reserved12; /* Reserved */
786 u_short reserved14; /* Reserved */
787 u_short last_cell_slot; /* last_cell_slot_count */
788 u_short f_pcr; /* Peak Cell Rate */
789 u_short fraction; /* fraction */
790 u_short f_icr; /* Initial Cell Rate */
791 u_short f_cdf; /* */
792 u_short f_mcr; /* Minimum Cell Rate */
793 u_short f_acr; /* Allowed Cell Rate */
794 u_short f_status; /* */
795 } f_vc_abr_entry;
796
797 typedef struct {
798 u_short r_status_rdf; /* status + RDF */
799 u_short r_air; /* AIR */
800 u_short reserved4[14]; /* Reserved */
801 } r_vc_abr_entry;
802
803 #define MRM 3
804 #define MIN(x,y) ((x) < (y)) ? (x) : (y)
805
806 typedef struct srv_cls_param {
807 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
808 u32 pcr; /* Peak Cell Rate (24-bit) */
809 /* VBR parameters */
810 u32 scr; /* sustainable cell rate */
811 u32 max_burst_size; /* ?? cell rate or data rate */
812
813 /* ABR only UNI 4.0 Parameters */
814 u32 mcr; /* Min Cell Rate (24-bit) */
815 u32 icr; /* Initial Cell Rate (24-bit) */
816 u32 tbe; /* Transient Buffer Exposure (24-bit) */
817 u32 frtt; /* Fixed Round Trip Time (24-bit) */
818
819 #if 0 /* Additional Parameters of TM 4.0 */
820 bits 31 30 29 28 27-25 24-22 21-19 18-9
821 -----------------------------------------------------------------------------
822 | NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
823 -----------------------------------------------------------------------------
824 #endif /* 0 */
825
826 u8 nrm; /* Max # of Cells for each forward RM
827 cell (3-bit) */
828 u8 trm; /* Time between forward RM cells (3-bit) */
829 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
830 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
831 u8 rif; /* Rate Increment Factor (4-bit) */
832 u8 rdf; /* Rate Decrease Factor (4-bit) */
833 u8 reserved; /* 8 bits to keep structure word aligned */
834 } srv_cls_param_t;
835
836 struct testTable_t {
837 u16 lastTime;
838 u16 fract;
839 u8 vc_status;
840 };
841
842 typedef struct {
843 u16 vci;
844 u16 error;
845 } RX_ERROR_Q;
846
847 typedef struct {
848 u8 active: 1;
849 u8 abr: 1;
850 u8 ubr: 1;
851 u8 cnt: 5;
852 #define VC_ACTIVE 0x01
853 #define VC_ABR 0x02
854 #define VC_UBR 0x04
855 } vcstatus_t;
856
857 struct ia_rfL_t {
858 u32 fdq_st; /* Free desc queue start address */
859 u32 fdq_ed; /* Free desc queue end address */
860 u32 fdq_rd; /* Free desc queue read pointer */
861 u32 fdq_wr; /* Free desc queue write pointer */
862 u32 pcq_st; /* Packet Complete queue start address */
863 u32 pcq_ed; /* Packet Complete queue end address */
864 u32 pcq_rd; /* Packet Complete queue read pointer */
865 u32 pcq_wr; /* Packet Complete queue write pointer */
866 };
867
868 struct ia_ffL_t {
869 u32 prq_st; /* Packet Ready Queue Start Address */
870 u32 prq_ed; /* Packet Ready Queue End Address */
871 u32 prq_wr; /* Packet Ready Queue write pointer */
872 u32 tcq_st; /* Transmit Complete Queue Start Address*/
873 u32 tcq_ed; /* Transmit Complete Queue End Address */
874 u32 tcq_rd; /* Transmit Complete Queue read pointer */
875 };
876
877 struct desc_tbl_t {
878 u32 timestamp;
879 struct ia_vcc *iavcc;
880 struct sk_buff *txskb;
881 };
882
883 typedef struct ia_rtn_q {
884 struct desc_tbl_t data;
885 struct ia_rtn_q *next, *tail;
886 } IARTN_Q;
887
888 #define SUNI_LOSV 0x04
889 typedef struct {
890 u32 suni_master_reset; /* SUNI Master Reset and Identity */
891 u32 suni_master_config; /* SUNI Master Configuration */
892 u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */
893 u32 suni_reserved1; /* Reserved */
894 u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */
895 u32 suni_master_control; /* SUNI Master Clock Monitor */
896 u32 suni_reserved2[10]; /* Reserved */
897
898 u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */
899 u32 suni_rsop_status; /* RSOP Status/Interrupt States */
900 u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */
901 u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */
902
903 u32 suni_tsop_control; /* TSOP Control */
904 u32 suni_tsop_diag; /* TSOP Disgnostics */
905 u32 suni_tsop_reserved[2]; /* TSOP Reserved */
906
907 u32 suni_rlop_cs; /* RLOP Control/Status */
908 u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */
909 u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */
910 u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */
911 u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */
912 u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */
913 u32 suni_rlop_line_febe; /* RLOP Line FEBE */
914 u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */
915
916 u32 suni_tlop_control; /* TLOP Control */
917 u32 suni_tlop_disg; /* TLOP Disgnostics */
918 u32 suni_tlop_reserved[14]; /* TLOP Reserved */
919
920 u32 suni_rpop_cs; /* RPOP Status/Control */
921 u32 suni_rpop_intr; /* RPOP Interrupt/Status */
922 u32 suni_rpop_reserved; /* RPOP Reserved */
923 u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */
924 u32 suni_rpop_reserved1[3]; /* RPOP Reserved */
925 u32 suni_rpop_path_sig; /* RPOP Path Signal Label */
926 u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */
927 u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */
928 u32 suni_rpop_febel; /* RPOP Path FEBE LSB */
929 u32 suni_rpop_febem; /* RPOP Path FEBE MSB */
930 u32 suni_rpop_reserved2[4]; /* RPOP Reserved */
931
932 u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */
933 u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */
934 u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */
935 u32 suni_tpop_reserved1[2]; /* TPOP Reserved */
936 u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */
937 u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */
938 u32 suni_tpop_reserved2; /* TPOP Reserved */
939 u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */
940 u32 suni_tpop_path_status; /* TPOP Path Status */
941 u32 suni_tpop_reserved3[6]; /* TPOP Reserved */
942
943 u32 suni_racp_cs; /* RACP Control/Status */
944 u32 suni_racp_intr; /* RACP Interrupt Enable/Status */
945 u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */
946 u32 suni_racp_hdr_mask; /* RACP Match Header Mask */
947 u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */
948 u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */
949 u32 suni_racp_reserved[10]; /* RACP Reserved */
950
951 u32 suni_tacp_control; /* TACP Control */
952 u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */
953 u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */
954 u32 suni_tacp_reserved[5]; /* TACP Reserved */
955
956 u32 suni_reserved3[24]; /* Reserved */
957
958 u32 suni_master_test; /* SUNI Master Test */
959 u32 suni_reserved_test; /* SUNI Reserved for Test */
960 } IA_SUNI;
961
962
963 typedef struct _SUNI_STATS_
964 {
965 u32 valid; // 1 = oc3 PHY card
966 u32 carrier_detect; // GPIN input
967 // RSOP: receive section overhead processor
968 u16 rsop_oof_state; // 1 = out of frame
969 u16 rsop_lof_state; // 1 = loss of frame
970 u16 rsop_los_state; // 1 = loss of signal
971 u32 rsop_los_count; // loss of signal count
972 u32 rsop_bse_count; // section BIP-8 error count
973 // RLOP: receive line overhead processor
974 u16 rlop_ferf_state; // 1 = far end receive failure
975 u16 rlop_lais_state; // 1 = line AIS
976 u32 rlop_lbe_count; // BIP-24 count
977 u32 rlop_febe_count; // FEBE count;
978 // RPOP: receive path overhead processor
979 u16 rpop_lop_state; // 1 = LOP
980 u16 rpop_pais_state; // 1 = path AIS
981 u16 rpop_pyel_state; // 1 = path yellow alert
982 u32 rpop_bip_count; // path BIP-8 error count
983 u32 rpop_febe_count; // path FEBE error count
984 u16 rpop_psig; // path signal label value
985 // RACP: receive ATM cell processor
986 u16 racp_hp_state; // hunt/presync state
987 u32 racp_fu_count; // FIFO underrun count
988 u32 racp_fo_count; // FIFO overrun count
989 u32 racp_chcs_count; // correctable HCS error count
990 u32 racp_uchcs_count; // uncorrectable HCS error count
991 } IA_SUNI_STATS;
992
993 typedef struct iadev_t {
994 /*-----base pointers into (i)chipSAR+ address space */
995 u32 *phy; /* base pointer into phy(SUNI) */
996 u32 *dma; /* base pointer into DMA control
997 registers */
998 u32 *reg; /* base pointer to SAR registers
999 - Bus Interface Control Regs */
1000 u32 *seg_reg; /* base pointer to segmentation engine
1001 internal registers */
1002 u32 *reass_reg; /* base pointer to reassemble engine
1003 internal registers */
1004 u32 *ram; /* base pointer to SAR RAM */
1005 unsigned int seg_ram;
1006 unsigned int reass_ram;
1007 struct dle_q tx_dle_q;
1008 struct free_desc_q *tx_free_desc_qhead;
1009 struct sk_buff_head tx_dma_q, tx_backlog;
1010 spinlock_t tx_lock;
1011 IARTN_Q tx_return_q;
1012 u32 close_pending;
1013 #if LINUX_VERSION_CODE >= 0x20303
1014 wait_queue_head_t close_wait;
1015 wait_queue_head_t timeout_wait;
1016 #else
1017 struct wait_queue *close_wait;
1018 struct wait_queue *timeout_wait;
1019 #endif
1020 caddr_t *tx_buf;
1021 u16 num_tx_desc, tx_buf_sz, rate_limit;
1022 u32 tx_cell_cnt, tx_pkt_cnt;
1023 u32 MAIN_VC_TABLE_ADDR, EXT_VC_TABLE_ADDR, ABR_SCHED_TABLE_ADDR;
1024 struct dle_q rx_dle_q;
1025 struct free_desc_q *rx_free_desc_qhead;
1026 struct sk_buff_head rx_dma_q;
1027 spinlock_t rx_lock, misc_lock;
1028 struct atm_vcc **rx_open; /* list of all open VCs */
1029 u16 num_rx_desc, rx_buf_sz, rxing;
1030 u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif;
1031 u32 RX_DESC_BASE_ADDR;
1032 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1033 struct atm_dev *next_board; /* other iphase devices */
1034 struct pci_dev *pci;
1035 int mem;
1036 unsigned long base_diff; /* virtual - real base address */
1037 unsigned int real_base, base; /* real and virtual base address */
1038 unsigned int pci_map_size; /*pci map size of board */
1039 unsigned char irq;
1040 unsigned char bus;
1041 unsigned char dev_fn;
1042 u_short phy_type;
1043 u_short num_vc, memSize, memType;
1044 struct ia_ffL_t ffL;
1045 struct ia_rfL_t rfL;
1046 /* Suni stat */
1047 // IA_SUNI_STATS suni_stats;
1048 unsigned char carrier_detect;
1049 /* CBR related */
1050 // transmit DMA & Receive
1051 unsigned int tx_dma_cnt; // number of elements on dma queue
1052 unsigned int rx_dma_cnt; // number of elements on rx dma queue
1053 unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
1054 // receive MARK for Cell FIFO
1055 unsigned int rx_mark_cnt; // number of elements on mark queue
1056 unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.
1057 unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.
1058 unsigned int CbrEntryPt; // CBR Sched Table Entry Point.
1059 unsigned int Granularity; // CBR Granularity given Table Size.
1060 /* ABR related */
1061 unsigned int sum_mcr, sum_cbr, LineRate;
1062 unsigned int n_abr;
1063 struct desc_tbl_t *desc_tbl;
1064 u_short host_tcq_wr;
1065 struct testTable_t **testTable;
1066 } IADEV;
1067
1068
1069 #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1070 #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1071
1072 /******************* IDT77105 25MB/s PHY DEFINE *****************************/
1073 typedef struct {
1074 u_int mb25_master_ctrl; /* Master control */
1075 u_int mb25_intr_status; /* Interrupt status */
1076 u_int mb25_diag_control; /* Diagnostic control */
1077 u_int mb25_led_hec; /* LED driver and HEC status/control */
1078 u_int mb25_low_byte_counter; /* Low byte counter */
1079 u_int mb25_high_byte_counter; /* High byte counter */
1080 } ia_mb25_t;
1081
1082 /*
1083 * Master Control
1084 */
1085 #define MB25_MC_UPLO 0x80 /* UPLO */
1086 #define MB25_MC_DREC 0x40 /* Discard receive cell errors */
1087 #define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
1088 #define MB25_MC_TDPC 0x10 /* Transmit data parity check */
1089 #define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
1090 #define MB25_MC_HALTTX 0x04 /* Halt Tx */
1091 #define MB25_MC_UMS 0x02 /* UTOPIA mode select */
1092 #define MB25_MC_ENABLED 0x01 /* Enable interrupt */
1093
1094 /*
1095 * Interrupt Status
1096 */
1097 #define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
1098 #define MB25_IS_HECECR 0x20 /* HEC error cell received */
1099 #define MB25_IS_SCR 0x10 /* "Short Cell" Received */
1100 #define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
1101 #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1102 #define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
1103 #define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
1104
1105 /*
1106 * Diagnostic Control
1107 */
1108 #define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
1109 #define MB25_DC_RXCOS 0x40 /* RxClav operation select */
1110 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1111 #define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
1112 #define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
1113 #define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
1114 #define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
1115
1116 #define MB25_DC_LL 0x03 /* Line Loopback */
1117 #define MB25_DC_PL 0x02 /* PHY Loopback */
1118 #define MB25_DC_NM 0x00
1119
1120 #define FE_MASK 0x00F0
1121 #define FE_MULTI_MODE 0x0000
1122 #define FE_SINGLE_MODE 0x0010
1123 #define FE_UTP_OPTION 0x0020
1124 #define FE_25MBIT_PHY 0x0040
1125 #define FE_DS3_PHY 0x0080 /* DS3 */
1126 #define FE_E3_PHY 0x0090 /* E3 */
1127
1128 extern void ia_mb25_init (IADEV *);
1129
1130 /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
1131 typedef struct _suni_pm7345_t
1132 {
1133 u_int suni_config; /* SUNI Configuration */
1134 u_int suni_intr_enbl; /* SUNI Interrupt Enable */
1135 u_int suni_intr_stat; /* SUNI Interrupt Status */
1136 u_int suni_control; /* SUNI Control */
1137 u_int suni_id_reset; /* SUNI Reset and Identity */
1138 u_int suni_data_link_ctrl;
1139 u_int suni_rboc_conf_intr_enbl;
1140 u_int suni_rboc_stat;
1141 u_int suni_ds3_frm_cfg;
1142 u_int suni_ds3_frm_intr_enbl;
1143 u_int suni_ds3_frm_intr_stat;
1144 u_int suni_ds3_frm_stat;
1145 u_int suni_rfdl_cfg;
1146 u_int suni_rfdl_enbl_stat;
1147 u_int suni_rfdl_stat;
1148 u_int suni_rfdl_data;
1149 u_int suni_pmon_chng;
1150 u_int suni_pmon_intr_enbl_stat;
1151 u_int suni_reserved1[0x13-0x11];
1152 u_int suni_pmon_lcv_evt_cnt_lsb;
1153 u_int suni_pmon_lcv_evt_cnt_msb;
1154 u_int suni_pmon_fbe_evt_cnt_lsb;
1155 u_int suni_pmon_fbe_evt_cnt_msb;
1156 u_int suni_pmon_sez_det_cnt_lsb;
1157 u_int suni_pmon_sez_det_cnt_msb;
1158 u_int suni_pmon_pe_evt_cnt_lsb;
1159 u_int suni_pmon_pe_evt_cnt_msb;
1160 u_int suni_pmon_ppe_evt_cnt_lsb;
1161 u_int suni_pmon_ppe_evt_cnt_msb;
1162 u_int suni_pmon_febe_evt_cnt_lsb;
1163 u_int suni_pmon_febe_evt_cnt_msb;
1164 u_int suni_ds3_tran_cfg;
1165 u_int suni_ds3_tran_diag;
1166 u_int suni_reserved2[0x23-0x21];
1167 u_int suni_xfdl_cfg;
1168 u_int suni_xfdl_intr_st;
1169 u_int suni_xfdl_xmit_data;
1170 u_int suni_xboc_code;
1171 u_int suni_splr_cfg;
1172 u_int suni_splr_intr_en;
1173 u_int suni_splr_intr_st;
1174 u_int suni_splr_status;
1175 u_int suni_splt_cfg;
1176 u_int suni_splt_cntl;
1177 u_int suni_splt_diag_g1;
1178 u_int suni_splt_f1;
1179 u_int suni_cppm_loc_meters;
1180 u_int suni_cppm_chng_of_cppm_perf_meter;
1181 u_int suni_cppm_b1_err_cnt_lsb;
1182 u_int suni_cppm_b1_err_cnt_msb;
1183 u_int suni_cppm_framing_err_cnt_lsb;
1184 u_int suni_cppm_framing_err_cnt_msb;
1185 u_int suni_cppm_febe_cnt_lsb;
1186 u_int suni_cppm_febe_cnt_msb;
1187 u_int suni_cppm_hcs_err_cnt_lsb;
1188 u_int suni_cppm_hcs_err_cnt_msb;
1189 u_int suni_cppm_idle_un_cell_cnt_lsb;
1190 u_int suni_cppm_idle_un_cell_cnt_msb;
1191 u_int suni_cppm_rcv_cell_cnt_lsb;
1192 u_int suni_cppm_rcv_cell_cnt_msb;
1193 u_int suni_cppm_xmit_cell_cnt_lsb;
1194 u_int suni_cppm_xmit_cell_cnt_msb;
1195 u_int suni_rxcp_ctrl;
1196 u_int suni_rxcp_fctrl;
1197 u_int suni_rxcp_intr_en_sts;
1198 u_int suni_rxcp_idle_pat_h1;
1199 u_int suni_rxcp_idle_pat_h2;
1200 u_int suni_rxcp_idle_pat_h3;
1201 u_int suni_rxcp_idle_pat_h4;
1202 u_int suni_rxcp_idle_mask_h1;
1203 u_int suni_rxcp_idle_mask_h2;
1204 u_int suni_rxcp_idle_mask_h3;
1205 u_int suni_rxcp_idle_mask_h4;
1206 u_int suni_rxcp_cell_pat_h1;
1207 u_int suni_rxcp_cell_pat_h2;
1208 u_int suni_rxcp_cell_pat_h3;
1209 u_int suni_rxcp_cell_pat_h4;
1210 u_int suni_rxcp_cell_mask_h1;
1211 u_int suni_rxcp_cell_mask_h2;
1212 u_int suni_rxcp_cell_mask_h3;
1213 u_int suni_rxcp_cell_mask_h4;
1214 u_int suni_rxcp_hcs_cs;
1215 u_int suni_rxcp_lcd_cnt_threshold;
1216 u_int suni_reserved3[0x57-0x54];
1217 u_int suni_txcp_ctrl;
1218 u_int suni_txcp_intr_en_sts;
1219 u_int suni_txcp_idle_pat_h1;
1220 u_int suni_txcp_idle_pat_h2;
1221 u_int suni_txcp_idle_pat_h3;
1222 u_int suni_txcp_idle_pat_h4;
1223 u_int suni_txcp_idle_pat_h5;
1224 u_int suni_txcp_idle_payload;
1225 u_int suni_e3_frm_fram_options;
1226 u_int suni_e3_frm_maint_options;
1227 u_int suni_e3_frm_fram_intr_enbl;
1228 u_int suni_e3_frm_fram_intr_ind_stat;
1229 u_int suni_e3_frm_maint_intr_enbl;
1230 u_int suni_e3_frm_maint_intr_ind;
1231 u_int suni_e3_frm_maint_stat;
1232 u_int suni_reserved4;
1233 u_int suni_e3_tran_fram_options;
1234 u_int suni_e3_tran_stat_diag_options;
1235 u_int suni_e3_tran_bip_8_err_mask;
1236 u_int suni_e3_tran_maint_adapt_options;
1237 u_int suni_ttb_ctrl;
1238 u_int suni_ttb_trail_trace_id_stat;
1239 u_int suni_ttb_ind_addr;
1240 u_int suni_ttb_ind_data;
1241 u_int suni_ttb_exp_payload_type;
1242 u_int suni_ttb_payload_type_ctrl_stat;
1243 u_int suni_pad5[0x7f-0x71];
1244 u_int suni_master_test;
1245 u_int suni_pad6[0xff-0x80];
1246 }suni_pm7345_t;
1247
1248 #define SUNI_PM7345_T suni_pm7345_t
1249 #define SUNI_PM7345 0x20 /* Suni chip type */
1250 #define SUNI_PM5346 0x30 /* Suni chip type */
1251 /*
1252 * SUNI_PM7345 Configuration
1253 */
1254 #define SUNI_PM7345_CLB 0x01 /* Cell loopback */
1255 #define SUNI_PM7345_PLB 0x02 /* Payload loopback */
1256 #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
1257 #define SUNI_PM7345_LLB 0x80 /* Line loopback */
1258 #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
1259 #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
1260 #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
1261 #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
1262 /*
1263 * DS3 FRMR Interrupt Enable
1264 */
1265 #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1266 #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
1267 #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
1268 #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
1269 #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1270 #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1271 #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1272 #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1273
1274 /*
1275 * DS3 FRMR Status
1276 */
1277 #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
1278 #define SUNI_DS3_REDV 0x40 /* DS3 RED state */
1279 #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
1280 #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
1281 #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1282 #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1283 #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1284 #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1285
1286 /*
1287 * E3 FRMR Interrupt/Status
1288 */
1289 #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
1290 #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1291 #define SUNI_E3_LCVI 0x10 /* Line code violation intr */
1292 #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1293 #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1294 #define SUNI_E3_LOS 0x02 /* Loss of signal state */
1295 #define SUNI_E3_OOF 0x01 /* Out of frame state */
1296
1297 /*
1298 * E3 FRMR Maintenance Status
1299 */
1300 #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1301 #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
1302 #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
1303
1304 /*
1305 * RXCP Control/Status
1306 */
1307 #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
1308 #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
1309 #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
1310 #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
1311 #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
1312 #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
1313 #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
1314 #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
1315
1316 /*
1317 * RXCP Interrupt Enable/Status
1318 */
1319 #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
1320 #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
1321 #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
1322 #define SUNI_DS3_OOCDI 0x10 /* SYNC state */
1323 #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
1324 #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
1325 #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
1326 #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
1327
1328 extern void ia_suni_pm7345_init (IADEV *iadev);
1329
1330 ///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
1331
1332 /* ia_eeprom define*/
1333 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1334 #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
1335 #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1336 #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1337 /* 0x3 to 0xF are reserved for future */
1338
1339 #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1340 #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
1341 #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
1342 #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
1343
1344 #define NOVRAM_SIZE 64
1345 #define CMD_LEN 10
1346
1347 /***********
1348 *
1349 * Switches and defines for header files.
1350 *
1351 * The following defines are used to turn on and off
1352 * various options in the header files. Primarily useful
1353 * for debugging.
1354 *
1355 ***********/
1356
1357 /*
1358 * a list of the commands that can be sent to the NOVRAM
1359 */
1360
1361 #define EXTEND 0x100
1362 #define IAWRITE 0x140
1363 #define IAREAD 0x180
1364 #define ERASE 0x1c0
1365
1366 #define EWDS 0x00
1367 #define WRAL 0x10
1368 #define ERAL 0x20
1369 #define EWEN 0x30
1370
1371 /*
1372 * these bits duplicate the hw_flip.h register settings
1373 * note: how the data in / out bits are defined in the flipper specification
1374 */
1375
1376 #define NVCE 0x02
1377 #define NVSK 0x01
1378 #define NVDO 0x08
1379 #define NVDI 0x04
1380 /***********************
1381 *
1382 * This define ands the value and the current config register and puts
1383 * the result in the config register
1384 *
1385 ***********************/
1386
1387 #define CFG_AND(val) { \
1388 u32 t; \
1389 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1390 t &= (val); \
1391 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1392 }
1393
1394 /***********************
1395 *
1396 * This define ors the value and the current config register and puts
1397 * the result in the config register
1398 *
1399 ***********************/
1400
1401 #define CFG_OR(val) { \
1402 u32 t; \
1403 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1404 t |= (val); \
1405 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1406 }
1407
1408 /***********************
1409 *
1410 * Send a command to the NOVRAM, the command is in cmd.
1411 *
1412 * clear CE and SK. Then assert CE.
1413 * Clock each of the command bits out in the correct order with SK
1414 * exit with CE still asserted
1415 *
1416 ***********************/
1417
1418 #define NVRAM_CMD(cmd) { \
1419 int i; \
1420 u_short c = cmd; \
1421 CFG_AND(~(NVCE|NVSK)); \
1422 CFG_OR(NVCE); \
1423 for (i=0; i<CMD_LEN; i++) { \
1424 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1425 c <<= 1; \
1426 } \
1427 }
1428
1429 /***********************
1430 *
1431 * clear the CE, this must be used after each command is complete
1432 *
1433 ***********************/
1434
1435 #define NVRAM_CLR_CE {CFG_AND(~NVCE)}
1436
1437 /***********************
1438 *
1439 * clock the data bit in bitval out to the NOVRAM. The bitval must be
1440 * a 1 or 0, or the clockout operation is undefined
1441 *
1442 ***********************/
1443
1444 #define NVRAM_CLKOUT(bitval) { \
1445 CFG_AND(~NVDI); \
1446 CFG_OR((bitval) ? NVDI : 0); \
1447 CFG_OR(NVSK); \
1448 CFG_AND( ~NVSK); \
1449 }
1450
1451 /***********************
1452 *
1453 * clock the data bit in and return a 1 or 0, depending on the value
1454 * that was received from the NOVRAM
1455 *
1456 ***********************/
1457
1458 #define NVRAM_CLKIN(value) { \
1459 u32 _t; \
1460 CFG_OR(NVSK); \
1461 CFG_AND(~NVSK); \
1462 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1463 value = (_t & NVDO) ? 1 : 0; \
1464 }
1465
1466
1467 #endif /* IPHASE_H */
1468