File: /usr/src/linux/drivers/atm/nicstar.h
1 /******************************************************************************
2 *
3 * nicstar.h
4 *
5 * Header file for the nicstar device driver.
6 *
7 * Author: Rui Prior (rprior@inescn.pt)
8 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
9 *
10 * (C) INESC 1998
11 *
12 ******************************************************************************/
13
14
15 #ifndef _LINUX_NICSTAR_H_
16 #define _LINUX_NICSTAR_H_
17
18
19 /* Includes *******************************************************************/
20
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/uio.h>
24 #include <linux/skbuff.h>
25 #include <linux/atmdev.h>
26 #include <linux/atm_nicstar.h>
27
28
29 /* Options ********************************************************************/
30
31 #undef NS_DEBUG_SPINLOCKS
32
33 #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
34 controlled by the device driver. Must
35 be <= 5 */
36
37 #undef RCQ_SUPPORT /* Do not define this for now */
38
39 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
40 #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */
41
42 #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */
43 #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */
44 #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */
45 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
46
47 #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
48 Define 4096 only if (all) your card(s)
49 have 32K x 32bit SRAM, in which case
50 setting this to 16384 will just waste a
51 lot of memory.
52 Setting this to 4096 for a card with
53 128K x 32bit SRAM will limit the maximum
54 VCI. */
55
56 /*#define NS_PCI_LATENCY 64*/ /* Must be a multiple of 32 */
57
58 /* Number of buffers initially allocated */
59 #define NUM_SB 32 /* Must be even */
60 #define NUM_LB 24 /* Must be even */
61 #define NUM_HB 8 /* Pre-allocated huge buffers */
62 #define NUM_IOVB 48 /* Iovec buffers */
63
64 /* Lower level for count of buffers */
65 #define MIN_SB 8 /* Must be even */
66 #define MIN_LB 8 /* Must be even */
67 #define MIN_HB 6
68 #define MIN_IOVB 8
69
70 /* Upper level for count of buffers */
71 #define MAX_SB 64 /* Must be even, <= 508 */
72 #define MAX_LB 48 /* Must be even, <= 508 */
73 #define MAX_HB 10
74 #define MAX_IOVB 80
75
76 /* These are the absolute maximum allowed for the ioctl() */
77 #define TOP_SB 256 /* Must be even, <= 508 */
78 #define TOP_LB 128 /* Must be even, <= 508 */
79 #define TOP_HB 64
80 #define TOP_IOVB 256
81
82
83 #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
84 #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
85
86 #undef ENABLE_TSQFIE
87
88 #define SCQFULL_TIMEOUT (5 * HZ)
89
90 #define NS_POLL_PERIOD (HZ)
91
92 #define PCR_TOLERANCE (1.0001)
93
94
95
96 /* ESI stuff ******************************************************************/
97
98 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
99
100
101 /* #defines *******************************************************************/
102
103 #define NS_IOREMAP_SIZE 4096
104
105 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
106 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
107
108 #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */
109 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
110 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
112
113 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
114 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
115
116 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
117
118 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
119 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
120
121
122 /* NICStAR structures located in host memory **********************************/
123
124
125
126 /* RSQ - Receive Status Queue
127 *
128 * Written by the NICStAR, read by the device driver.
129 */
130
131 typedef struct ns_rsqe
132 {
133 u32 word_1;
134 u32 buffer_handle;
135 u32 final_aal5_crc32;
136 u32 word_4;
137 } ns_rsqe;
138
139 #define ns_rsqe_vpi(ns_rsqep) \
140 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
141 #define ns_rsqe_vci(ns_rsqep) \
142 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
143
144 #define NS_RSQE_VALID 0x80000000
145 #define NS_RSQE_NZGFC 0x00004000
146 #define NS_RSQE_EOPDU 0x00002000
147 #define NS_RSQE_BUFSIZE 0x00001000
148 #define NS_RSQE_CONGESTION 0x00000800
149 #define NS_RSQE_CLP 0x00000400
150 #define NS_RSQE_CRCERR 0x00000200
151
152 #define NS_RSQE_BUFSIZE_SM 0x00000000
153 #define NS_RSQE_BUFSIZE_LG 0x00001000
154
155 #define ns_rsqe_valid(ns_rsqep) \
156 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
157 #define ns_rsqe_nzgfc(ns_rsqep) \
158 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
159 #define ns_rsqe_eopdu(ns_rsqep) \
160 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
161 #define ns_rsqe_bufsize(ns_rsqep) \
162 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
163 #define ns_rsqe_congestion(ns_rsqep) \
164 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
165 #define ns_rsqe_clp(ns_rsqep) \
166 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
167 #define ns_rsqe_crcerr(ns_rsqep) \
168 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
169
170 #define ns_rsqe_cellcount(ns_rsqep) \
171 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
172 #define ns_rsqe_init(ns_rsqep) \
173 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
174
175 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
176 #define NS_RSQ_ALIGNMENT NS_RSQSIZE
177
178
179
180 /* RCQ - Raw Cell Queue
181 *
182 * Written by the NICStAR, read by the device driver.
183 */
184
185 typedef struct cell_payload
186 {
187 u32 word[12];
188 } cell_payload;
189
190 typedef struct ns_rcqe
191 {
192 u32 word_1;
193 u32 word_2;
194 u32 word_3;
195 u32 word_4;
196 cell_payload payload;
197 } ns_rcqe;
198
199 #define NS_RCQE_SIZE 64 /* bytes */
200
201 #define ns_rcqe_islast(ns_rcqep) \
202 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
203 #define ns_rcqe_cellheader(ns_rcqep) \
204 (le32_to_cpu((ns_rcqep)->word_1))
205 #define ns_rcqe_nextbufhandle(ns_rcqep) \
206 (le32_to_cpu((ns_rcqep)->word_2))
207
208
209
210 /* SCQ - Segmentation Channel Queue
211 *
212 * Written by the device driver, read by the NICStAR.
213 */
214
215 typedef struct ns_scqe
216 {
217 u32 word_1;
218 u32 word_2;
219 u32 word_3;
220 u32 word_4;
221 } ns_scqe;
222
223 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
224 or TSR (Transmit Status Requests) */
225
226 #define NS_SCQE_TYPE_TBD 0x00000000
227 #define NS_SCQE_TYPE_TSR 0x80000000
228
229
230 #define NS_TBD_EOPDU 0x40000000
231 #define NS_TBD_AAL0 0x00000000
232 #define NS_TBD_AAL34 0x04000000
233 #define NS_TBD_AAL5 0x08000000
234
235 #define NS_TBD_VPI_MASK 0x0FF00000
236 #define NS_TBD_VCI_MASK 0x000FFFF0
237 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
238
239 #define NS_TBD_VPI_SHIFT 20
240 #define NS_TBD_VCI_SHIFT 4
241
242 #define ns_tbd_mkword_1(flags, m, n, buflen) \
243 (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
244 #define ns_tbd_mkword_1_novbr(flags, buflen) \
245 (cpu_to_le32((flags) | (buflen) | 0x00810000))
246 #define ns_tbd_mkword_3(control, pdulen) \
247 (cpu_to_le32((control) << 16 | (pdulen)))
248 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
249 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
250
251
252 #define NS_TSR_INTENABLE 0x20000000
253
254 #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
255
256 #define ns_tsr_mkword_1(flags) \
257 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
258 #define ns_tsr_mkword_2(scdi, scqi) \
259 (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
260
261 #define ns_scqe_is_tsr(ns_scqep) \
262 (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
263
264 #define VBR_SCQ_NUM_ENTRIES 512
265 #define VBR_SCQSIZE 8192
266 #define CBR_SCQ_NUM_ENTRIES 64
267 #define CBR_SCQSIZE 1024
268
269 #define NS_SCQE_SIZE 16
270
271
272
273 /* TSQ - Transmit Status Queue
274 *
275 * Written by the NICStAR, read by the device driver.
276 */
277
278 typedef struct ns_tsi
279 {
280 u32 word_1;
281 u32 word_2;
282 } ns_tsi;
283
284 /* NOTE: The first word can be a status word copied from the TSR which
285 originated the TSI, or a timer overflow indicator. In this last
286 case, the value of the first word is all zeroes. */
287
288 #define NS_TSI_EMPTY 0x80000000
289 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
290
291 #define ns_tsi_isempty(ns_tsip) \
292 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
293 #define ns_tsi_gettimestamp(ns_tsip) \
294 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
295
296 #define ns_tsi_init(ns_tsip) \
297 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
298
299
300 #define NS_TSQSIZE 8192
301 #define NS_TSQ_NUM_ENTRIES 1024
302 #define NS_TSQ_ALIGNMENT 8192
303
304
305 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
306
307 #define ns_tsi_tmrof(ns_tsip) \
308 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
309 #define ns_tsi_getscdindex(ns_tsip) \
310 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
311 #define ns_tsi_getscqpos(ns_tsip) \
312 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
313
314
315
316 /* NICStAR structures located in local SRAM ***********************************/
317
318
319
320 /* RCT - Receive Connection Table
321 *
322 * Written by both the NICStAR and the device driver.
323 */
324
325 typedef struct ns_rcte
326 {
327 u32 word_1;
328 u32 buffer_handle;
329 u32 dma_address;
330 u32 aal5_crc32;
331 } ns_rcte;
332
333 #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
334 #define NS_RCTE_NZGFC 0x00100000
335 #define NS_RCTE_CONNECTOPEN 0x00080000
336 #define NS_RCTE_AALMASK 0x00070000
337 #define NS_RCTE_AAL0 0x00000000
338 #define NS_RCTE_AAL34 0x00010000
339 #define NS_RCTE_AAL5 0x00020000
340 #define NS_RCTE_RCQ 0x00030000
341 #define NS_RCTE_RAWCELLINTEN 0x00008000
342 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
343 #define NS_RCTE_BUFFVALID 0x00002000
344 #define NS_RCTE_FBDSIZE 0x00001000
345 #define NS_RCTE_EFCI 0x00000800
346 #define NS_RCTE_CLP 0x00000400
347 #define NS_RCTE_CRCERROR 0x00000200
348 #define NS_RCTE_CELLCOUNT_MASK 0x000001FF
349
350 #define NS_RCTE_FBDSIZE_SM 0x00000000
351 #define NS_RCTE_FBDSIZE_LG 0x00001000
352
353 #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
354
355 /* NOTE: We could make macros to contruct the first word of the RCTE,
356 but that doesn't seem to make much sense... */
357
358
359
360 /* FBD - Free Buffer Descriptor
361 *
362 * Written by the device driver using via the command register.
363 */
364
365 typedef struct ns_fbd
366 {
367 u32 buffer_handle;
368 u32 dma_address;
369 } ns_fbd;
370
371
372
373
374 /* TST - Transmit Schedule Table
375 *
376 * Written by the device driver.
377 */
378
379 typedef u32 ns_tste;
380
381 #define NS_TST_OPCODE_MASK 0x60000000
382
383 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
384 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
385 #define NS_TST_OPCODE_VARIABLE 0x40000000
386 #define NS_TST_OPCODE_END 0x60000000 /* Jump */
387
388 #define ns_tste_make(opcode, sramad) (opcode | sramad)
389
390 /* NOTE:
391
392 - When the opcode is FIXED, sramad specifies the SRAM address of the
393 SCD for that fixed rate channel.
394 - When the opcode is END, sramad specifies the SRAM address of the
395 location of the next TST entry to read.
396 */
397
398
399
400 /* SCD - Segmentation Channel Descriptor
401 *
402 * Written by both the device driver and the NICStAR
403 */
404
405 typedef struct ns_scd
406 {
407 u32 word_1;
408 u32 word_2;
409 u32 partial_aal5_crc;
410 u32 reserved;
411 ns_scqe cache_a;
412 ns_scqe cache_b;
413 } ns_scd;
414
415 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
416 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
417 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
418 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
419 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
420 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
421 #define NS_SCD_XMITFOREVER 0x02000000
422
423 /* NOTE: There are other fields in word 2 of the SCD, but as they should
424 not be needed in the device driver they are not defined here. */
425
426
427
428
429 /* NICStAR local SRAM memory map **********************************************/
430
431
432 #define NS_RCT 0x00000
433 #define NS_RCT_32_END 0x03FFF
434 #define NS_RCT_128_END 0x0FFFF
435 #define NS_UNUSED_32 0x04000
436 #define NS_UNUSED_128 0x10000
437 #define NS_UNUSED_END 0x1BFFF
438 #define NS_TST_FRSCD 0x1C000
439 #define NS_TST_FRSCD_END 0x1E7DB
440 #define NS_VRSCD2 0x1E7DC
441 #define NS_VRSCD2_END 0x1E7E7
442 #define NS_VRSCD1 0x1E7E8
443 #define NS_VRSCD1_END 0x1E7F3
444 #define NS_VRSCD0 0x1E7F4
445 #define NS_VRSCD0_END 0x1E7FF
446 #define NS_RXFIFO 0x1E800
447 #define NS_RXFIFO_END 0x1F7FF
448 #define NS_SMFBQ 0x1F800
449 #define NS_SMFBQ_END 0x1FBFF
450 #define NS_LGFBQ 0x1FC00
451 #define NS_LGFBQ_END 0x1FFFF
452
453
454
455 /* NISCtAR operation registers ************************************************/
456
457
458 /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
459
460 enum ns_regs
461 {
462 DR0 = 0x00, /* Data Register 0 R/W*/
463 DR1 = 0x04, /* Data Register 1 W */
464 DR2 = 0x08, /* Data Register 2 W */
465 DR3 = 0x0C, /* Data Register 3 W */
466 CMD = 0x10, /* Command W */
467 CFG = 0x14, /* Configuration R/W */
468 STAT = 0x18, /* Status R/W */
469 RSQB = 0x1C, /* Receive Status Queue Base W */
470 RSQT = 0x20, /* Receive Status Queue Tail R */
471 RSQH = 0x24, /* Receive Status Queue Head W */
472 CDC = 0x28, /* Cell Drop Counter R/clear */
473 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
474 ICC = 0x30, /* Invalid Cell Count R/clear */
475 RAWCT = 0x34, /* Raw Cell Tail R */
476 TMR = 0x38, /* Timer R */
477 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
478 TSQB = 0x40, /* Transmit Status Queue Base W */
479 TSQT = 0x44, /* Transmit Status Queue Tail R */
480 TSQH = 0x48, /* Transmit Status Queue Head W */
481 GP = 0x4C, /* General Purpose R/W */
482 VPM = 0x50 /* VPI/VCI Mask W */
483 };
484
485
486 /* NICStAR commands issued to the CMD register ********************************/
487
488
489 /* Top 4 bits are command opcode, lower 28 are parameters. */
490
491 #define NS_CMD_NO_OPERATION 0x00000000
492 /* params always 0 */
493
494 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
495 /* b19{1=open,0=close} b18-2{SRAM addr} */
496
497 #define NS_CMD_WRITE_SRAM 0x40000000
498 /* b18-2{SRAM addr} b1-0{burst size} */
499
500 #define NS_CMD_READ_SRAM 0x50000000
501 /* b18-2{SRAM addr} */
502
503 #define NS_CMD_WRITE_FREEBUFQ 0x60000000
504 /* b0{large buf indicator} */
505
506 #define NS_CMD_READ_UTILITY 0x80000000
507 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
508
509 #define NS_CMD_WRITE_UTILITY 0x90000000
510 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
511
512 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
513 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
514
515
516 /* NICStAR configuration bits *************************************************/
517
518 #define NS_CFG_SWRST 0x80000000 /* Software Reset */
519 #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
520 #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
521 #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
522 #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
523 Interrupt Enable */
524 #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
525 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
526 #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
527 #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
528 #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
529 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
530 #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
531 Handling */
532 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
533 #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
534 Interrupt Enable */
535 #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
536 #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
537 Enable */
538 #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
539 #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
540 Enable */
541 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
542 Enable */
543 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
544 #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
545 Interrupt Enable */
546 #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
547
548 #define NS_CFG_SMBUFSIZE_48 0x00000000
549 #define NS_CFG_SMBUFSIZE_96 0x08000000
550 #define NS_CFG_SMBUFSIZE_240 0x10000000
551 #define NS_CFG_SMBUFSIZE_2048 0x18000000
552
553 #define NS_CFG_LGBUFSIZE_2048 0x00000000
554 #define NS_CFG_LGBUFSIZE_4096 0x02000000
555 #define NS_CFG_LGBUFSIZE_8192 0x04000000
556 #define NS_CFG_LGBUFSIZE_16384 0x06000000
557
558 #define NS_CFG_RSQSIZE_2048 0x00000000
559 #define NS_CFG_RSQSIZE_4096 0x00400000
560 #define NS_CFG_RSQSIZE_8192 0x00800000
561
562 #define NS_CFG_VPIBITS_0 0x00000000
563 #define NS_CFG_VPIBITS_1 0x00040000
564 #define NS_CFG_VPIBITS_2 0x00080000
565 #define NS_CFG_VPIBITS_8 0x000C0000
566
567 #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
568 #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
569 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
570
571 #define NS_CFG_RXINT_NOINT 0x00000000
572 #define NS_CFG_RXINT_NODELAY 0x00001000
573 #define NS_CFG_RXINT_314US 0x00002000
574 #define NS_CFG_RXINT_624US 0x00003000
575 #define NS_CFG_RXINT_899US 0x00004000
576
577
578 /* NICStAR STATus bits ********************************************************/
579
580 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
581 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
582 #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
583 #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
584 #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
585 #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
586 #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
587 #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
588 #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
589 #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
590 #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
591 #define NS_STAT_EOPDU 0x00000020 /* End of PDU */
592 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
593 #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
594 #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
595 #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
596
597 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
598 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
599
600
601
602 /* #defines which depend on other #defines ************************************/
603
604
605 #define NS_TST0 NS_TST_FRSCD
606 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
607
608 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
609 #define NS_FRSCD_SIZE 12 /* 12 dwords */
610 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
611
612 #if (NS_SMBUFSIZE == 48)
613 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
614 #elif (NS_SMBUFSIZE == 96)
615 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
616 #elif (NS_SMBUFSIZE == 240)
617 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
618 #elif (NS_SMBUFSIZE == 2048)
619 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
620 #else
621 #error NS_SMBUFSIZE is incorrect in nicstar.h
622 #endif /* NS_SMBUFSIZE */
623
624 #if (NS_LGBUFSIZE == 2048)
625 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
626 #elif (NS_LGBUFSIZE == 4096)
627 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
628 #eliif (NS_LGBUFSIZE == 8192)
629 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
630 #elif (NS_LGBUFSIZE == 16384)
631 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
632 #else
633 #error NS_LGBUFSIZE is incorrect in nicstar.h
634 #endif /* NS_LGBUFSIZE */
635
636 #if (NS_RSQSIZE == 2048)
637 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
638 #elif (NS_RSQSIZE == 4096)
639 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
640 #elif (NS_RSQSIZE == 8192)
641 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
642 #else
643 #error NS_RSQSIZE is incorrect in nicstar.h
644 #endif /* NS_RSQSIZE */
645
646 #if (NS_VPIBITS == 0)
647 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
648 #elif (NS_VPIBITS == 1)
649 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
650 #elif (NS_VPIBITS == 2)
651 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
652 #elif (NS_VPIBITS == 8)
653 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
654 #else
655 #error NS_VPIBITS is incorrect in nicstar.h
656 #endif /* NS_VPIBITS */
657
658 #ifdef RCQ_SUPPORT
659 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
660 #else
661 #define NS_CFG_RAWIE_OPT 0x00000000
662 #endif /* RCQ_SUPPORT */
663
664 #ifdef ENABLE_TSQFIE
665 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
666 #else
667 #define NS_CFG_TSQFIE_OPT 0x00000000
668 #endif /* ENABLE_TSQFIE */
669
670
671 /* PCI stuff ******************************************************************/
672
673 #ifndef PCI_VENDOR_ID_IDT
674 #define PCI_VENDOR_ID_IDT 0x111D
675 #endif /* PCI_VENDOR_ID_IDT */
676
677 #ifndef PCI_DEVICE_ID_IDT_IDT77201
678 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
679 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
680
681
682
683 /* Device driver structures ***************************************************/
684
685
686 typedef struct tsq_info
687 {
688 void *org;
689 ns_tsi *base;
690 ns_tsi *next;
691 ns_tsi *last;
692 } tsq_info;
693
694
695 typedef struct scq_info
696 {
697 void *org;
698 ns_scqe *base;
699 ns_scqe *last;
700 ns_scqe *next;
701 volatile ns_scqe *tail; /* Not related to the nicstar register */
702 unsigned num_entries;
703 struct sk_buff **skb; /* Pointer to an array of pointers
704 to the sk_buffs used for tx */
705 u32 scd; /* SRAM address of the corresponding
706 SCD */
707 int tbd_count; /* Only meaningful on variable rate */
708 wait_queue_head_t scqfull_waitq;
709 volatile char full; /* SCQ full indicator */
710 spinlock_t lock; /* SCQ spinlock */
711 #ifdef NS_DEBUG_SPINLOCKS
712 volatile long has_lock;
713 volatile int cpu_lock;
714 #endif /* NS_DEBUG_SPINLOCKS */
715 } scq_info;
716
717
718
719 typedef struct rsq_info
720 {
721 void *org;
722 ns_rsqe *base;
723 ns_rsqe *next;
724 ns_rsqe *last;
725 } rsq_info;
726
727
728 typedef struct skb_pool
729 {
730 volatile int count; /* number of buffers in the queue */
731 struct sk_buff_head queue;
732 } skb_pool;
733
734 /* NOTE: for small and large buffer pools, the count is not used, as the
735 actual value used for buffer management is the one read from the
736 card. */
737
738
739 typedef struct vc_map
740 {
741 volatile int tx:1; /* TX vc? */
742 volatile int rx:1; /* RX vc? */
743 struct atm_vcc *tx_vcc, *rx_vcc;
744 struct sk_buff *rx_iov; /* RX iovector skb */
745 scq_info *scq; /* To keep track of the SCQ */
746 u32 cbr_scd; /* SRAM address of the corresponding
747 SCD. 0x00000000 for UBR/VBR/ABR */
748 int tbd_count;
749 } vc_map;
750
751
752 typedef struct ns_dev
753 {
754 int index; /* Card ID to the device driver */
755 int sram_size; /* In k x 32bit words. 32 or 128 */
756 unsigned long membase; /* Card's memory base address */
757 unsigned long max_pcr;
758 int rct_size; /* Number of entries */
759 int vpibits;
760 int vcibits;
761 struct pci_dev *pcidev;
762 struct atm_dev *atmdev;
763 tsq_info tsq;
764 rsq_info rsq;
765 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
766 skb_pool sbpool; /* Small buffers */
767 skb_pool lbpool; /* Large buffers */
768 skb_pool hbpool; /* Pre-allocated huge buffers */
769 skb_pool iovpool; /* iovector buffers */
770 volatile int efbie; /* Empty free buf. queue int. enabled */
771 volatile u32 tst_addr; /* SRAM address of the TST in use */
772 volatile int tst_free_entries;
773 vc_map vcmap[NS_MAX_RCTSIZE];
774 vc_map *tste2vc[NS_TST_NUM_ENTRIES];
775 vc_map *scd2vc[NS_FRSCD_NUM];
776 buf_nr sbnr;
777 buf_nr lbnr;
778 buf_nr hbnr;
779 buf_nr iovnr;
780 int sbfqc;
781 int lbfqc;
782 u32 sm_handle;
783 u32 sm_addr;
784 u32 lg_handle;
785 u32 lg_addr;
786 struct sk_buff *rcbuf; /* Current raw cell buffer */
787 u32 rawch; /* Raw cell queue head */
788 unsigned intcnt; /* Interrupt counter */
789 spinlock_t int_lock; /* Interrupt lock */
790 spinlock_t res_lock; /* Card resource lock */
791 #ifdef NS_DEBUG_SPINLOCKS
792 volatile long has_int_lock;
793 volatile int cpu_int;
794 volatile long has_res_lock;
795 volatile int cpu_res;
796 #endif /* NS_DEBUG_SPINLOCKS */
797 } ns_dev;
798
799
800 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
801 CBR vc. If the entry is not allocated, it must be NULL.
802
803 There are two TSTs so the driver can modify them on the fly
804 without stopping the transmission.
805
806 scd2vc allows us to find out unused fixed rate SCDs, because
807 they must have a NULL pointer here. */
808
809
810 #endif /* _LINUX_NICSTAR_H_ */
811