File: /usr/src/linux/drivers/atm/nicstar.c
1 /******************************************************************************
2 *
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 *
20 *
21 ******************************************************************************/
22
23
24 /**** IMPORTANT INFORMATION ***************************************************
25 *
26 * There are currently three types of spinlocks:
27 *
28 * 1 - Per card interrupt spinlock (to protect structures and such)
29 * 2 - Per SCQ scq spinlock
30 * 3 - Per card resource spinlock (to access registers, etc.)
31 *
32 * These must NEVER be grabbed in reverse order.
33 *
34 ******************************************************************************/
35
36 /* Header files ***************************************************************/
37
38 #include <linux/module.h>
39 #include <linux/config.h>
40 #include <linux/kernel.h>
41 #include <linux/skbuff.h>
42 #include <linux/atmdev.h>
43 #include <linux/atm.h>
44 #include <linux/pci.h>
45 #include <linux/types.h>
46 #include <linux/string.h>
47 #include <linux/delay.h>
48 #include <linux/init.h>
49 #include <linux/sched.h>
50 #include <linux/timer.h>
51 #include <linux/interrupt.h>
52 #include <linux/bitops.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/atomic.h>
56 #include "nicstar.h"
57 #include "nicstarmac.h"
58 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59 #include "suni.h"
60 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62 #include "idt77105.h"
63 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65 #if BITS_PER_LONG != 32
66 # error FIXME: this driver requires a 32-bit platform
67 #endif
68
69 /* Additional code ************************************************************/
70
71 #include "nicstarmac.c"
72
73
74 /* Configurable parameters ****************************************************/
75
76 #undef PHY_LOOPBACK
77 #undef TX_DEBUG
78 #undef RX_DEBUG
79 #undef GENERAL_DEBUG
80 #undef EXTRA_DEBUG
81
82 #undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
83 you're going to use only raw ATM */
84
85
86 /* Do not touch these *********************************************************/
87
88 #ifdef TX_DEBUG
89 #define TXPRINTK(args...) printk(args)
90 #else
91 #define TXPRINTK(args...)
92 #endif /* TX_DEBUG */
93
94 #ifdef RX_DEBUG
95 #define RXPRINTK(args...) printk(args)
96 #else
97 #define RXPRINTK(args...)
98 #endif /* RX_DEBUG */
99
100 #ifdef GENERAL_DEBUG
101 #define PRINTK(args...) printk(args)
102 #else
103 #define PRINTK(args...)
104 #endif /* GENERAL_DEBUG */
105
106 #ifdef EXTRA_DEBUG
107 #define XPRINTK(args...) printk(args)
108 #else
109 #define XPRINTK(args...)
110 #endif /* EXTRA_DEBUG */
111
112
113 /* Macros *********************************************************************/
114
115 #define MAX(a,b) ((a) > (b) ? (a) : (b))
116 #define MIN(a,b) ((a) < (b) ? (a) : (b))
117
118 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
119
120 #define NS_DELAY mdelay(1)
121
122 #define ALIGN_BUS_ADDR(addr, alignment) \
123 ((((u32) (addr)) + (((u32) (alignment)) - 1)) & ~(((u32) (alignment)) - 1))
124 #define ALIGN_ADDRESS(addr, alignment) \
125 bus_to_virt(ALIGN_BUS_ADDR(virt_to_bus(addr), alignment))
126
127 #undef CEIL
128
129 #ifndef ATM_SKB
130 #define ATM_SKB(s) (&(s)->atm)
131 #endif
132
133 /* Spinlock debugging stuff */
134 #ifdef NS_DEBUG_SPINLOCKS /* See nicstar.h */
135 #define ns_grab_int_lock(card,flags) \
136 do { \
137 unsigned long nsdsf, nsdsf2; \
138 local_irq_save(flags); \
139 save_flags(nsdsf); cli();\
140 if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
141 (flags)&(1<<9)?"en":"dis"); \
142 if (spin_is_locked(&(card)->int_lock) && \
143 (card)->cpu_int == smp_processor_id()) { \
144 printk("nicstar.c: line %d (cpu %d) int_lock already locked at line %d (cpu %d)\n", \
145 __LINE__, smp_processor_id(), (card)->has_int_lock, \
146 (card)->cpu_int); \
147 printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
148 } \
149 if (spin_is_locked(&(card)->res_lock) && \
150 (card)->cpu_res == smp_processor_id()) { \
151 printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying int)\n", \
152 __LINE__, smp_processor_id(), (card)->has_res_lock, \
153 (card)->cpu_res); \
154 printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
155 } \
156 spin_lock_irq(&(card)->int_lock); \
157 (card)->has_int_lock = __LINE__; \
158 (card)->cpu_int = smp_processor_id(); \
159 restore_flags(nsdsf); } while (0)
160 #define ns_grab_res_lock(card,flags) \
161 do { \
162 unsigned long nsdsf, nsdsf2; \
163 local_irq_save(flags); \
164 save_flags(nsdsf); cli();\
165 if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
166 (flags)&(1<<9)?"en":"dis"); \
167 if (spin_is_locked(&(card)->res_lock) && \
168 (card)->cpu_res == smp_processor_id()) { \
169 printk("nicstar.c: line %d (cpu %d) res_lock already locked at line %d (cpu %d)\n", \
170 __LINE__, smp_processor_id(), (card)->has_res_lock, \
171 (card)->cpu_res); \
172 printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
173 } \
174 spin_lock_irq(&(card)->res_lock); \
175 (card)->has_res_lock = __LINE__; \
176 (card)->cpu_res = smp_processor_id(); \
177 restore_flags(nsdsf); } while (0)
178 #define ns_grab_scq_lock(card,scq,flags) \
179 do { \
180 unsigned long nsdsf, nsdsf2; \
181 local_irq_save(flags); \
182 save_flags(nsdsf); cli();\
183 if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
184 (flags)&(1<<9)?"en":"dis"); \
185 if (spin_is_locked(&(scq)->lock) && \
186 (scq)->cpu_lock == smp_processor_id()) { \
187 printk("nicstar.c: line %d (cpu %d) this scq_lock already locked at line %d (cpu %d)\n", \
188 __LINE__, smp_processor_id(), (scq)->has_lock, \
189 (scq)->cpu_lock); \
190 printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
191 } \
192 if (spin_is_locked(&(card)->res_lock) && \
193 (card)->cpu_res == smp_processor_id()) { \
194 printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying scq)\n", \
195 __LINE__, smp_processor_id(), (card)->has_res_lock, \
196 (card)->cpu_res); \
197 printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
198 } \
199 spin_lock_irq(&(scq)->lock); \
200 (scq)->has_lock = __LINE__; \
201 (scq)->cpu_lock = smp_processor_id(); \
202 restore_flags(nsdsf); } while (0)
203 #else /* !NS_DEBUG_SPINLOCKS */
204 #define ns_grab_int_lock(card,flags) \
205 spin_lock_irqsave(&(card)->int_lock,(flags))
206 #define ns_grab_res_lock(card,flags) \
207 spin_lock_irqsave(&(card)->res_lock,(flags))
208 #define ns_grab_scq_lock(card,scq,flags) \
209 spin_lock_irqsave(&(scq)->lock,flags)
210 #endif /* NS_DEBUG_SPINLOCKS */
211
212
213 /* Function declarations ******************************************************/
214
215 static u32 ns_read_sram(ns_dev *card, u32 sram_address);
216 static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count);
217 static int __init ns_init_card(int i, struct pci_dev *pcidev);
218 static void __init ns_init_card_error(ns_dev *card, int error);
219 static scq_info *get_scq(int size, u32 scd);
220 static void free_scq(scq_info *scq, struct atm_vcc *vcc);
221 static void push_rxbufs(ns_dev *card, u32 type, u32 handle1, u32 addr1,
222 u32 handle2, u32 addr2);
223 static void ns_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
224 static int ns_open(struct atm_vcc *vcc, short vpi, int vci);
225 static void ns_close(struct atm_vcc *vcc);
226 static void fill_tst(ns_dev *card, int n, vc_map *vc);
227 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
228 static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd,
229 struct sk_buff *skb);
230 static void process_tsq(ns_dev *card);
231 static void drain_scq(ns_dev *card, scq_info *scq, int pos);
232 static void process_rsq(ns_dev *card);
233 static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe);
234 #ifdef NS_USE_DESTRUCTORS
235 static void ns_sb_destructor(struct sk_buff *sb);
236 static void ns_lb_destructor(struct sk_buff *lb);
237 static void ns_hb_destructor(struct sk_buff *hb);
238 #endif /* NS_USE_DESTRUCTORS */
239 static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb);
240 static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count);
241 static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb);
242 static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb);
243 static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb);
244 static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page);
245 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg);
246 static void which_list(ns_dev *card, struct sk_buff *skb);
247 static void ns_poll(unsigned long arg);
248 static int ns_parse_mac(char *mac, unsigned char *esi);
249 static short ns_h2i(char c);
250 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
251 unsigned long addr);
252 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
253
254
255
256 /* Global variables ***********************************************************/
257
258 static struct ns_dev *cards[NS_MAX_CARDS];
259 static unsigned num_cards;
260 static struct atmdev_ops atm_ops =
261 {
262 open: ns_open,
263 close: ns_close,
264 ioctl: ns_ioctl,
265 send: ns_send,
266 phy_put: ns_phy_put,
267 phy_get: ns_phy_get,
268 proc_read: ns_proc_read,
269 owner: THIS_MODULE,
270 };
271 static struct timer_list ns_timer;
272 static char *mac[NS_MAX_CARDS];
273 MODULE_PARM(mac, "1-" __MODULE_STRING(NS_MAX_CARDS) "s");
274 MODULE_LICENSE("GPL");
275
276
277 /* Functions*******************************************************************/
278
279 #ifdef MODULE
280
281 int __init init_module(void)
282 {
283 int i;
284 unsigned error = 0; /* Initialized to remove compile warning */
285 struct pci_dev *pcidev;
286
287 XPRINTK("nicstar: init_module() called.\n");
288 if(!pci_present())
289 {
290 printk("nicstar: no PCI subsystem found.\n");
291 return -EIO;
292 }
293
294 for(i = 0; i < NS_MAX_CARDS; i++)
295 cards[i] = NULL;
296
297 pcidev = NULL;
298 for(i = 0; i < NS_MAX_CARDS; i++)
299 {
300 if ((pcidev = pci_find_device(PCI_VENDOR_ID_IDT,
301 PCI_DEVICE_ID_IDT_IDT77201,
302 pcidev)) == NULL)
303 break;
304
305 error = ns_init_card(i, pcidev);
306 if (error)
307 cards[i--] = NULL; /* Try to find another card but don't increment index */
308 }
309
310 if (i == 0)
311 {
312 if (!error)
313 {
314 printk("nicstar: no cards found.\n");
315 return -ENXIO;
316 }
317 else
318 return -EIO;
319 }
320 TXPRINTK("nicstar: TX debug enabled.\n");
321 RXPRINTK("nicstar: RX debug enabled.\n");
322 PRINTK("nicstar: General debug enabled.\n");
323 #ifdef PHY_LOOPBACK
324 printk("nicstar: using PHY loopback.\n");
325 #endif /* PHY_LOOPBACK */
326 XPRINTK("nicstar: init_module() returned.\n");
327
328 init_timer(&ns_timer);
329 ns_timer.expires = jiffies + NS_POLL_PERIOD;
330 ns_timer.data = 0UL;
331 ns_timer.function = ns_poll;
332 add_timer(&ns_timer);
333 return 0;
334 }
335
336
337
338 void cleanup_module(void)
339 {
340 int i, j;
341 unsigned short pci_command;
342 ns_dev *card;
343 struct sk_buff *hb;
344 struct sk_buff *iovb;
345 struct sk_buff *lb;
346 struct sk_buff *sb;
347
348 XPRINTK("nicstar: cleanup_module() called.\n");
349
350 if (MOD_IN_USE)
351 printk("nicstar: module in use, remove delayed.\n");
352
353 del_timer(&ns_timer);
354
355 for (i = 0; i < NS_MAX_CARDS; i++)
356 {
357 if (cards[i] == NULL)
358 continue;
359
360 card = cards[i];
361
362 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
363 if (card->max_pcr == ATM_25_PCR) {
364 idt77105_stop(card->atmdev);
365 }
366 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
367
368 /* Stop everything */
369 writel(0x00000000, card->membase + CFG);
370
371 /* De-register device */
372 atm_dev_deregister(card->atmdev);
373
374 /* Disable memory mapping and busmastering */
375 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command) != 0)
376 {
377 printk("nicstar%d: can't read PCI_COMMAND.\n", i);
378 }
379 pci_command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
380 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command) != 0)
381 {
382 printk("nicstar%d: can't write PCI_COMMAND.\n", i);
383 }
384
385 /* Free up resources */
386 j = 0;
387 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
388 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
389 {
390 dev_kfree_skb_any(hb);
391 j++;
392 }
393 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
394 j = 0;
395 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, card->iovpool.count);
396 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
397 {
398 dev_kfree_skb_any(iovb);
399 j++;
400 }
401 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
402 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
403 dev_kfree_skb_any(lb);
404 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
405 dev_kfree_skb_any(sb);
406 free_scq(card->scq0, NULL);
407 for (j = 0; j < NS_FRSCD_NUM; j++)
408 {
409 if (card->scd2vc[j] != NULL)
410 free_scq(card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
411 }
412 kfree(card->rsq.org);
413 kfree(card->tsq.org);
414 free_irq(card->pcidev->irq, card);
415 iounmap((void *) card->membase);
416 kfree(card);
417
418 }
419 XPRINTK("nicstar: cleanup_module() returned.\n");
420 }
421
422
423 #else
424
425 int __init nicstar_detect(void)
426 {
427 int i;
428 unsigned error = 0; /* Initialized to remove compile warning */
429 struct pci_dev *pcidev;
430
431 if(!pci_present())
432 {
433 printk("nicstar: no PCI subsystem found.\n");
434 return -EIO;
435 }
436
437 for(i = 0; i < NS_MAX_CARDS; i++)
438 cards[i] = NULL;
439
440 pcidev = NULL;
441 for(i = 0; i < NS_MAX_CARDS; i++)
442 {
443 if ((pcidev = pci_find_device(PCI_VENDOR_ID_IDT,
444 PCI_DEVICE_ID_IDT_IDT77201,
445 pcidev)) == NULL)
446 break;
447
448 error = ns_init_card(i, pcidev);
449 if (error)
450 cards[i--] = NULL; /* Try to find another card but don't increment index */
451 }
452
453 if (i == 0 && error)
454 return -EIO;
455
456 TXPRINTK("nicstar: TX debug enabled.\n");
457 RXPRINTK("nicstar: RX debug enabled.\n");
458 PRINTK("nicstar: General debug enabled.\n");
459 #ifdef PHY_LOOPBACK
460 printk("nicstar: using PHY loopback.\n");
461 #endif /* PHY_LOOPBACK */
462 XPRINTK("nicstar: init_module() returned.\n");
463
464 init_timer(&ns_timer);
465 ns_timer.expires = jiffies + NS_POLL_PERIOD;
466 ns_timer.data = 0UL;
467 ns_timer.function = ns_poll;
468 add_timer(&ns_timer);
469 return i;
470 }
471
472
473 #endif /* MODULE */
474
475
476 static u32 ns_read_sram(ns_dev *card, u32 sram_address)
477 {
478 unsigned long flags;
479 u32 data;
480 sram_address <<= 2;
481 sram_address &= 0x0007FFFC; /* address must be dword aligned */
482 sram_address |= 0x50000000; /* SRAM read command */
483 ns_grab_res_lock(card, flags);
484 while (CMD_BUSY(card));
485 writel(sram_address, card->membase + CMD);
486 while (CMD_BUSY(card));
487 data = readl(card->membase + DR0);
488 spin_unlock_irqrestore(&card->res_lock, flags);
489 return data;
490 }
491
492
493
494 static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count)
495 {
496 unsigned long flags;
497 int i, c;
498 count--; /* count range now is 0..3 instead of 1..4 */
499 c = count;
500 c <<= 2; /* to use increments of 4 */
501 ns_grab_res_lock(card, flags);
502 while (CMD_BUSY(card));
503 for (i = 0; i <= c; i += 4)
504 writel(*(value++), card->membase + i);
505 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
506 so card->membase + DR0 == card->membase */
507 sram_address <<= 2;
508 sram_address &= 0x0007FFFC;
509 sram_address |= (0x40000000 | count);
510 writel(sram_address, card->membase + CMD);
511 spin_unlock_irqrestore(&card->res_lock, flags);
512 }
513
514
515 static int __init ns_init_card(int i, struct pci_dev *pcidev)
516 {
517 int j;
518 struct ns_dev *card = NULL;
519 unsigned short pci_command;
520 unsigned char pci_latency;
521 unsigned error;
522 u32 data;
523 u32 u32d[4];
524 u32 ns_cfg_rctsize;
525 int bcount;
526
527 error = 0;
528
529 if (pci_enable_device(pcidev))
530 {
531 printk("nicstar%d: can't enable PCI device\n", i);
532 error = 2;
533 ns_init_card_error(card, error);
534 return error;
535 }
536
537 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL)
538 {
539 printk("nicstar%d: can't allocate memory for device structure.\n", i);
540 error = 2;
541 ns_init_card_error(card, error);
542 return error;
543 }
544 cards[i] = card;
545 spin_lock_init(&card->int_lock);
546 spin_lock_init(&card->res_lock);
547
548 card->index = i;
549 card->atmdev = NULL;
550 card->pcidev = pcidev;
551 card->membase = pci_resource_start(pcidev, 1);
552 #ifdef __powerpc__
553 /* Compensate for different memory map between host CPU and PCI bus.
554 Shouldn't we use a macro for this? */
555 card->membase += KERNELBASE;
556 #endif /* __powerpc__ */
557 card->membase = (unsigned long) ioremap(card->membase, NS_IOREMAP_SIZE);
558 if (card->membase == 0)
559 {
560 printk("nicstar%d: can't ioremap() membase.\n",i);
561 error = 3;
562 ns_init_card_error(card, error);
563 return error;
564 }
565 PRINTK("nicstar%d: membase at 0x%x.\n", i, card->membase);
566
567 if (pci_read_config_word(pcidev, PCI_COMMAND, &pci_command) != 0)
568 {
569 printk("nicstar%d: can't read PCI_COMMAND.\n", i);
570 error = 4;
571 ns_init_card_error(card, error);
572 return error;
573 }
574 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
575 if (pci_write_config_word(pcidev, PCI_COMMAND, pci_command) != 0)
576 {
577 printk("nicstar%d: can't write PCI_COMMAND.\n", i);
578 error = 5;
579 ns_init_card_error(card, error);
580 return error;
581 }
582
583 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0)
584 {
585 printk("nicstar%d: can't read PCI latency timer.\n", i);
586 error = 6;
587 ns_init_card_error(card, error);
588 return error;
589 }
590 #ifdef NS_PCI_LATENCY
591 if (pci_latency < NS_PCI_LATENCY)
592 {
593 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, NS_PCI_LATENCY);
594 for (j = 1; j < 4; j++)
595 {
596 if (pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
597 break;
598 }
599 if (j == 4)
600 {
601 printk("nicstar%d: can't set PCI latency timer to %d.\n", i, NS_PCI_LATENCY);
602 error = 7;
603 ns_init_card_error(card, error);
604 return error;
605 }
606 }
607 #endif /* NS_PCI_LATENCY */
608
609 /* Clear timer overflow */
610 data = readl(card->membase + STAT);
611 if (data & NS_STAT_TMROF)
612 writel(NS_STAT_TMROF, card->membase + STAT);
613
614 /* Software reset */
615 writel(NS_CFG_SWRST, card->membase + CFG);
616 NS_DELAY;
617 writel(0x00000000, card->membase + CFG);
618
619 /* PHY reset */
620 writel(0x00000008, card->membase + GP);
621 NS_DELAY;
622 writel(0x00000001, card->membase + GP);
623 NS_DELAY;
624 while (CMD_BUSY(card));
625 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
626 NS_DELAY;
627
628 /* Detect PHY type */
629 while (CMD_BUSY(card));
630 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
631 while (CMD_BUSY(card));
632 data = readl(card->membase + DR0);
633 switch(data) {
634 case 0x00000009:
635 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
636 card->max_pcr = ATM_25_PCR;
637 while(CMD_BUSY(card));
638 writel(0x00000008, card->membase + DR0);
639 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
640 /* Clear an eventual pending interrupt */
641 writel(NS_STAT_SFBQF, card->membase + STAT);
642 #ifdef PHY_LOOPBACK
643 while(CMD_BUSY(card));
644 writel(0x00000022, card->membase + DR0);
645 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
646 #endif /* PHY_LOOPBACK */
647 break;
648 case 0x00000030:
649 case 0x00000031:
650 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
651 card->max_pcr = ATM_OC3_PCR;
652 #ifdef PHY_LOOPBACK
653 while(CMD_BUSY(card));
654 writel(0x00000002, card->membase + DR0);
655 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
656 #endif /* PHY_LOOPBACK */
657 break;
658 default:
659 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
660 error = 8;
661 ns_init_card_error(card, error);
662 return error;
663 }
664 writel(0x00000000, card->membase + GP);
665
666 /* Determine SRAM size */
667 data = 0x76543210;
668 ns_write_sram(card, 0x1C003, &data, 1);
669 data = 0x89ABCDEF;
670 ns_write_sram(card, 0x14003, &data, 1);
671 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
672 ns_read_sram(card, 0x1C003) == 0x76543210)
673 card->sram_size = 128;
674 else
675 card->sram_size = 32;
676 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
677
678 card->rct_size = NS_MAX_RCTSIZE;
679
680 #if (NS_MAX_RCTSIZE == 4096)
681 if (card->sram_size == 128)
682 printk("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", i);
683 #elif (NS_MAX_RCTSIZE == 16384)
684 if (card->sram_size == 32)
685 {
686 printk("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", i);
687 card->rct_size = 4096;
688 }
689 #else
690 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
691 #endif
692
693 card->vpibits = NS_VPIBITS;
694 if (card->rct_size == 4096)
695 card->vcibits = 12 - NS_VPIBITS;
696 else /* card->rct_size == 16384 */
697 card->vcibits = 14 - NS_VPIBITS;
698
699 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
700 if (mac[i] == NULL)
701 nicstar_init_eprom(card->membase);
702
703 if (request_irq(pcidev->irq, &ns_irq_handler, SA_INTERRUPT | SA_SHIRQ, "nicstar", card) != 0)
704 {
705 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
706 error = 9;
707 ns_init_card_error(card, error);
708 return error;
709 }
710
711 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
712 writel(0x00000000, card->membase + VPM);
713
714 /* Initialize TSQ */
715 card->tsq.org = kmalloc(NS_TSQSIZE + NS_TSQ_ALIGNMENT, GFP_KERNEL);
716 if (card->tsq.org == NULL)
717 {
718 printk("nicstar%d: can't allocate TSQ.\n", i);
719 error = 10;
720 ns_init_card_error(card, error);
721 return error;
722 }
723 card->tsq.base = (ns_tsi *) ALIGN_ADDRESS(card->tsq.org, NS_TSQ_ALIGNMENT);
724 card->tsq.next = card->tsq.base;
725 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
726 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
727 ns_tsi_init(card->tsq.base + j);
728 writel(0x00000000, card->membase + TSQH);
729 writel((u32) virt_to_bus(card->tsq.base), card->membase + TSQB);
730 PRINTK("nicstar%d: TSQ base at 0x%x 0x%x 0x%x.\n", i, (u32) card->tsq.base,
731 (u32) virt_to_bus(card->tsq.base), readl(card->membase + TSQB));
732
733 /* Initialize RSQ */
734 card->rsq.org = kmalloc(NS_RSQSIZE + NS_RSQ_ALIGNMENT, GFP_KERNEL);
735 if (card->rsq.org == NULL)
736 {
737 printk("nicstar%d: can't allocate RSQ.\n", i);
738 error = 11;
739 ns_init_card_error(card, error);
740 return error;
741 }
742 card->rsq.base = (ns_rsqe *) ALIGN_ADDRESS(card->rsq.org, NS_RSQ_ALIGNMENT);
743 card->rsq.next = card->rsq.base;
744 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
745 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
746 ns_rsqe_init(card->rsq.base + j);
747 writel(0x00000000, card->membase + RSQH);
748 writel((u32) virt_to_bus(card->rsq.base), card->membase + RSQB);
749 PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base);
750
751 /* Initialize SCQ0, the only VBR SCQ used */
752 card->scq1 = (scq_info *) NULL;
753 card->scq2 = (scq_info *) NULL;
754 card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0);
755 if (card->scq0 == (scq_info *) NULL)
756 {
757 printk("nicstar%d: can't get SCQ0.\n", i);
758 error = 12;
759 ns_init_card_error(card, error);
760 return error;
761 }
762 u32d[0] = (u32) virt_to_bus(card->scq0->base);
763 u32d[1] = (u32) 0x00000000;
764 u32d[2] = (u32) 0xffffffff;
765 u32d[3] = (u32) 0x00000000;
766 ns_write_sram(card, NS_VRSCD0, u32d, 4);
767 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
768 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
769 card->scq0->scd = NS_VRSCD0;
770 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%x.\n", i, (u32) card->scq0->base);
771
772 /* Initialize TSTs */
773 card->tst_addr = NS_TST0;
774 card->tst_free_entries = NS_TST_NUM_ENTRIES;
775 data = NS_TST_OPCODE_VARIABLE;
776 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
777 ns_write_sram(card, NS_TST0 + j, &data, 1);
778 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
779 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
780 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
781 ns_write_sram(card, NS_TST1 + j, &data, 1);
782 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
783 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
784 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
785 card->tste2vc[j] = NULL;
786 writel(NS_TST0 << 2, card->membase + TSTB);
787
788
789 /* Initialize RCT. AAL type is set on opening the VC. */
790 #ifdef RCQ_SUPPORT
791 u32d[0] = NS_RCTE_RAWCELLINTEN;
792 #else
793 u32d[0] = 0x00000000;
794 #endif /* RCQ_SUPPORT */
795 u32d[1] = 0x00000000;
796 u32d[2] = 0x00000000;
797 u32d[3] = 0xFFFFFFFF;
798 for (j = 0; j < card->rct_size; j++)
799 ns_write_sram(card, j * 4, u32d, 4);
800
801 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
802
803 for (j = 0; j < NS_FRSCD_NUM; j++)
804 card->scd2vc[j] = NULL;
805
806 /* Initialize buffer levels */
807 card->sbnr.min = MIN_SB;
808 card->sbnr.init = NUM_SB;
809 card->sbnr.max = MAX_SB;
810 card->lbnr.min = MIN_LB;
811 card->lbnr.init = NUM_LB;
812 card->lbnr.max = MAX_LB;
813 card->iovnr.min = MIN_IOVB;
814 card->iovnr.init = NUM_IOVB;
815 card->iovnr.max = MAX_IOVB;
816 card->hbnr.min = MIN_HB;
817 card->hbnr.init = NUM_HB;
818 card->hbnr.max = MAX_HB;
819
820 card->sm_handle = 0x00000000;
821 card->sm_addr = 0x00000000;
822 card->lg_handle = 0x00000000;
823 card->lg_addr = 0x00000000;
824
825 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
826
827 /* Pre-allocate some huge buffers */
828 skb_queue_head_init(&card->hbpool.queue);
829 card->hbpool.count = 0;
830 for (j = 0; j < NUM_HB; j++)
831 {
832 struct sk_buff *hb;
833 hb = alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
834 if (hb == NULL)
835 {
836 printk("nicstar%d: can't allocate %dth of %d huge buffers.\n",
837 i, j, NUM_HB);
838 error = 13;
839 ns_init_card_error(card, error);
840 return error;
841 }
842 skb_queue_tail(&card->hbpool.queue, hb);
843 card->hbpool.count++;
844 }
845
846
847 /* Allocate large buffers */
848 skb_queue_head_init(&card->lbpool.queue);
849 card->lbpool.count = 0; /* Not used */
850 for (j = 0; j < NUM_LB; j++)
851 {
852 struct sk_buff *lb;
853 lb = alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
854 if (lb == NULL)
855 {
856 printk("nicstar%d: can't allocate %dth of %d large buffers.\n",
857 i, j, NUM_LB);
858 error = 14;
859 ns_init_card_error(card, error);
860 return error;
861 }
862 skb_queue_tail(&card->lbpool.queue, lb);
863 skb_reserve(lb, NS_SMBUFSIZE);
864 push_rxbufs(card, BUF_LG, (u32) lb, (u32) virt_to_bus(lb->data), 0, 0);
865 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
866 if (j == 1)
867 {
868 card->rcbuf = lb;
869 card->rawch = (u32) virt_to_bus(lb->data);
870 }
871 }
872 /* Test for strange behaviour which leads to crashes */
873 if ((bcount = ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min)
874 {
875 printk("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
876 i, j, bcount);
877 error = 14;
878 ns_init_card_error(card, error);
879 return error;
880 }
881
882
883 /* Allocate small buffers */
884 skb_queue_head_init(&card->sbpool.queue);
885 card->sbpool.count = 0; /* Not used */
886 for (j = 0; j < NUM_SB; j++)
887 {
888 struct sk_buff *sb;
889 sb = alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
890 if (sb == NULL)
891 {
892 printk("nicstar%d: can't allocate %dth of %d small buffers.\n",
893 i, j, NUM_SB);
894 error = 15;
895 ns_init_card_error(card, error);
896 return error;
897 }
898 skb_queue_tail(&card->sbpool.queue, sb);
899 skb_reserve(sb, NS_AAL0_HEADER);
900 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data), 0, 0);
901 }
902 /* Test for strange behaviour which leads to crashes */
903 if ((bcount = ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min)
904 {
905 printk("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
906 i, j, bcount);
907 error = 15;
908 ns_init_card_error(card, error);
909 return error;
910 }
911
912
913 /* Allocate iovec buffers */
914 skb_queue_head_init(&card->iovpool.queue);
915 card->iovpool.count = 0;
916 for (j = 0; j < NUM_IOVB; j++)
917 {
918 struct sk_buff *iovb;
919 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
920 if (iovb == NULL)
921 {
922 printk("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
923 i, j, NUM_IOVB);
924 error = 16;
925 ns_init_card_error(card, error);
926 return error;
927 }
928 skb_queue_tail(&card->iovpool.queue, iovb);
929 card->iovpool.count++;
930 }
931
932 card->intcnt = 0;
933
934 /* Configure NICStAR */
935 if (card->rct_size == 4096)
936 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
937 else /* (card->rct_size == 16384) */
938 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
939
940 card->efbie = 1;
941
942 /* Register device */
943 card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL);
944 if (card->atmdev == NULL)
945 {
946 printk("nicstar%d: can't register device.\n", i);
947 error = 17;
948 ns_init_card_error(card, error);
949 return error;
950 }
951
952 if (ns_parse_mac(mac[i], card->atmdev->esi))
953 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
954 card->atmdev->esi, 6);
955
956 printk("nicstar%d: MAC address %02X:%02X:%02X:%02X:%02X:%02X\n", i,
957 card->atmdev->esi[0], card->atmdev->esi[1], card->atmdev->esi[2],
958 card->atmdev->esi[3], card->atmdev->esi[4], card->atmdev->esi[5]);
959
960 card->atmdev->dev_data = card;
961 card->atmdev->ci_range.vpi_bits = card->vpibits;
962 card->atmdev->ci_range.vci_bits = card->vcibits;
963 card->atmdev->link_rate = card->max_pcr;
964 card->atmdev->phy = NULL;
965
966 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
967 if (card->max_pcr == ATM_OC3_PCR) {
968 suni_init(card->atmdev);
969
970 MOD_INC_USE_COUNT;
971 /* Can't remove the nicstar driver or the suni driver would oops */
972 }
973 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
974
975 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
976 if (card->max_pcr == ATM_25_PCR) {
977 idt77105_init(card->atmdev);
978 /* Note that for the IDT77105 PHY we don't need the awful
979 * module count hack that the SUNI needs because we can
980 * stop the '105 when the nicstar module is cleaned up.
981 */
982 }
983 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
984
985 if (card->atmdev->phy && card->atmdev->phy->start)
986 card->atmdev->phy->start(card->atmdev);
987
988 writel(NS_CFG_RXPATH |
989 NS_CFG_SMBUFSIZE |
990 NS_CFG_LGBUFSIZE |
991 NS_CFG_EFBIE |
992 NS_CFG_RSQSIZE |
993 NS_CFG_VPIBITS |
994 ns_cfg_rctsize |
995 NS_CFG_RXINT_NODELAY |
996 NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
997 NS_CFG_RSQAFIE |
998 NS_CFG_TXEN |
999 NS_CFG_TXIE |
1000 NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
1001 NS_CFG_PHYIE,
1002 card->membase + CFG);
1003
1004 num_cards++;
1005
1006 return error;
1007 }
1008
1009
1010
1011 static void __init ns_init_card_error(ns_dev *card, int error)
1012 {
1013 if (error >= 17)
1014 {
1015 writel(0x00000000, card->membase + CFG);
1016 }
1017 if (error >= 16)
1018 {
1019 struct sk_buff *iovb;
1020 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
1021 dev_kfree_skb_any(iovb);
1022 }
1023 if (error >= 15)
1024 {
1025 struct sk_buff *sb;
1026 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
1027 dev_kfree_skb_any(sb);
1028 free_scq(card->scq0, NULL);
1029 }
1030 if (error >= 14)
1031 {
1032 struct sk_buff *lb;
1033 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
1034 dev_kfree_skb_any(lb);
1035 }
1036 if (error >= 13)
1037 {
1038 struct sk_buff *hb;
1039 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
1040 dev_kfree_skb_any(hb);
1041 }
1042 if (error >= 12)
1043 {
1044 kfree(card->rsq.org);
1045 }
1046 if (error >= 11)
1047 {
1048 kfree(card->tsq.org);
1049 }
1050 if (error >= 10)
1051 {
1052 free_irq(card->pcidev->irq, card);
1053 }
1054 if (error >= 4)
1055 {
1056 iounmap((void *) card->membase);
1057 }
1058 if (error >= 3)
1059 {
1060 kfree(card);
1061 }
1062 }
1063
1064
1065
1066 static scq_info *get_scq(int size, u32 scd)
1067 {
1068 scq_info *scq;
1069 int i;
1070
1071 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
1072 return (scq_info *) NULL;
1073
1074 scq = (scq_info *) kmalloc(sizeof(scq_info), GFP_KERNEL);
1075 if (scq == (scq_info *) NULL)
1076 return (scq_info *) NULL;
1077 scq->org = kmalloc(2 * size, GFP_KERNEL);
1078 if (scq->org == NULL)
1079 {
1080 kfree(scq);
1081 return (scq_info *) NULL;
1082 }
1083 scq->skb = (struct sk_buff **) kmalloc(sizeof(struct sk_buff *) *
1084 (size / NS_SCQE_SIZE), GFP_KERNEL);
1085 if (scq->skb == (struct sk_buff **) NULL)
1086 {
1087 kfree(scq->org);
1088 kfree(scq);
1089 return (scq_info *) NULL;
1090 }
1091 scq->num_entries = size / NS_SCQE_SIZE;
1092 scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size);
1093 scq->next = scq->base;
1094 scq->last = scq->base + (scq->num_entries - 1);
1095 scq->tail = scq->last;
1096 scq->scd = scd;
1097 scq->num_entries = size / NS_SCQE_SIZE;
1098 scq->tbd_count = 0;
1099 init_waitqueue_head(&scq->scqfull_waitq);
1100 scq->full = 0;
1101 spin_lock_init(&scq->lock);
1102
1103 for (i = 0; i < scq->num_entries; i++)
1104 scq->skb[i] = NULL;
1105
1106 return scq;
1107 }
1108
1109
1110
1111 /* For variable rate SCQ vcc must be NULL */
1112 static void free_scq(scq_info *scq, struct atm_vcc *vcc)
1113 {
1114 int i;
1115
1116 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
1117 for (i = 0; i < scq->num_entries; i++)
1118 {
1119 if (scq->skb[i] != NULL)
1120 {
1121 vcc = ATM_SKB(scq->skb[i])->vcc;
1122 if (vcc->pop != NULL)
1123 vcc->pop(vcc, scq->skb[i]);
1124 else
1125 dev_kfree_skb_any(scq->skb[i]);
1126 }
1127 }
1128 else /* vcc must be != NULL */
1129 {
1130 if (vcc == NULL)
1131 {
1132 printk("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
1133 for (i = 0; i < scq->num_entries; i++)
1134 dev_kfree_skb_any(scq->skb[i]);
1135 }
1136 else
1137 for (i = 0; i < scq->num_entries; i++)
1138 {
1139 if (scq->skb[i] != NULL)
1140 {
1141 if (vcc->pop != NULL)
1142 vcc->pop(vcc, scq->skb[i]);
1143 else
1144 dev_kfree_skb_any(scq->skb[i]);
1145 }
1146 }
1147 }
1148 kfree(scq->skb);
1149 kfree(scq->org);
1150 kfree(scq);
1151 }
1152
1153
1154
1155 /* The handles passed must be pointers to the sk_buff containing the small
1156 or large buffer(s) cast to u32. */
1157 static void push_rxbufs(ns_dev *card, u32 type, u32 handle1, u32 addr1,
1158 u32 handle2, u32 addr2)
1159 {
1160 u32 stat;
1161 unsigned long flags;
1162
1163
1164 #ifdef GENERAL_DEBUG
1165 if (!addr1)
1166 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", card->index);
1167 #endif /* GENERAL_DEBUG */
1168
1169 stat = readl(card->membase + STAT);
1170 card->sbfqc = ns_stat_sfbqc_get(stat);
1171 card->lbfqc = ns_stat_lfbqc_get(stat);
1172 if (type == BUF_SM)
1173 {
1174 if (!addr2)
1175 {
1176 if (card->sm_addr)
1177 {
1178 addr2 = card->sm_addr;
1179 handle2 = card->sm_handle;
1180 card->sm_addr = 0x00000000;
1181 card->sm_handle = 0x00000000;
1182 }
1183 else /* (!sm_addr) */
1184 {
1185 card->sm_addr = addr1;
1186 card->sm_handle = handle1;
1187 }
1188 }
1189 }
1190 else /* type == BUF_LG */
1191 {
1192 if (!addr2)
1193 {
1194 if (card->lg_addr)
1195 {
1196 addr2 = card->lg_addr;
1197 handle2 = card->lg_handle;
1198 card->lg_addr = 0x00000000;
1199 card->lg_handle = 0x00000000;
1200 }
1201 else /* (!lg_addr) */
1202 {
1203 card->lg_addr = addr1;
1204 card->lg_handle = handle1;
1205 }
1206 }
1207 }
1208
1209 if (addr2)
1210 {
1211 if (type == BUF_SM)
1212 {
1213 if (card->sbfqc >= card->sbnr.max)
1214 {
1215 skb_unlink((struct sk_buff *) handle1);
1216 dev_kfree_skb_any((struct sk_buff *) handle1);
1217 skb_unlink((struct sk_buff *) handle2);
1218 dev_kfree_skb_any((struct sk_buff *) handle2);
1219 return;
1220 }
1221 else
1222 card->sbfqc += 2;
1223 }
1224 else /* (type == BUF_LG) */
1225 {
1226 if (card->lbfqc >= card->lbnr.max)
1227 {
1228 skb_unlink((struct sk_buff *) handle1);
1229 dev_kfree_skb_any((struct sk_buff *) handle1);
1230 skb_unlink((struct sk_buff *) handle2);
1231 dev_kfree_skb_any((struct sk_buff *) handle2);
1232 return;
1233 }
1234 else
1235 card->lbfqc += 2;
1236 }
1237
1238 ns_grab_res_lock(card, flags);
1239
1240 while (CMD_BUSY(card));
1241 writel(addr2, card->membase + DR3);
1242 writel(handle2, card->membase + DR2);
1243 writel(addr1, card->membase + DR1);
1244 writel(handle1, card->membase + DR0);
1245 writel(NS_CMD_WRITE_FREEBUFQ | (u32) type, card->membase + CMD);
1246
1247 spin_unlock_irqrestore(&card->res_lock, flags);
1248
1249 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", card->index,
1250 (type == BUF_SM ? "small" : "large"), addr1, addr2);
1251 }
1252
1253 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1254 card->lbfqc >= card->lbnr.min)
1255 {
1256 card->efbie = 1;
1257 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), card->membase + CFG);
1258 }
1259
1260 return;
1261 }
1262
1263
1264
1265 static void ns_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
1266 {
1267 u32 stat_r;
1268 ns_dev *card;
1269 struct atm_dev *dev;
1270 unsigned long flags;
1271
1272 card = (ns_dev *) dev_id;
1273 dev = card->atmdev;
1274 card->intcnt++;
1275
1276 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1277
1278 ns_grab_int_lock(card, flags);
1279
1280 stat_r = readl(card->membase + STAT);
1281
1282 /* Transmit Status Indicator has been written to T. S. Queue */
1283 if (stat_r & NS_STAT_TSIF)
1284 {
1285 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1286 process_tsq(card);
1287 writel(NS_STAT_TSIF, card->membase + STAT);
1288 }
1289
1290 /* Incomplete CS-PDU has been transmitted */
1291 if (stat_r & NS_STAT_TXICP)
1292 {
1293 writel(NS_STAT_TXICP, card->membase + STAT);
1294 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1295 card->index);
1296 }
1297
1298 /* Transmit Status Queue 7/8 full */
1299 if (stat_r & NS_STAT_TSQF)
1300 {
1301 writel(NS_STAT_TSQF, card->membase + STAT);
1302 PRINTK("nicstar%d: TSQ full.\n", card->index);
1303 process_tsq(card);
1304 }
1305
1306 /* Timer overflow */
1307 if (stat_r & NS_STAT_TMROF)
1308 {
1309 writel(NS_STAT_TMROF, card->membase + STAT);
1310 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1311 }
1312
1313 /* PHY device interrupt signal active */
1314 if (stat_r & NS_STAT_PHYI)
1315 {
1316 writel(NS_STAT_PHYI, card->membase + STAT);
1317 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1318 if (dev->phy && dev->phy->interrupt) {
1319 dev->phy->interrupt(dev);
1320 }
1321 }
1322
1323 /* Small Buffer Queue is full */
1324 if (stat_r & NS_STAT_SFBQF)
1325 {
1326 writel(NS_STAT_SFBQF, card->membase + STAT);
1327 printk("nicstar%d: Small free buffer queue is full.\n", card->index);
1328 }
1329
1330 /* Large Buffer Queue is full */
1331 if (stat_r & NS_STAT_LFBQF)
1332 {
1333 writel(NS_STAT_LFBQF, card->membase + STAT);
1334 printk("nicstar%d: Large free buffer queue is full.\n", card->index);
1335 }
1336
1337 /* Receive Status Queue is full */
1338 if (stat_r & NS_STAT_RSQF)
1339 {
1340 writel(NS_STAT_RSQF, card->membase + STAT);
1341 printk("nicstar%d: RSQ full.\n", card->index);
1342 process_rsq(card);
1343 }
1344
1345 /* Complete CS-PDU received */
1346 if (stat_r & NS_STAT_EOPDU)
1347 {
1348 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1349 process_rsq(card);
1350 writel(NS_STAT_EOPDU, card->membase + STAT);
1351 }
1352
1353 /* Raw cell received */
1354 if (stat_r & NS_STAT_RAWCF)
1355 {
1356 writel(NS_STAT_RAWCF, card->membase + STAT);
1357 #ifndef RCQ_SUPPORT
1358 printk("nicstar%d: Raw cell received and no support yet...\n",
1359 card->index);
1360 #endif /* RCQ_SUPPORT */
1361 /* NOTE: the following procedure may keep a raw cell pending until the
1362 next interrupt. As this preliminary support is only meant to
1363 avoid buffer leakage, this is not an issue. */
1364 while (readl(card->membase + RAWCT) != card->rawch)
1365 {
1366 ns_rcqe *rawcell;
1367
1368 rawcell = (ns_rcqe *) bus_to_virt(card->rawch);
1369 if (ns_rcqe_islast(rawcell))
1370 {
1371 struct sk_buff *oldbuf;
1372
1373 oldbuf = card->rcbuf;
1374 card->rcbuf = (struct sk_buff *) ns_rcqe_nextbufhandle(rawcell);
1375 card->rawch = (u32) virt_to_bus(card->rcbuf->data);
1376 recycle_rx_buf(card, oldbuf);
1377 }
1378 else
1379 card->rawch += NS_RCQE_SIZE;
1380 }
1381 }
1382
1383 /* Small buffer queue is empty */
1384 if (stat_r & NS_STAT_SFBQE)
1385 {
1386 int i;
1387 struct sk_buff *sb;
1388
1389 writel(NS_STAT_SFBQE, card->membase + STAT);
1390 printk("nicstar%d: Small free buffer queue empty.\n",
1391 card->index);
1392 for (i = 0; i < card->sbnr.min; i++)
1393 {
1394 sb = alloc_skb(NS_SMSKBSIZE, GFP_ATOMIC);
1395 if (sb == NULL)
1396 {
1397 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG);
1398 card->efbie = 0;
1399 break;
1400 }
1401 skb_queue_tail(&card->sbpool.queue, sb);
1402 skb_reserve(sb, NS_AAL0_HEADER);
1403 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data), 0, 0);
1404 }
1405 card->sbfqc = i;
1406 process_rsq(card);
1407 }
1408
1409 /* Large buffer queue empty */
1410 if (stat_r & NS_STAT_LFBQE)
1411 {
1412 int i;
1413 struct sk_buff *lb;
1414
1415 writel(NS_STAT_LFBQE, card->membase + STAT);
1416 printk("nicstar%d: Large free buffer queue empty.\n",
1417 card->index);
1418 for (i = 0; i < card->lbnr.min; i++)
1419 {
1420 lb = alloc_skb(NS_LGSKBSIZE, GFP_ATOMIC);
1421 if (lb == NULL)
1422 {
1423 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG);
1424 card->efbie = 0;
1425 break;
1426 }
1427 skb_queue_tail(&card->lbpool.queue, lb);
1428 skb_reserve(lb, NS_SMBUFSIZE);
1429 push_rxbufs(card, BUF_LG, (u32) lb, (u32) virt_to_bus(lb->data), 0, 0);
1430 }
1431 card->lbfqc = i;
1432 process_rsq(card);
1433 }
1434
1435 /* Receive Status Queue is 7/8 full */
1436 if (stat_r & NS_STAT_RSQAF)
1437 {
1438 writel(NS_STAT_RSQAF, card->membase + STAT);
1439 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1440 process_rsq(card);
1441 }
1442
1443 spin_unlock_irqrestore(&card->int_lock, flags);
1444 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1445 }
1446
1447
1448
1449 static int ns_open(struct atm_vcc *vcc, short vpi, int vci)
1450 {
1451 ns_dev *card;
1452 vc_map *vc;
1453 int error;
1454 unsigned long tmpl, modl;
1455 int tcr, tcra; /* target cell rate, and absolute value */
1456 int n = 0; /* Number of entries in the TST. Initialized to remove
1457 the compiler warning. */
1458 u32 u32d[4];
1459 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1460 warning. How I wish compilers were clever enough to
1461 tell which variables can truly be used
1462 uninitialized... */
1463 int inuse; /* tx or rx vc already in use by another vcc */
1464
1465 card = (ns_dev *) vcc->dev->dev_data;
1466 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int) vpi, vci);
1467 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0)
1468 {
1469 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1470 return -EINVAL;
1471 }
1472
1473 if ((error = atm_find_ci(vcc, &vpi, &vci)))
1474 {
1475 PRINTK("nicstar%d: error in atm_find_ci().\n", card->index);
1476 return error;
1477 }
1478 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1479 vcc->vpi = vpi;
1480 vcc->vci = vci;
1481 vcc->dev_data = vc;
1482
1483 inuse = 0;
1484 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1485 inuse = 1;
1486 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1487 inuse += 2;
1488 if (inuse)
1489 {
1490 printk("nicstar%d: %s vci already in use.\n", card->index,
1491 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1492 return -EINVAL;
1493 }
1494
1495 set_bit(ATM_VF_ADDR,&vcc->flags);
1496
1497 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1498 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1499 needed to do that. */
1500 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
1501 {
1502 scq_info *scq;
1503
1504 set_bit(ATM_VF_PARTIAL,&vcc->flags);
1505 if (vcc->qos.txtp.traffic_class == ATM_CBR)
1506 {
1507 /* Check requested cell rate and availability of SCD */
1508 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 &&
1509 vcc->qos.txtp.min_pcr == 0)
1510 {
1511 PRINTK("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1512 card->index);
1513 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1514 clear_bit(ATM_VF_ADDR,&vcc->flags);
1515 return -EINVAL;
1516 }
1517
1518 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1519 tcra = tcr >= 0 ? tcr : -tcr;
1520
1521 PRINTK("nicstar%d: target cell rate = %d.\n", card->index,
1522 vcc->qos.txtp.max_pcr);
1523
1524 tmpl = (unsigned long)tcra * (unsigned long)NS_TST_NUM_ENTRIES;
1525 modl = tmpl % card->max_pcr;
1526
1527 n = (int)(tmpl / card->max_pcr);
1528 if (tcr > 0)
1529 {
1530 if (modl > 0) n++;
1531 }
1532 else if (tcr == 0)
1533 {
1534 if ((n = (card->tst_free_entries - NS_TST_RESERVED)) <= 0)
1535 {
1536 PRINTK("nicstar%d: no CBR bandwidth free.\n", card->index);
1537 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1538 clear_bit(ATM_VF_ADDR,&vcc->flags);
1539 return -EINVAL;
1540 }
1541 }
1542
1543 if (n == 0)
1544 {
1545 printk("nicstar%d: selected bandwidth < granularity.\n", card->index);
1546 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1547 clear_bit(ATM_VF_ADDR,&vcc->flags);
1548 return -EINVAL;
1549 }
1550
1551 if (n > (card->tst_free_entries - NS_TST_RESERVED))
1552 {
1553 PRINTK("nicstar%d: not enough free CBR bandwidth.\n", card->index);
1554 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1555 clear_bit(ATM_VF_ADDR,&vcc->flags);
1556 return -EINVAL;
1557 }
1558 else
1559 card->tst_free_entries -= n;
1560
1561 XPRINTK("nicstar%d: writing %d tst entries.\n", card->index, n);
1562 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++)
1563 {
1564 if (card->scd2vc[frscdi] == NULL)
1565 {
1566 card->scd2vc[frscdi] = vc;
1567 break;
1568 }
1569 }
1570 if (frscdi == NS_FRSCD_NUM)
1571 {
1572 PRINTK("nicstar%d: no SCD available for CBR channel.\n", card->index);
1573 card->tst_free_entries += n;
1574 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1575 clear_bit(ATM_VF_ADDR,&vcc->flags);
1576 return -EBUSY;
1577 }
1578
1579 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1580
1581 scq = get_scq(CBR_SCQSIZE, vc->cbr_scd);
1582 if (scq == (scq_info *) NULL)
1583 {
1584 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", card->index);
1585 card->scd2vc[frscdi] = NULL;
1586 card->tst_free_entries += n;
1587 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1588 clear_bit(ATM_VF_ADDR,&vcc->flags);
1589 return -ENOMEM;
1590 }
1591 vc->scq = scq;
1592 u32d[0] = (u32) virt_to_bus(scq->base);
1593 u32d[1] = (u32) 0x00000000;
1594 u32d[2] = (u32) 0xffffffff;
1595 u32d[3] = (u32) 0x00000000;
1596 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1597
1598 fill_tst(card, n, vc);
1599 }
1600 else /* not CBR */
1601 {
1602 vc->cbr_scd = 0x00000000;
1603 vc->scq = card->scq0;
1604 }
1605
1606 if (vcc->qos.txtp.traffic_class != ATM_NONE)
1607 {
1608 vc->tx = 1;
1609 vc->tx_vcc = vcc;
1610 vc->tbd_count = 0;
1611 }
1612 if (vcc->qos.rxtp.traffic_class != ATM_NONE)
1613 {
1614 u32 status;
1615
1616 vc->rx = 1;
1617 vc->rx_vcc = vcc;
1618 vc->rx_iov = NULL;
1619
1620 /* Open the connection in hardware */
1621 if (vcc->qos.aal == ATM_AAL5)
1622 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1623 else /* vcc->qos.aal == ATM_AAL0 */
1624 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1625 #ifdef RCQ_SUPPORT
1626 status |= NS_RCTE_RAWCELLINTEN;
1627 #endif /* RCQ_SUPPORT */
1628 ns_write_sram(card, NS_RCT + (vpi << card->vcibits | vci) *
1629 NS_RCT_ENTRY_SIZE, &status, 1);
1630 }
1631
1632 }
1633
1634 set_bit(ATM_VF_READY,&vcc->flags);
1635 return 0;
1636 }
1637
1638
1639
1640 static void ns_close(struct atm_vcc *vcc)
1641 {
1642 vc_map *vc;
1643 ns_dev *card;
1644 u32 data;
1645 int i;
1646
1647 vc = vcc->dev_data;
1648 card = vcc->dev->dev_data;
1649 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1650 (int) vcc->vpi, vcc->vci);
1651
1652 clear_bit(ATM_VF_READY,&vcc->flags);
1653
1654 if (vcc->qos.rxtp.traffic_class != ATM_NONE)
1655 {
1656 u32 addr;
1657 unsigned long flags;
1658
1659 addr = NS_RCT + (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1660 ns_grab_res_lock(card, flags);
1661 while(CMD_BUSY(card));
1662 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, card->membase + CMD);
1663 spin_unlock_irqrestore(&card->res_lock, flags);
1664
1665 vc->rx = 0;
1666 if (vc->rx_iov != NULL)
1667 {
1668 struct sk_buff *iovb;
1669 u32 stat;
1670
1671 stat = readl(card->membase + STAT);
1672 card->sbfqc = ns_stat_sfbqc_get(stat);
1673 card->lbfqc = ns_stat_lfbqc_get(stat);
1674
1675 PRINTK("nicstar%d: closing a VC with pending rx buffers.\n",
1676 card->index);
1677 iovb = vc->rx_iov;
1678 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data,
1679 ATM_SKB(iovb)->iovcnt);
1680 ATM_SKB(iovb)->iovcnt = 0;
1681 ATM_SKB(iovb)->vcc = NULL;
1682 ns_grab_int_lock(card, flags);
1683 recycle_iov_buf(card, iovb);
1684 spin_unlock_irqrestore(&card->int_lock, flags);
1685 vc->rx_iov = NULL;
1686 }
1687 }
1688
1689 if (vcc->qos.txtp.traffic_class != ATM_NONE)
1690 {
1691 vc->tx = 0;
1692 }
1693
1694 if (vcc->qos.txtp.traffic_class == ATM_CBR)
1695 {
1696 unsigned long flags;
1697 ns_scqe *scqep;
1698 scq_info *scq;
1699
1700 scq = vc->scq;
1701
1702 for (;;)
1703 {
1704 ns_grab_scq_lock(card, scq, flags);
1705 scqep = scq->next;
1706 if (scqep == scq->base)
1707 scqep = scq->last;
1708 else
1709 scqep--;
1710 if (scqep == scq->tail)
1711 {
1712 spin_unlock_irqrestore(&scq->lock, flags);
1713 break;
1714 }
1715 /* If the last entry is not a TSR, place one in the SCQ in order to
1716 be able to completely drain it and then close. */
1717 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next)
1718 {
1719 ns_scqe tsr;
1720 u32 scdi, scqi;
1721 u32 data;
1722 int index;
1723
1724 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1725 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1726 scqi = scq->next - scq->base;
1727 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1728 tsr.word_3 = 0x00000000;
1729 tsr.word_4 = 0x00000000;
1730 *scq->next = tsr;
1731 index = (int) scqi;
1732 scq->skb[index] = NULL;
1733 if (scq->next == scq->last)
1734 scq->next = scq->base;
1735 else
1736 scq->next++;
1737 data = (u32) virt_to_bus(scq->next);
1738 ns_write_sram(card, scq->scd, &data, 1);
1739 }
1740 spin_unlock_irqrestore(&scq->lock, flags);
1741 schedule();
1742 }
1743
1744 /* Free all TST entries */
1745 data = NS_TST_OPCODE_VARIABLE;
1746 for (i = 0; i < NS_TST_NUM_ENTRIES; i++)
1747 {
1748 if (card->tste2vc[i] == vc)
1749 {
1750 ns_write_sram(card, card->tst_addr + i, &data, 1);
1751 card->tste2vc[i] = NULL;
1752 card->tst_free_entries++;
1753 }
1754 }
1755
1756 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1757 free_scq(vc->scq, vcc);
1758 }
1759
1760 vcc->dev_data = NULL;
1761 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1762 clear_bit(ATM_VF_ADDR,&vcc->flags);
1763
1764 #ifdef RX_DEBUG
1765 {
1766 u32 stat, cfg;
1767 stat = readl(card->membase + STAT);
1768 cfg = readl(card->membase + CFG);
1769 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1770 printk("TSQ: base = 0x%08X next = 0x%08X last = 0x%08X TSQT = 0x%08X \n",
1771 (u32) card->tsq.base, (u32) card->tsq.next,(u32) card->tsq.last,
1772 readl(card->membase + TSQT));
1773 printk("RSQ: base = 0x%08X next = 0x%08X last = 0x%08X RSQT = 0x%08X \n",
1774 (u32) card->rsq.base, (u32) card->rsq.next,(u32) card->rsq.last,
1775 readl(card->membase + RSQT));
1776 printk("Empty free buffer queue interrupt %s \n",
1777 card->efbie ? "enabled" : "disabled");
1778 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1779 ns_stat_sfbqc_get(stat), card->sbpool.count,
1780 ns_stat_lfbqc_get(stat), card->lbpool.count);
1781 printk("hbpool.count = %d iovpool.count = %d \n",
1782 card->hbpool.count, card->iovpool.count);
1783 }
1784 #endif /* RX_DEBUG */
1785 }
1786
1787
1788
1789 static void fill_tst(ns_dev *card, int n, vc_map *vc)
1790 {
1791 u32 new_tst;
1792 unsigned long cl;
1793 int e, r;
1794 u32 data;
1795
1796 /* It would be very complicated to keep the two TSTs synchronized while
1797 assuring that writes are only made to the inactive TST. So, for now I
1798 will use only one TST. If problems occur, I will change this again */
1799
1800 new_tst = card->tst_addr;
1801
1802 /* Fill procedure */
1803
1804 for (e = 0; e < NS_TST_NUM_ENTRIES; e++)
1805 {
1806 if (card->tste2vc[e] == NULL)
1807 break;
1808 }
1809 if (e == NS_TST_NUM_ENTRIES) {
1810 printk("nicstar%d: No free TST entries found. \n", card->index);
1811 return;
1812 }
1813
1814 r = n;
1815 cl = NS_TST_NUM_ENTRIES;
1816 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1817
1818 while (r > 0)
1819 {
1820 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL)
1821 {
1822 card->tste2vc[e] = vc;
1823 ns_write_sram(card, new_tst + e, &data, 1);
1824 cl -= NS_TST_NUM_ENTRIES;
1825 r--;
1826 }
1827
1828 if (++e == NS_TST_NUM_ENTRIES) {
1829 e = 0;
1830 }
1831 cl += n;
1832 }
1833
1834 /* End of fill procedure */
1835
1836 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1837 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1838 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1839 card->tst_addr = new_tst;
1840 }
1841
1842
1843
1844 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1845 {
1846 ns_dev *card;
1847 vc_map *vc;
1848 scq_info *scq;
1849 unsigned long buflen;
1850 ns_scqe scqe;
1851 u32 flags; /* TBD flags, not CPU flags */
1852
1853 card = vcc->dev->dev_data;
1854 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1855 if ((vc = (vc_map *) vcc->dev_data) == NULL)
1856 {
1857 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", card->index);
1858 atomic_inc(&vcc->stats->tx_err);
1859 dev_kfree_skb_any(skb);
1860 return -EINVAL;
1861 }
1862
1863 if (!vc->tx)
1864 {
1865 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", card->index);
1866 atomic_inc(&vcc->stats->tx_err);
1867 dev_kfree_skb_any(skb);
1868 return -EINVAL;
1869 }
1870
1871 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0)
1872 {
1873 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", card->index);
1874 atomic_inc(&vcc->stats->tx_err);
1875 dev_kfree_skb_any(skb);
1876 return -EINVAL;
1877 }
1878
1879 if (ATM_SKB(skb)->iovcnt != 0)
1880 {
1881 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1882 atomic_inc(&vcc->stats->tx_err);
1883 dev_kfree_skb_any(skb);
1884 return -EINVAL;
1885 }
1886
1887 ATM_SKB(skb)->vcc = vcc;
1888
1889 if (vcc->qos.aal == ATM_AAL5)
1890 {
1891 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1892 flags = NS_TBD_AAL5;
1893 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data));
1894 scqe.word_3 = cpu_to_le32((u32) skb->len);
1895 scqe.word_4 = ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1896 ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1897 flags |= NS_TBD_EOPDU;
1898 }
1899 else /* (vcc->qos.aal == ATM_AAL0) */
1900 {
1901 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1902 flags = NS_TBD_AAL0;
1903 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data) + NS_AAL0_HEADER);
1904 scqe.word_3 = cpu_to_le32(0x00000000);
1905 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1906 flags |= NS_TBD_EOPDU;
1907 scqe.word_4 = cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1908 /* Force the VPI/VCI to be the same as in VCC struct */
1909 scqe.word_4 |= cpu_to_le32((((u32) vcc->vpi) << NS_TBD_VPI_SHIFT |
1910 ((u32) vcc->vci) << NS_TBD_VCI_SHIFT) &
1911 NS_TBD_VC_MASK);
1912 }
1913
1914 if (vcc->qos.txtp.traffic_class == ATM_CBR)
1915 {
1916 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1917 scq = ((vc_map *) vcc->dev_data)->scq;
1918 }
1919 else
1920 {
1921 scqe.word_1 = ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1922 scq = card->scq0;
1923 }
1924
1925 if (push_scqe(card, vc, scq, &scqe, skb) != 0)
1926 {
1927 atomic_inc(&vcc->stats->tx_err);
1928 dev_kfree_skb_any(skb);
1929 return -EIO;
1930 }
1931 atomic_inc(&vcc->stats->tx);
1932
1933 return 0;
1934 }
1935
1936
1937
1938 static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd,
1939 struct sk_buff *skb)
1940 {
1941 unsigned long flags;
1942 ns_scqe tsr;
1943 u32 scdi, scqi;
1944 int scq_is_vbr;
1945 u32 data;
1946 int index;
1947
1948 ns_grab_scq_lock(card, scq, flags);
1949 while (scq->tail == scq->next)
1950 {
1951 if (in_interrupt()) {
1952 spin_unlock_irqrestore(&scq->lock, flags);
1953 printk("nicstar%d: Error pushing TBD.\n", card->index);
1954 return 1;
1955 }
1956
1957 scq->full = 1;
1958 spin_unlock_irqrestore(&scq->lock, flags);
1959 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
1960 ns_grab_scq_lock(card, scq, flags);
1961
1962 if (scq->full) {
1963 spin_unlock_irqrestore(&scq->lock, flags);
1964 printk("nicstar%d: Timeout pushing TBD.\n", card->index);
1965 return 1;
1966 }
1967 }
1968 *scq->next = *tbd;
1969 index = (int) (scq->next - scq->base);
1970 scq->skb[index] = skb;
1971 XPRINTK("nicstar%d: sending skb at 0x%x (pos %d).\n",
1972 card->index, (u32) skb, index);
1973 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
1974 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1975 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1976 (u32) scq->next);
1977 if (scq->next == scq->last)
1978 scq->next = scq->base;
1979 else
1980 scq->next++;
1981
1982 vc->tbd_count++;
1983 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
1984 {
1985 scq->tbd_count++;
1986 scq_is_vbr = 1;
1987 }
1988 else
1989 scq_is_vbr = 0;
1990
1991 if (vc->tbd_count >= MAX_TBD_PER_VC || scq->tbd_count >= MAX_TBD_PER_SCQ)
1992 {
1993 int has_run = 0;
1994
1995 while (scq->tail == scq->next)
1996 {
1997 if (in_interrupt()) {
1998 data = (u32) virt_to_bus(scq->next);
1999 ns_write_sram(card, scq->scd, &data, 1);
2000 spin_unlock_irqrestore(&scq->lock, flags);
2001 printk("nicstar%d: Error pushing TSR.\n", card->index);
2002 return 0;
2003 }
2004
2005 scq->full = 1;
2006 if (has_run++) break;
2007 spin_unlock_irqrestore(&scq->lock, flags);
2008 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
2009 ns_grab_scq_lock(card, scq, flags);
2010 }
2011
2012 if (!scq->full)
2013 {
2014 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
2015 if (scq_is_vbr)
2016 scdi = NS_TSR_SCDISVBR;
2017 else
2018 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
2019 scqi = scq->next - scq->base;
2020 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
2021 tsr.word_3 = 0x00000000;
2022 tsr.word_4 = 0x00000000;
2023
2024 *scq->next = tsr;
2025 index = (int) scqi;
2026 scq->skb[index] = NULL;
2027 XPRINTK("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
2028 card->index, le32_to_cpu(tsr.word_1), le32_to_cpu(tsr.word_2),
2029 le32_to_cpu(tsr.word_3), le32_to_cpu(tsr.word_4),
2030 (u32) scq->next);
2031 if (scq->next == scq->last)
2032 scq->next = scq->base;
2033 else
2034 scq->next++;
2035 vc->tbd_count = 0;
2036 scq->tbd_count = 0;
2037 }
2038 else
2039 PRINTK("nicstar%d: Timeout pushing TSR.\n", card->index);
2040 }
2041 data = (u32) virt_to_bus(scq->next);
2042 ns_write_sram(card, scq->scd, &data, 1);
2043
2044 spin_unlock_irqrestore(&scq->lock, flags);
2045
2046 return 0;
2047 }
2048
2049
2050
2051 static void process_tsq(ns_dev *card)
2052 {
2053 u32 scdi;
2054 scq_info *scq;
2055 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
2056 int serviced_entries; /* flag indicating at least on entry was serviced */
2057
2058 serviced_entries = 0;
2059
2060 if (card->tsq.next == card->tsq.last)
2061 one_ahead = card->tsq.base;
2062 else
2063 one_ahead = card->tsq.next + 1;
2064
2065 if (one_ahead == card->tsq.last)
2066 two_ahead = card->tsq.base;
2067 else
2068 two_ahead = one_ahead + 1;
2069
2070 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
2071 !ns_tsi_isempty(two_ahead))
2072 /* At most two empty, as stated in the 77201 errata */
2073 {
2074 serviced_entries = 1;
2075
2076 /* Skip the one or two possible empty entries */
2077 while (ns_tsi_isempty(card->tsq.next)) {
2078 if (card->tsq.next == card->tsq.last)
2079 card->tsq.next = card->tsq.base;
2080 else
2081 card->tsq.next++;
2082 }
2083
2084 if (!ns_tsi_tmrof(card->tsq.next))
2085 {
2086 scdi = ns_tsi_getscdindex(card->tsq.next);
2087 if (scdi == NS_TSI_SCDISVBR)
2088 scq = card->scq0;
2089 else
2090 {
2091 if (card->scd2vc[scdi] == NULL)
2092 {
2093 printk("nicstar%d: could not find VC from SCD index.\n",
2094 card->index);
2095 ns_tsi_init(card->tsq.next);
2096 return;
2097 }
2098 scq = card->scd2vc[scdi]->scq;
2099 }
2100 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
2101 scq->full = 0;
2102 wake_up_interruptible(&(scq->scqfull_waitq));
2103 }
2104
2105 ns_tsi_init(card->tsq.next);
2106 previous = card->tsq.next;
2107 if (card->tsq.next == card->tsq.last)
2108 card->tsq.next = card->tsq.base;
2109 else
2110 card->tsq.next++;
2111
2112 if (card->tsq.next == card->tsq.last)
2113 one_ahead = card->tsq.base;
2114 else
2115 one_ahead = card->tsq.next + 1;
2116
2117 if (one_ahead == card->tsq.last)
2118 two_ahead = card->tsq.base;
2119 else
2120 two_ahead = one_ahead + 1;
2121 }
2122
2123 if (serviced_entries) {
2124 writel((((u32) previous) - ((u32) card->tsq.base)),
2125 card->membase + TSQH);
2126 }
2127 }
2128
2129
2130
2131 static void drain_scq(ns_dev *card, scq_info *scq, int pos)
2132 {
2133 struct atm_vcc *vcc;
2134 struct sk_buff *skb;
2135 int i;
2136 unsigned long flags;
2137
2138 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%x, pos %d.\n",
2139 card->index, (u32) scq, pos);
2140 if (pos >= scq->num_entries)
2141 {
2142 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
2143 return;
2144 }
2145
2146 ns_grab_scq_lock(card, scq, flags);
2147 i = (int) (scq->tail - scq->base);
2148 if (++i == scq->num_entries)
2149 i = 0;
2150 while (i != pos)
2151 {
2152 skb = scq->skb[i];
2153 XPRINTK("nicstar%d: freeing skb at 0x%x (index %d).\n",
2154 card->index, (u32) skb, i);
2155 if (skb != NULL)
2156 {
2157 vcc = ATM_SKB(skb)->vcc;
2158 if (vcc->pop != NULL) {
2159 vcc->pop(vcc, skb);
2160 } else {
2161 dev_kfree_skb_irq(skb);
2162 }
2163 scq->skb[i] = NULL;
2164 }
2165 if (++i == scq->num_entries)
2166 i = 0;
2167 }
2168 scq->tail = scq->base + pos;
2169 spin_unlock_irqrestore(&scq->lock, flags);
2170 }
2171
2172
2173
2174 static void process_rsq(ns_dev *card)
2175 {
2176 ns_rsqe *previous;
2177
2178 if (!ns_rsqe_valid(card->rsq.next))
2179 return;
2180 while (ns_rsqe_valid(card->rsq.next))
2181 {
2182 dequeue_rx(card, card->rsq.next);
2183 ns_rsqe_init(card->rsq.next);
2184 previous = card->rsq.next;
2185 if (card->rsq.next == card->rsq.last)
2186 card->rsq.next = card->rsq.base;
2187 else
2188 card->rsq.next++;
2189 }
2190 writel((((u32) previous) - ((u32) card->rsq.base)),
2191 card->membase + RSQH);
2192 }
2193
2194
2195
2196 static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe)
2197 {
2198 u32 vpi, vci;
2199 vc_map *vc;
2200 struct sk_buff *iovb;
2201 struct iovec *iov;
2202 struct atm_vcc *vcc;
2203 struct sk_buff *skb;
2204 unsigned short aal5_len;
2205 int len;
2206 u32 stat;
2207
2208 stat = readl(card->membase + STAT);
2209 card->sbfqc = ns_stat_sfbqc_get(stat);
2210 card->lbfqc = ns_stat_lfbqc_get(stat);
2211
2212 skb = (struct sk_buff *) le32_to_cpu(rsqe->buffer_handle);
2213 vpi = ns_rsqe_vpi(rsqe);
2214 vci = ns_rsqe_vci(rsqe);
2215 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits)
2216 {
2217 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2218 card->index, vpi, vci);
2219 recycle_rx_buf(card, skb);
2220 return;
2221 }
2222
2223 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2224 if (!vc->rx)
2225 {
2226 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2227 card->index, vpi, vci);
2228 recycle_rx_buf(card, skb);
2229 return;
2230 }
2231
2232 vcc = vc->rx_vcc;
2233
2234 if (vcc->qos.aal == ATM_AAL0)
2235 {
2236 struct sk_buff *sb;
2237 unsigned char *cell;
2238 int i;
2239
2240 cell = skb->data;
2241 for (i = ns_rsqe_cellcount(rsqe); i; i--)
2242 {
2243 if ((sb = alloc_skb(NS_SMSKBSIZE, GFP_ATOMIC)) == NULL)
2244 {
2245 printk("nicstar%d: Can't allocate buffers for aal0.\n",
2246 card->index);
2247 atomic_add(i,&vcc->stats->rx_drop);
2248 break;
2249 }
2250 if (!atm_charge(vcc, sb->truesize))
2251 {
2252 RXPRINTK("nicstar%d: atm_charge() dropped aal0 packets.\n",
2253 card->index);
2254 atomic_add(i-1,&vcc->stats->rx_drop); /* already increased by 1 */
2255 dev_kfree_skb_any(sb);
2256 break;
2257 }
2258 /* Rebuild the header */
2259 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2260 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2261 if (i == 1 && ns_rsqe_eopdu(rsqe))
2262 *((u32 *) sb->data) |= 0x00000002;
2263 skb_put(sb, NS_AAL0_HEADER);
2264 memcpy(sb->tail, cell, ATM_CELL_PAYLOAD);
2265 skb_put(sb, ATM_CELL_PAYLOAD);
2266 ATM_SKB(sb)->vcc = vcc;
2267 sb->stamp = xtime;
2268 vcc->push(vcc, sb);
2269 atomic_inc(&vcc->stats->rx);
2270 cell += ATM_CELL_PAYLOAD;
2271 }
2272
2273 recycle_rx_buf(card, skb);
2274 return;
2275 }
2276
2277 /* To reach this point, the AAL layer can only be AAL5 */
2278
2279 if ((iovb = vc->rx_iov) == NULL)
2280 {
2281 iovb = skb_dequeue(&(card->iovpool.queue));
2282 if (iovb == NULL) /* No buffers in the queue */
2283 {
2284 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2285 if (iovb == NULL)
2286 {
2287 printk("nicstar%d: Out of iovec buffers.\n", card->index);
2288 atomic_inc(&vcc->stats->rx_drop);
2289 recycle_rx_buf(card, skb);
2290 return;
2291 }
2292 }
2293 else
2294 if (--card->iovpool.count < card->iovnr.min)
2295 {
2296 struct sk_buff *new_iovb;
2297 if ((new_iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL)
2298 {
2299 skb_queue_tail(&card->iovpool.queue, new_iovb);
2300 card->iovpool.count++;
2301 }
2302 }
2303 vc->rx_iov = iovb;
2304 ATM_SKB(iovb)->iovcnt = 0;
2305 iovb->len = 0;
2306 iovb->tail = iovb->data = iovb->head;
2307 ATM_SKB(iovb)->vcc = vcc;
2308 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2309 buffer is stored as iovec base, NOT a pointer to the
2310 small or large buffer itself. */
2311 }
2312 else if (ATM_SKB(iovb)->iovcnt >= NS_MAX_IOVECS)
2313 {
2314 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2315 atomic_inc(&vcc->stats->rx_err);
2316 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, NS_MAX_IOVECS);
2317 ATM_SKB(iovb)->iovcnt = 0;
2318 iovb->len = 0;
2319 iovb->tail = iovb->data = iovb->head;
2320 ATM_SKB(iovb)->vcc = vcc;
2321 }
2322 iov = &((struct iovec *) iovb->data)[ATM_SKB(iovb)->iovcnt++];
2323 iov->iov_base = (void *) skb;
2324 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2325 iovb->len += iov->iov_len;
2326
2327 if (ATM_SKB(iovb)->iovcnt == 1)
2328 {
2329 if (skb->list != &card->sbpool.queue)
2330 {
2331 printk("nicstar%d: Expected a small buffer, and this is not one.\n",
2332 card->index);
2333 which_list(card, skb);
2334 atomic_inc(&vcc->stats->rx_err);
2335 recycle_rx_buf(card, skb);
2336 vc->rx_iov = NULL;
2337 recycle_iov_buf(card, iovb);
2338 return;
2339 }
2340 }
2341 else /* ATM_SKB(iovb)->iovcnt >= 2 */
2342 {
2343 if (skb->list != &card->lbpool.queue)
2344 {
2345 printk("nicstar%d: Expected a large buffer, and this is not one.\n",
2346 card->index);
2347 which_list(card, skb);
2348 atomic_inc(&vcc->stats->rx_err);
2349 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data,
2350 ATM_SKB(iovb)->iovcnt);
2351 vc->rx_iov = NULL;
2352 recycle_iov_buf(card, iovb);
2353 return;
2354 }
2355 }
2356
2357 if (ns_rsqe_eopdu(rsqe))
2358 {
2359 /* This works correctly regardless of the endianness of the host */
2360 unsigned char *L1L2 = (unsigned char *)((u32)skb->data +
2361 iov->iov_len - 6);
2362 aal5_len = L1L2[0] << 8 | L1L2[1];
2363 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2364 if (ns_rsqe_crcerr(rsqe) ||
2365 len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2366 {
2367 printk("nicstar%d: AAL5 CRC error", card->index);
2368 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2369 printk(" - PDU size mismatch.\n");
2370 else
2371 printk(".\n");
2372 atomic_inc(&vcc->stats->rx_err);
2373 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data,
2374 ATM_SKB(iovb)->iovcnt);
2375 vc->rx_iov = NULL;
2376 recycle_iov_buf(card, iovb);
2377 return;
2378 }
2379
2380 /* By this point we (hopefully) have a complete SDU without errors. */
2381
2382 if (ATM_SKB(iovb)->iovcnt == 1) /* Just a small buffer */
2383 {
2384 /* skb points to a small buffer */
2385 if (!atm_charge(vcc, skb->truesize))
2386 {
2387 push_rxbufs(card, BUF_SM, (u32) skb, (u32) virt_to_bus(skb->data),
2388 0, 0);
2389 }
2390 else
2391 {
2392 skb_put(skb, len);
2393 dequeue_sm_buf(card, skb);
2394 #ifdef NS_USE_DESTRUCTORS
2395 skb->destructor = ns_sb_destructor;
2396 #endif /* NS_USE_DESTRUCTORS */
2397 ATM_SKB(skb)->vcc = vcc;
2398 skb->stamp = xtime;
2399 vcc->push(vcc, skb);
2400 atomic_inc(&vcc->stats->rx);
2401 }
2402 }
2403 else if (ATM_SKB(iovb)->iovcnt == 2) /* One small plus one large buffer */
2404 {
2405 struct sk_buff *sb;
2406
2407 sb = (struct sk_buff *) (iov - 1)->iov_base;
2408 /* skb points to a large buffer */
2409
2410 if (len <= NS_SMBUFSIZE)
2411 {
2412 if (!atm_charge(vcc, sb->truesize))
2413 {
2414 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data),
2415 0, 0);
2416 }
2417 else
2418 {
2419 skb_put(sb, len);
2420 dequeue_sm_buf(card, sb);
2421 #ifdef NS_USE_DESTRUCTORS
2422 sb->destructor = ns_sb_destructor;
2423 #endif /* NS_USE_DESTRUCTORS */
2424 ATM_SKB(sb)->vcc = vcc;
2425 sb->stamp = xtime;
2426 vcc->push(vcc, sb);
2427 atomic_inc(&vcc->stats->rx);
2428 }
2429
2430 push_rxbufs(card, BUF_LG, (u32) skb,
2431 (u32) virt_to_bus(skb->data), 0, 0);
2432
2433 }
2434 else /* len > NS_SMBUFSIZE, the usual case */
2435 {
2436 if (!atm_charge(vcc, skb->truesize))
2437 {
2438 push_rxbufs(card, BUF_LG, (u32) skb,
2439 (u32) virt_to_bus(skb->data), 0, 0);
2440 }
2441 else
2442 {
2443 dequeue_lg_buf(card, skb);
2444 #ifdef NS_USE_DESTRUCTORS
2445 skb->destructor = ns_lb_destructor;
2446 #endif /* NS_USE_DESTRUCTORS */
2447 skb_push(skb, NS_SMBUFSIZE);
2448 memcpy(skb->data, sb->data, NS_SMBUFSIZE);
2449 skb_put(skb, len - NS_SMBUFSIZE);
2450 ATM_SKB(skb)->vcc = vcc;
2451 skb->stamp = xtime;
2452 vcc->push(vcc, skb);
2453 atomic_inc(&vcc->stats->rx);
2454 }
2455
2456 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data),
2457 0, 0);
2458
2459 }
2460
2461 }
2462 else /* Must push a huge buffer */
2463 {
2464 struct sk_buff *hb, *sb, *lb;
2465 int remaining, tocopy;
2466 int j;
2467
2468 hb = skb_dequeue(&(card->hbpool.queue));
2469 if (hb == NULL) /* No buffers in the queue */
2470 {
2471
2472 hb = alloc_skb(NS_HBUFSIZE, GFP_ATOMIC);
2473 if (hb == NULL)
2474 {
2475 printk("nicstar%d: Out of huge buffers.\n", card->index);
2476 atomic_inc(&vcc->stats->rx_drop);
2477 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data,
2478 ATM_SKB(iovb)->iovcnt);
2479 vc->rx_iov = NULL;
2480 recycle_iov_buf(card, iovb);
2481 return;
2482 }
2483 else if (card->hbpool.count < card->hbnr.min)
2484 {
2485 struct sk_buff *new_hb;
2486 if ((new_hb = alloc_skb(NS_HBUFSIZE, GFP_ATOMIC)) != NULL)
2487 {
2488 skb_queue_tail(&card->hbpool.queue, new_hb);
2489 card->hbpool.count++;
2490 }
2491 }
2492 }
2493 else
2494 if (--card->hbpool.count < card->hbnr.min)
2495 {
2496 struct sk_buff *new_hb;
2497 if ((new_hb = alloc_skb(NS_HBUFSIZE, GFP_ATOMIC)) != NULL)
2498 {
2499 skb_queue_tail(&card->hbpool.queue, new_hb);
2500 card->hbpool.count++;
2501 }
2502 if (card->hbpool.count < card->hbnr.min)
2503 {
2504 if ((new_hb = alloc_skb(NS_HBUFSIZE, GFP_ATOMIC)) != NULL)
2505 {
2506 skb_queue_tail(&card->hbpool.queue, new_hb);
2507 card->hbpool.count++;
2508 }
2509 }
2510 }
2511
2512 iov = (struct iovec *) iovb->data;
2513
2514 if (!atm_charge(vcc, hb->truesize))
2515 {
2516 recycle_iovec_rx_bufs(card, iov, ATM_SKB(iovb)->iovcnt);
2517 if (card->hbpool.count < card->hbnr.max)
2518 {
2519 skb_queue_tail(&card->hbpool.queue, hb);
2520 card->hbpool.count++;
2521 }
2522 else
2523 dev_kfree_skb_any(hb);
2524 }
2525 else
2526 {
2527 /* Copy the small buffer to the huge buffer */
2528 sb = (struct sk_buff *) iov->iov_base;
2529 memcpy(hb->data, sb->data, iov->iov_len);
2530 skb_put(hb, iov->iov_len);
2531 remaining = len - iov->iov_len;
2532 iov++;
2533 /* Free the small buffer */
2534 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data),
2535 0, 0);
2536
2537 /* Copy all large buffers to the huge buffer and free them */
2538 for (j = 1; j < ATM_SKB(iovb)->iovcnt; j++)
2539 {
2540 lb = (struct sk_buff *) iov->iov_base;
2541 tocopy = MIN(remaining, iov->iov_len);
2542 memcpy(hb->tail, lb->data, tocopy);
2543 skb_put(hb, tocopy);
2544 iov++;
2545 remaining -= tocopy;
2546 push_rxbufs(card, BUF_LG, (u32) lb,
2547 (u32) virt_to_bus(lb->data), 0, 0);
2548 }
2549 #ifdef EXTRA_DEBUG
2550 if (remaining != 0 || hb->len != len)
2551 printk("nicstar%d: Huge buffer len mismatch.\n", card->index);
2552 #endif /* EXTRA_DEBUG */
2553 ATM_SKB(hb)->vcc = vcc;
2554 #ifdef NS_USE_DESTRUCTORS
2555 hb->destructor = ns_hb_destructor;
2556 #endif /* NS_USE_DESTRUCTORS */
2557 hb->stamp = xtime;
2558 vcc->push(vcc, hb);
2559 atomic_inc(&vcc->stats->rx);
2560 }
2561 }
2562
2563 vc->rx_iov = NULL;
2564 recycle_iov_buf(card, iovb);
2565 }
2566
2567 }
2568
2569
2570
2571 #ifdef NS_USE_DESTRUCTORS
2572
2573 static void ns_sb_destructor(struct sk_buff *sb)
2574 {
2575 ns_dev *card;
2576 u32 stat;
2577
2578 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data;
2579 stat = readl(card->membase + STAT);
2580 card->sbfqc = ns_stat_sfbqc_get(stat);
2581 card->lbfqc = ns_stat_lfbqc_get(stat);
2582
2583 do
2584 {
2585 sb = alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2586 if (sb == NULL)
2587 break;
2588 skb_queue_tail(&card->sbpool.queue, sb);
2589 skb_reserve(sb, NS_AAL0_HEADER);
2590 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data), 0, 0);
2591 } while (card->sbfqc < card->sbnr.min);
2592 }
2593
2594
2595
2596 static void ns_lb_destructor(struct sk_buff *lb)
2597 {
2598 ns_dev *card;
2599 u32 stat;
2600
2601 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data;
2602 stat = readl(card->membase + STAT);
2603 card->sbfqc = ns_stat_sfbqc_get(stat);
2604 card->lbfqc = ns_stat_lfbqc_get(stat);
2605
2606 do
2607 {
2608 lb = alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2609 if (lb == NULL)
2610 break;
2611 skb_queue_tail(&card->lbpool.queue, lb);
2612 skb_reserve(lb, NS_SMBUFSIZE);
2613 push_rxbufs(card, BUF_LG, (u32) lb, (u32) virt_to_bus(lb->data), 0, 0);
2614 } while (card->lbfqc < card->lbnr.min);
2615 }
2616
2617
2618
2619 static void ns_hb_destructor(struct sk_buff *hb)
2620 {
2621 ns_dev *card;
2622
2623 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data;
2624
2625 while (card->hbpool.count < card->hbnr.init)
2626 {
2627 hb = alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2628 if (hb == NULL)
2629 break;
2630 skb_queue_tail(&card->hbpool.queue, hb);
2631 card->hbpool.count++;
2632 }
2633 }
2634
2635 #endif /* NS_USE_DESTRUCTORS */
2636
2637
2638
2639 static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb)
2640 {
2641 if (skb->list == &card->sbpool.queue)
2642 push_rxbufs(card, BUF_SM, (u32) skb, (u32) virt_to_bus(skb->data), 0, 0);
2643 else if (skb->list == &card->lbpool.queue)
2644 push_rxbufs(card, BUF_LG, (u32) skb, (u32) virt_to_bus(skb->data), 0, 0);
2645 else
2646 {
2647 printk("nicstar%d: What kind of rx buffer is this?\n", card->index);
2648 dev_kfree_skb_any(skb);
2649 }
2650 }
2651
2652
2653
2654 static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count)
2655 {
2656 struct sk_buff *skb;
2657
2658 for (; count > 0; count--)
2659 {
2660 skb = (struct sk_buff *) (iov++)->iov_base;
2661 if (skb->list == &card->sbpool.queue)
2662 push_rxbufs(card, BUF_SM, (u32) skb, (u32) virt_to_bus(skb->data),
2663 0, 0);
2664 else if (skb->list == &card->lbpool.queue)
2665 push_rxbufs(card, BUF_LG, (u32) skb, (u32) virt_to_bus(skb->data),
2666 0, 0);
2667 else
2668 {
2669 printk("nicstar%d: What kind of rx buffer is this?\n", card->index);
2670 dev_kfree_skb_any(skb);
2671 }
2672 }
2673 }
2674
2675
2676
2677 static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb)
2678 {
2679 if (card->iovpool.count < card->iovnr.max)
2680 {
2681 skb_queue_tail(&card->iovpool.queue, iovb);
2682 card->iovpool.count++;
2683 }
2684 else
2685 dev_kfree_skb_any(iovb);
2686 }
2687
2688
2689
2690 static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb)
2691 {
2692 skb_unlink(sb);
2693 #ifdef NS_USE_DESTRUCTORS
2694 if (card->sbfqc < card->sbnr.min)
2695 #else
2696 if (card->sbfqc < card->sbnr.init)
2697 {
2698 struct sk_buff *new_sb;
2699 if ((new_sb = alloc_skb(NS_SMSKBSIZE, GFP_ATOMIC)) != NULL)
2700 {
2701 skb_queue_tail(&card->sbpool.queue, new_sb);
2702 skb_reserve(new_sb, NS_AAL0_HEADER);
2703 push_rxbufs(card, BUF_SM, (u32) new_sb,
2704 (u32) virt_to_bus(new_sb->data), 0, 0);
2705 }
2706 }
2707 if (card->sbfqc < card->sbnr.init)
2708 #endif /* NS_USE_DESTRUCTORS */
2709 {
2710 struct sk_buff *new_sb;
2711 if ((new_sb = alloc_skb(NS_SMSKBSIZE, GFP_ATOMIC)) != NULL)
2712 {
2713 skb_queue_tail(&card->sbpool.queue, new_sb);
2714 skb_reserve(new_sb, NS_AAL0_HEADER);
2715 push_rxbufs(card, BUF_SM, (u32) new_sb,
2716 (u32) virt_to_bus(new_sb->data), 0, 0);
2717 }
2718 }
2719 }
2720
2721
2722
2723 static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb)
2724 {
2725 skb_unlink(lb);
2726 #ifdef NS_USE_DESTRUCTORS
2727 if (card->lbfqc < card->lbnr.min)
2728 #else
2729 if (card->lbfqc < card->lbnr.init)
2730 {
2731 struct sk_buff *new_lb;
2732 if ((new_lb = alloc_skb(NS_LGSKBSIZE, GFP_ATOMIC)) != NULL)
2733 {
2734 skb_queue_tail(&card->lbpool.queue, new_lb);
2735 skb_reserve(new_lb, NS_SMBUFSIZE);
2736 push_rxbufs(card, BUF_LG, (u32) new_lb,
2737 (u32) virt_to_bus(new_lb->data), 0, 0);
2738 }
2739 }
2740 if (card->lbfqc < card->lbnr.init)
2741 #endif /* NS_USE_DESTRUCTORS */
2742 {
2743 struct sk_buff *new_lb;
2744 if ((new_lb = alloc_skb(NS_LGSKBSIZE, GFP_ATOMIC)) != NULL)
2745 {
2746 skb_queue_tail(&card->lbpool.queue, new_lb);
2747 skb_reserve(new_lb, NS_SMBUFSIZE);
2748 push_rxbufs(card, BUF_LG, (u32) new_lb,
2749 (u32) virt_to_bus(new_lb->data), 0, 0);
2750 }
2751 }
2752 }
2753
2754
2755
2756 static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
2757 {
2758 u32 stat;
2759 ns_dev *card;
2760 int left;
2761
2762 left = (int) *pos;
2763 card = (ns_dev *) dev->dev_data;
2764 stat = readl(card->membase + STAT);
2765 if (!left--)
2766 return sprintf(page, "Pool count min init max \n");
2767 if (!left--)
2768 return sprintf(page, "Small %5d %5d %5d %5d \n",
2769 ns_stat_sfbqc_get(stat), card->sbnr.min, card->sbnr.init,
2770 card->sbnr.max);
2771 if (!left--)
2772 return sprintf(page, "Large %5d %5d %5d %5d \n",
2773 ns_stat_lfbqc_get(stat), card->lbnr.min, card->lbnr.init,
2774 card->lbnr.max);
2775 if (!left--)
2776 return sprintf(page, "Huge %5d %5d %5d %5d \n", card->hbpool.count,
2777 card->hbnr.min, card->hbnr.init, card->hbnr.max);
2778 if (!left--)
2779 return sprintf(page, "Iovec %5d %5d %5d %5d \n", card->iovpool.count,
2780 card->iovnr.min, card->iovnr.init, card->iovnr.max);
2781 if (!left--)
2782 {
2783 int retval;
2784 retval = sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2785 card->intcnt = 0;
2786 return retval;
2787 }
2788 #if 0
2789 /* Dump 25.6 Mbps PHY registers */
2790 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2791 here just in case it's needed for debugging. */
2792 if (card->max_pcr == ATM_25_PCR && !left--)
2793 {
2794 u32 phy_regs[4];
2795 u32 i;
2796
2797 for (i = 0; i < 4; i++)
2798 {
2799 while (CMD_BUSY(card));
2800 writel(NS_CMD_READ_UTILITY | 0x00000200 | i, card->membase + CMD);
2801 while (CMD_BUSY(card));
2802 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2803 }
2804
2805 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2806 phy_regs[0], phy_regs[1], phy_regs[2], phy_regs[3]);
2807 }
2808 #endif /* 0 - Dump 25.6 Mbps PHY registers */
2809 #if 0
2810 /* Dump TST */
2811 if (left-- < NS_TST_NUM_ENTRIES)
2812 {
2813 if (card->tste2vc[left + 1] == NULL)
2814 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2815 else
2816 return sprintf(page, "%5d - %d %d \n", left + 1,
2817 card->tste2vc[left + 1]->tx_vcc->vpi,
2818 card->tste2vc[left + 1]->tx_vcc->vci);
2819 }
2820 #endif /* 0 */
2821 return 0;
2822 }
2823
2824
2825
2826 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
2827 {
2828 ns_dev *card;
2829 pool_levels pl;
2830 int btype;
2831 unsigned long flags;
2832
2833 card = dev->dev_data;
2834 switch (cmd)
2835 {
2836 case NS_GETPSTAT:
2837 if (get_user(pl.buftype, &((pool_levels *) arg)->buftype))
2838 return -EFAULT;
2839 switch (pl.buftype)
2840 {
2841 case NS_BUFTYPE_SMALL:
2842 pl.count = ns_stat_sfbqc_get(readl(card->membase + STAT));
2843 pl.level.min = card->sbnr.min;
2844 pl.level.init = card->sbnr.init;
2845 pl.level.max = card->sbnr.max;
2846 break;
2847
2848 case NS_BUFTYPE_LARGE:
2849 pl.count = ns_stat_lfbqc_get(readl(card->membase + STAT));
2850 pl.level.min = card->lbnr.min;
2851 pl.level.init = card->lbnr.init;
2852 pl.level.max = card->lbnr.max;
2853 break;
2854
2855 case NS_BUFTYPE_HUGE:
2856 pl.count = card->hbpool.count;
2857 pl.level.min = card->hbnr.min;
2858 pl.level.init = card->hbnr.init;
2859 pl.level.max = card->hbnr.max;
2860 break;
2861
2862 case NS_BUFTYPE_IOVEC:
2863 pl.count = card->iovpool.count;
2864 pl.level.min = card->iovnr.min;
2865 pl.level.init = card->iovnr.init;
2866 pl.level.max = card->iovnr.max;
2867 break;
2868
2869 default:
2870 return -ENOIOCTLCMD;
2871
2872 }
2873 if (!copy_to_user((pool_levels *) arg, &pl, sizeof(pl)))
2874 return (sizeof(pl));
2875 else
2876 return -EFAULT;
2877
2878 case NS_SETBUFLEV:
2879 if (!capable(CAP_NET_ADMIN))
2880 return -EPERM;
2881 if (copy_from_user(&pl, (pool_levels *) arg, sizeof(pl)))
2882 return -EFAULT;
2883 if (pl.level.min >= pl.level.init || pl.level.init >= pl.level.max)
2884 return -EINVAL;
2885 if (pl.level.min == 0)
2886 return -EINVAL;
2887 switch (pl.buftype)
2888 {
2889 case NS_BUFTYPE_SMALL:
2890 if (pl.level.max > TOP_SB)
2891 return -EINVAL;
2892 card->sbnr.min = pl.level.min;
2893 card->sbnr.init = pl.level.init;
2894 card->sbnr.max = pl.level.max;
2895 break;
2896
2897 case NS_BUFTYPE_LARGE:
2898 if (pl.level.max > TOP_LB)
2899 return -EINVAL;
2900 card->lbnr.min = pl.level.min;
2901 card->lbnr.init = pl.level.init;
2902 card->lbnr.max = pl.level.max;
2903 break;
2904
2905 case NS_BUFTYPE_HUGE:
2906 if (pl.level.max > TOP_HB)
2907 return -EINVAL;
2908 card->hbnr.min = pl.level.min;
2909 card->hbnr.init = pl.level.init;
2910 card->hbnr.max = pl.level.max;
2911 break;
2912
2913 case NS_BUFTYPE_IOVEC:
2914 if (pl.level.max > TOP_IOVB)
2915 return -EINVAL;
2916 card->iovnr.min = pl.level.min;
2917 card->iovnr.init = pl.level.init;
2918 card->iovnr.max = pl.level.max;
2919 break;
2920
2921 default:
2922 return -EINVAL;
2923
2924 }
2925 return 0;
2926
2927 case NS_ADJBUFLEV:
2928 if (!capable(CAP_NET_ADMIN))
2929 return -EPERM;
2930 btype = (int) arg; /* an int is the same size as a pointer */
2931 switch (btype)
2932 {
2933 case NS_BUFTYPE_SMALL:
2934 while (card->sbfqc < card->sbnr.init)
2935 {
2936 struct sk_buff *sb;
2937
2938 sb = alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2939 if (sb == NULL)
2940 return -ENOMEM;
2941 skb_queue_tail(&card->sbpool.queue, sb);
2942 skb_reserve(sb, NS_AAL0_HEADER);
2943 push_rxbufs(card, BUF_SM, (u32) sb, (u32) virt_to_bus(sb->data), 0, 0);
2944 }
2945 break;
2946
2947 case NS_BUFTYPE_LARGE:
2948 while (card->lbfqc < card->lbnr.init)
2949 {
2950 struct sk_buff *lb;
2951
2952 lb = alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2953 if (lb == NULL)
2954 return -ENOMEM;
2955 skb_queue_tail(&card->lbpool.queue, lb);
2956 skb_reserve(lb, NS_SMBUFSIZE);
2957 push_rxbufs(card, BUF_LG, (u32) lb, (u32) virt_to_bus(lb->data), 0, 0);
2958 }
2959 break;
2960
2961 case NS_BUFTYPE_HUGE:
2962 while (card->hbpool.count > card->hbnr.init)
2963 {
2964 struct sk_buff *hb;
2965
2966 ns_grab_int_lock(card, flags);
2967 hb = skb_dequeue(&card->hbpool.queue);
2968 card->hbpool.count--;
2969 spin_unlock_irqrestore(&card->int_lock, flags);
2970 if (hb == NULL)
2971 printk("nicstar%d: huge buffer count inconsistent.\n",
2972 card->index);
2973 else
2974 dev_kfree_skb_any(hb);
2975
2976 }
2977 while (card->hbpool.count < card->hbnr.init)
2978 {
2979 struct sk_buff *hb;
2980
2981 hb = alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2982 if (hb == NULL)
2983 return -ENOMEM;
2984 ns_grab_int_lock(card, flags);
2985 skb_queue_tail(&card->hbpool.queue, hb);
2986 card->hbpool.count++;
2987 spin_unlock_irqrestore(&card->int_lock, flags);
2988 }
2989 break;
2990
2991 case NS_BUFTYPE_IOVEC:
2992 while (card->iovpool.count > card->iovnr.init)
2993 {
2994 struct sk_buff *iovb;
2995
2996 ns_grab_int_lock(card, flags);
2997 iovb = skb_dequeue(&card->iovpool.queue);
2998 card->iovpool.count--;
2999 spin_unlock_irqrestore(&card->int_lock, flags);
3000 if (iovb == NULL)
3001 printk("nicstar%d: iovec buffer count inconsistent.\n",
3002 card->index);
3003 else
3004 dev_kfree_skb_any(iovb);
3005
3006 }
3007 while (card->iovpool.count < card->iovnr.init)
3008 {
3009 struct sk_buff *iovb;
3010
3011 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
3012 if (iovb == NULL)
3013 return -ENOMEM;
3014 ns_grab_int_lock(card, flags);
3015 skb_queue_tail(&card->iovpool.queue, iovb);
3016 card->iovpool.count++;
3017 spin_unlock_irqrestore(&card->int_lock, flags);
3018 }
3019 break;
3020
3021 default:
3022 return -EINVAL;
3023
3024 }
3025 return 0;
3026
3027 default:
3028 if (dev->phy && dev->phy->ioctl) {
3029 return dev->phy->ioctl(dev, cmd, arg);
3030 }
3031 else {
3032 printk("nicstar%d: %s == NULL \n", card->index,
3033 dev->phy ? "dev->phy->ioctl" : "dev->phy");
3034 return -ENOIOCTLCMD;
3035 }
3036 }
3037 }
3038
3039
3040
3041 static void which_list(ns_dev *card, struct sk_buff *skb)
3042 {
3043 printk("It's a %s buffer.\n", skb->list == &card->sbpool.queue ?
3044 "small" : skb->list == &card->lbpool.queue ? "large" :
3045 skb->list == &card->hbpool.queue ? "huge" :
3046 skb->list == &card->iovpool.queue ? "iovec" : "unknown");
3047 }
3048
3049
3050
3051 static void ns_poll(unsigned long arg)
3052 {
3053 int i;
3054 ns_dev *card;
3055 unsigned long flags;
3056 u32 stat_r, stat_w;
3057
3058 PRINTK("nicstar: Entering ns_poll().\n");
3059 for (i = 0; i < num_cards; i++)
3060 {
3061 card = cards[i];
3062 if (spin_is_locked(&card->int_lock)) {
3063 /* Probably it isn't worth spinning */
3064 continue;
3065 }
3066 ns_grab_int_lock(card, flags);
3067
3068 stat_w = 0;
3069 stat_r = readl(card->membase + STAT);
3070 if (stat_r & NS_STAT_TSIF)
3071 stat_w |= NS_STAT_TSIF;
3072 if (stat_r & NS_STAT_EOPDU)
3073 stat_w |= NS_STAT_EOPDU;
3074
3075 process_tsq(card);
3076 process_rsq(card);
3077
3078 writel(stat_w, card->membase + STAT);
3079 spin_unlock_irqrestore(&card->int_lock, flags);
3080 }
3081 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
3082 PRINTK("nicstar: Leaving ns_poll().\n");
3083 }
3084
3085
3086
3087 static int ns_parse_mac(char *mac, unsigned char *esi)
3088 {
3089 int i, j;
3090 short byte1, byte0;
3091
3092 if (mac == NULL || esi == NULL)
3093 return -1;
3094 j = 0;
3095 for (i = 0; i < 6; i++)
3096 {
3097 if ((byte1 = ns_h2i(mac[j++])) < 0)
3098 return -1;
3099 if ((byte0 = ns_h2i(mac[j++])) < 0)
3100 return -1;
3101 esi[i] = (unsigned char) (byte1 * 16 + byte0);
3102 if (i < 5)
3103 {
3104 if (mac[j++] != ':')
3105 return -1;
3106 }
3107 }
3108 return 0;
3109 }
3110
3111
3112
3113 static short ns_h2i(char c)
3114 {
3115 if (c >= '0' && c <= '9')
3116 return (short) (c - '0');
3117 if (c >= 'A' && c <= 'F')
3118 return (short) (c - 'A' + 10);
3119 if (c >= 'a' && c <= 'f')
3120 return (short) (c - 'a' + 10);
3121 return -1;
3122 }
3123
3124
3125
3126 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
3127 unsigned long addr)
3128 {
3129 ns_dev *card;
3130 unsigned long flags;
3131
3132 card = dev->dev_data;
3133 ns_grab_res_lock(card, flags);
3134 while(CMD_BUSY(card));
3135 writel((unsigned long) value, card->membase + DR0);
3136 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
3137 card->membase + CMD);
3138 spin_unlock_irqrestore(&card->res_lock, flags);
3139 }
3140
3141
3142
3143 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
3144 {
3145 ns_dev *card;
3146 unsigned long flags;
3147 unsigned long data;
3148
3149 card = dev->dev_data;
3150 ns_grab_res_lock(card, flags);
3151 while(CMD_BUSY(card));
3152 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
3153 card->membase + CMD);
3154 while(CMD_BUSY(card));
3155 data = readl(card->membase + DR0) & 0x000000FF;
3156 spin_unlock_irqrestore(&card->res_lock, flags);
3157 return (unsigned char) data;
3158 }
3159