File: /usr/src/linux/drivers/block/cpqarray.c
1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to arrays@compaq.com
20 *
21 */
22 #include <linux/config.h> /* CONFIG_PROC_FS */
23 #include <linux/module.h>
24 #include <linux/version.h>
25 #include <linux/types.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/major.h>
31 #include <linux/fs.h>
32 #include <linux/blkpg.h>
33 #include <linux/timer.h>
34 #include <linux/proc_fs.h>
35 #include <linux/init.h>
36 #include <linux/hdreg.h>
37 #include <linux/spinlock.h>
38 #include <asm/uaccess.h>
39 #include <asm/io.h>
40
41
42 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
43
44 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.4.5)"
45 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,4,5)
46
47 /* Embedded module documentation macros - see modules.h */
48 /* Original author Chris Frantz - Compaq Computer Corporation */
49 MODULE_AUTHOR("Compaq Computer Corporation");
50 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers");
51 MODULE_LICENSE("GPL");
52
53 #define MAJOR_NR COMPAQ_SMART2_MAJOR
54 #include <linux/blk.h>
55 #include <linux/blkdev.h>
56 #include <linux/genhd.h>
57
58 #include "cpqarray.h"
59 #include "ida_cmd.h"
60 #include "smart1,2.h"
61 #include "ida_ioctl.h"
62
63 #define READ_AHEAD 128
64 #define NR_CMDS 128 /* This could probably go as high as ~400 */
65
66 #define MAX_CTLR 8
67 #define CTLR_SHIFT 8
68
69 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
70
71 static int nr_ctlr;
72 static ctlr_info_t *hba[MAX_CTLR];
73
74 static int eisa[8];
75
76 #define NR_PRODUCTS (sizeof(products)/sizeof(struct board_type))
77
78 /* board_id = Subsystem Device ID & Vendor ID
79 * product = Marketing Name for the board
80 * access = Address of the struct of function pointers
81 */
82 static struct board_type products[] = {
83 { 0x0040110E, "IDA", &smart1_access },
84 { 0x0140110E, "IDA-2", &smart1_access },
85 { 0x1040110E, "IAES", &smart1_access },
86 { 0x2040110E, "SMART", &smart1_access },
87 { 0x3040110E, "SMART-2/E", &smart2e_access },
88 { 0x40300E11, "SMART-2/P", &smart2_access },
89 { 0x40310E11, "SMART-2SL", &smart2_access },
90 { 0x40320E11, "Smart Array 3200", &smart2_access },
91 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
92 { 0x40340E11, "Smart Array 221", &smart2_access },
93 { 0x40400E11, "Integrated Array", &smart4_access },
94 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
95 { 0x40500E11, "Smart Array 4200", &smart4_access },
96 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
97 { 0x40580E11, "Smart Array 431", &smart4_access },
98 };
99
100 static struct hd_struct * ida;
101 static int * ida_sizes;
102 static int * ida_blocksizes;
103 static int * ida_hardsizes;
104 static struct gendisk ida_gendisk[MAX_CTLR];
105
106 static struct proc_dir_entry *proc_array;
107
108 /* Debug... */
109 #define DBG(s) do { s } while(0)
110 /* Debug (general info)... */
111 #define DBGINFO(s) do { } while(0)
112 /* Debug Paranoid... */
113 #define DBGP(s) do { } while(0)
114 /* Debug Extra Paranoid... */
115 #define DBGPX(s) do { } while(0)
116
117 int cpqarray_init(void);
118 static int cpqarray_pci_detect(void);
119 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
120 static void *remap_pci_mem(ulong base, ulong size);
121 static int cpqarray_eisa_detect(void);
122 static int pollcomplete(int ctlr);
123 static void getgeometry(int ctlr);
124 static void start_fwbk(int ctlr);
125
126 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
127 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
128
129 static int sendcmd(
130 __u8 cmd,
131 int ctlr,
132 void *buff,
133 size_t size,
134 unsigned int blk,
135 unsigned int blkcnt,
136 unsigned int log_unit );
137
138 static int ida_open(struct inode *inode, struct file *filep);
139 static int ida_release(struct inode *inode, struct file *filep);
140 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg);
141 static int ida_ctlr_ioctl(int ctlr, int dsk, ida_ioctl_t *io);
142
143 static void do_ida_request(request_queue_t *q);
144 static void start_io(ctlr_info_t *h);
145
146 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
147 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
148 static inline void complete_buffers(struct buffer_head *bh, int ok);
149 static inline void complete_command(cmdlist_t *cmd, int timeout);
150
151 static void do_ida_intr(int irq, void *dev_id, struct pt_regs * regs);
152 static void ida_timer(unsigned long tdata);
153 static int frevalidate_logvol(kdev_t dev);
154 static int revalidate_logvol(kdev_t dev, int maxusage);
155 static int revalidate_allvol(kdev_t dev);
156
157 #ifdef CONFIG_PROC_FS
158 static void ida_procinit(int i);
159 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
160 #else
161 static void ida_procinit(int i) {}
162 static int ida_proc_get_info(char *buffer, char **start, off_t offset,
163 int length, int *eof, void *data) { return 0;}
164 #endif
165
166 static void ida_geninit(int ctlr)
167 {
168 int i,j;
169 drv_info_t *drv;
170
171 for(i=0; i<NWD; i++) {
172 drv = &hba[ctlr]->drv[i];
173 if (!drv->nr_blks)
174 continue;
175 ida[(ctlr<<CTLR_SHIFT) + (i<<NWD_SHIFT)].nr_sects =
176 ida_sizes[(ctlr<<CTLR_SHIFT) + (i<<NWD_SHIFT)] =
177 drv->nr_blks;
178
179 for(j=0; j<16; j++) {
180 ida_blocksizes[(ctlr<<CTLR_SHIFT) + (i<<NWD_SHIFT)+j] =
181 1024;
182 ida_hardsizes[(ctlr<<CTLR_SHIFT) + (i<<NWD_SHIFT)+j] =
183 drv->blk_size;
184 }
185 ida_gendisk[ctlr].nr_real++;
186 }
187
188 }
189
190 static struct block_device_operations ida_fops = {
191 open: ida_open,
192 release: ida_release,
193 ioctl: ida_ioctl,
194 revalidate: frevalidate_logvol,
195 };
196
197
198 #ifdef CONFIG_PROC_FS
199
200 /*
201 * Get us a file in /proc/array that says something about each controller.
202 * Create /proc/array if it doesn't exist yet.
203 */
204 static void __init ida_procinit(int i)
205 {
206 if (proc_array == NULL) {
207 proc_array = proc_mkdir("cpqarray", proc_root_driver);
208 if (!proc_array) return;
209 }
210
211 create_proc_read_entry(hba[i]->devname, 0, proc_array,
212 ida_proc_get_info, hba[i]);
213 }
214
215 /*
216 * Report information about this controller.
217 */
218 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
219 {
220 off_t pos = 0;
221 off_t len = 0;
222 int size, i, ctlr;
223 ctlr_info_t *h = (ctlr_info_t*)data;
224 drv_info_t *drv;
225 #ifdef CPQ_PROC_PRINT_QUEUES
226 cmdlist_t *c;
227 #endif
228
229 ctlr = h->ctlr;
230 size = sprintf(buffer, "%s: Compaq %s Controller\n"
231 " Board ID: 0x%08lx\n"
232 " Firmware Revision: %c%c%c%c\n"
233 " Controller Sig: 0x%08lx\n"
234 " Memory Address: 0x%08lx\n"
235 " I/O Port: 0x%04x\n"
236 " IRQ: %d\n"
237 " Logical drives: %d\n"
238 " Physical drives: %d\n\n"
239 " Current Q depth: %d\n"
240 " Max Q depth since init: %d\n\n",
241 h->devname,
242 h->product_name,
243 (unsigned long)h->board_id,
244 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
245 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
246 (unsigned int) h->ioaddr, (unsigned int)h->intr,
247 h->log_drives, h->phys_drives,
248 h->Qdepth, h->maxQsinceinit);
249
250 pos += size; len += size;
251
252 size = sprintf(buffer+len, "Logical Drive Info:\n");
253 pos += size; len += size;
254
255 for(i=0; i<h->log_drives; i++) {
256 drv = &h->drv[i];
257 size = sprintf(buffer+len, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
258 ctlr, i, drv->blk_size, drv->nr_blks);
259 pos += size; len += size;
260 }
261
262 #ifdef CPQ_PROC_PRINT_QUEUES
263 size = sprintf(buffer+len, "\nCurrent Queues:\n");
264 pos += size; len += size;
265
266 c = h->reqQ;
267 size = sprintf(buffer+len, "reqQ = %p", c); pos += size; len += size;
268 if (c) c=c->next;
269 while(c && c != h->reqQ) {
270 size = sprintf(buffer+len, "->%p", c);
271 pos += size; len += size;
272 c=c->next;
273 }
274
275 c = h->cmpQ;
276 size = sprintf(buffer+len, "\ncmpQ = %p", c); pos += size; len += size;
277 if (c) c=c->next;
278 while(c && c != h->cmpQ) {
279 size = sprintf(buffer+len, "->%p", c);
280 pos += size; len += size;
281 c=c->next;
282 }
283
284 size = sprintf(buffer+len, "\n"); pos += size; len += size;
285 #endif
286 size = sprintf(buffer+len, "nr_allocs = %d\nnr_frees = %d\n",
287 h->nr_allocs, h->nr_frees);
288 pos += size; len += size;
289
290 *eof = 1;
291 *start = buffer+offset;
292 len -= offset;
293 if (len>length)
294 len = length;
295 return len;
296 }
297 #endif /* CONFIG_PROC_FS */
298
299 #ifdef MODULE
300
301 MODULE_PARM(eisa, "1-8i");
302 EXPORT_NO_SYMBOLS;
303
304 /* This is a bit of a hack... */
305 int __init init_module(void)
306 {
307 if (cpqarray_init() == 0) /* all the block dev numbers already used */
308 return -EIO; /* or no controllers were found */
309 return 0;
310 }
311
312 void cleanup_module(void)
313 {
314 int i;
315 char buff[4];
316
317 for(i=0; i<nr_ctlr; i++) {
318
319 /* sendcmd will turn off interrupt, and send the flush...
320 * To write all data in the battery backed cache to disks
321 * no data returned, but don't want to send NULL to sendcmd */
322 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
323 {
324 printk(KERN_WARNING "Unable to flush cache on "
325 "controller %d\n", i);
326 }
327 free_irq(hba[i]->intr, hba[i]);
328 iounmap(hba[i]->vaddr);
329 unregister_blkdev(MAJOR_NR+i, hba[i]->devname);
330 del_timer(&hba[i]->timer);
331 blk_cleanup_queue(BLK_DEFAULT_QUEUE(MAJOR_NR + i));
332 remove_proc_entry(hba[i]->devname, proc_array);
333 pci_free_consistent(hba[i]->pci_dev,
334 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
335 hba[i]->cmd_pool_dhandle);
336 kfree(hba[i]->cmd_pool_bits);
337
338 del_gendisk(&ida_gendisk[i]);
339 }
340 remove_proc_entry("cpqarray", proc_root_driver);
341 kfree(ida);
342 kfree(ida_sizes);
343 kfree(ida_hardsizes);
344 kfree(ida_blocksizes);
345 }
346 #endif /* MODULE */
347
348 static inline int cpq_new_segment(request_queue_t *q, struct request *rq,
349 int max_segments)
350 {
351 if (rq->nr_segments < SG_MAX) {
352 rq->nr_segments++;
353 return 1;
354 }
355 return 0;
356 }
357
358 static int cpq_back_merge_fn(request_queue_t *q, struct request *rq,
359 struct buffer_head *bh, int max_segments)
360 {
361 if (rq->bhtail->b_data + rq->bhtail->b_size == bh->b_data)
362 return 1;
363 return cpq_new_segment(q, rq, max_segments);
364 }
365
366 static int cpq_front_merge_fn(request_queue_t *q, struct request *rq,
367 struct buffer_head *bh, int max_segments)
368 {
369 if (bh->b_data + bh->b_size == rq->bh->b_data)
370 return 1;
371 return cpq_new_segment(q, rq, max_segments);
372 }
373
374 static int cpq_merge_requests_fn(request_queue_t *q, struct request *rq,
375 struct request *nxt, int max_segments)
376 {
377 int total_segments = rq->nr_segments + nxt->nr_segments;
378
379 if (rq->bhtail->b_data + rq->bhtail->b_size == nxt->bh->b_data)
380 total_segments--;
381
382 if (total_segments > SG_MAX)
383 return 0;
384
385 rq->nr_segments = total_segments;
386 return 1;
387 }
388
389 /*
390 * This is it. Find all the controllers and register them. I really hate
391 * stealing all these major device numbers.
392 * returns the number of block devices registered.
393 */
394 int __init cpqarray_init(void)
395 {
396 request_queue_t *q;
397 int i,j;
398 int num_cntlrs_reg = 0;
399
400 /* detect controllers */
401 cpqarray_pci_detect();
402 cpqarray_eisa_detect();
403
404 if (nr_ctlr == 0)
405 return(num_cntlrs_reg);
406
407 printk(DRIVER_NAME "\n");
408 printk("Found %d controller(s)\n", nr_ctlr);
409
410 /* allocate space for disk structs */
411 ida = kmalloc(sizeof(struct hd_struct)*nr_ctlr*NWD*16, GFP_KERNEL);
412 if(ida==NULL)
413 {
414 printk( KERN_ERR "cpqarray: out of memory");
415 return(num_cntlrs_reg);
416 }
417
418 ida_sizes = kmalloc(sizeof(int)*nr_ctlr*NWD*16, GFP_KERNEL);
419 if(ida_sizes==NULL)
420 {
421 kfree(ida);
422 printk( KERN_ERR "cpqarray: out of memory");
423 return(num_cntlrs_reg);
424 }
425
426 ida_blocksizes = kmalloc(sizeof(int)*nr_ctlr*NWD*16, GFP_KERNEL);
427 if(ida_blocksizes==NULL)
428 {
429 kfree(ida);
430 kfree(ida_sizes);
431 printk( KERN_ERR "cpqarray: out of memory");
432 return(num_cntlrs_reg);
433 }
434
435 ida_hardsizes = kmalloc(sizeof(int)*nr_ctlr*NWD*16, GFP_KERNEL);
436 if(ida_hardsizes==NULL)
437 {
438 kfree(ida);
439 kfree(ida_sizes);
440 kfree(ida_blocksizes);
441 printk( KERN_ERR "cpqarray: out of memory");
442 return(num_cntlrs_reg);
443 }
444
445 memset(ida, 0, sizeof(struct hd_struct)*nr_ctlr*NWD*16);
446 memset(ida_sizes, 0, sizeof(int)*nr_ctlr*NWD*16);
447 memset(ida_blocksizes, 0, sizeof(int)*nr_ctlr*NWD*16);
448 memset(ida_hardsizes, 0, sizeof(int)*nr_ctlr*NWD*16);
449 memset(ida_gendisk, 0, sizeof(struct gendisk)*MAX_CTLR);
450
451 /*
452 * register block devices
453 * Find disks and fill in structs
454 * Get an interrupt, set the Q depth and get into /proc
455 */
456 for(i=0; i< nr_ctlr; i++) {
457 /* If this successful it should insure that we are the only */
458 /* instance of the driver */
459 if (register_blkdev(MAJOR_NR+i, hba[i]->devname, &ida_fops)) {
460 printk(KERN_ERR "cpqarray: Unable to get major number %d for ida\n",
461 MAJOR_NR+i);
462 continue;
463 }
464
465
466 hba[i]->access.set_intr_mask(hba[i], 0);
467 if (request_irq(hba[i]->intr, do_ida_intr,
468 SA_INTERRUPT|SA_SHIRQ, hba[i]->devname, hba[i])) {
469
470 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
471 hba[i]->intr, hba[i]->devname);
472 unregister_blkdev(MAJOR_NR+i, hba[i]->devname);
473 continue;
474 }
475 num_cntlrs_reg++;
476 hba[i]->cmd_pool = (cmdlist_t *)pci_alloc_consistent(
477 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
478 &(hba[i]->cmd_pool_dhandle));
479 hba[i]->cmd_pool_bits = (__u32*)kmalloc(
480 ((NR_CMDS+31)/32)*sizeof(__u32), GFP_KERNEL);
481
482 if(hba[i]->cmd_pool_bits == NULL || hba[i]->cmd_pool == NULL)
483 {
484 nr_ctlr = i;
485 if(hba[i]->cmd_pool_bits)
486 kfree(hba[i]->cmd_pool_bits);
487 if(hba[i]->cmd_pool)
488 pci_free_consistent(hba[i]->pci_dev,
489 NR_CMDS * sizeof(cmdlist_t),
490 hba[i]->cmd_pool,
491 hba[i]->cmd_pool_dhandle);
492 free_irq(hba[i]->intr, hba[i]);
493 unregister_blkdev(MAJOR_NR+i, hba[i]->devname);
494 num_cntlrs_reg--;
495 printk( KERN_ERR "cpqarray: out of memory");
496
497 /* If num_cntlrs_reg == 0, no controllers worked.
498 * init_module will fail, so clean up global
499 * memory that clean_module would do.
500 */
501
502 if (num_cntlrs_reg == 0)
503 {
504 kfree(ida);
505 kfree(ida_sizes);
506 kfree(ida_hardsizes);
507 kfree(ida_blocksizes);
508 }
509 return(num_cntlrs_reg);
510
511 }
512 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
513 memset(hba[i]->cmd_pool_bits, 0, ((NR_CMDS+31)/32)*sizeof(__u32));
514 printk(KERN_INFO "cpqarray: Finding drives on %s",
515 hba[i]->devname);
516 getgeometry(i);
517 start_fwbk(i);
518
519 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
520
521 ida_procinit(i);
522
523 q = BLK_DEFAULT_QUEUE(MAJOR_NR + i);
524 q->queuedata = hba[i];
525 blk_init_queue(q, do_ida_request);
526 blk_queue_headactive(q, 0);
527 blksize_size[MAJOR_NR+i] = ida_blocksizes + (i*256);
528 hardsect_size[MAJOR_NR+i] = ida_hardsizes + (i*256);
529 read_ahead[MAJOR_NR+i] = READ_AHEAD;
530
531 q->back_merge_fn = cpq_back_merge_fn;
532 q->front_merge_fn = cpq_front_merge_fn;
533 q->merge_requests_fn = cpq_merge_requests_fn;
534
535 ida_gendisk[i].major = MAJOR_NR + i;
536 ida_gendisk[i].major_name = "ida";
537 ida_gendisk[i].minor_shift = NWD_SHIFT;
538 ida_gendisk[i].max_p = 16;
539 ida_gendisk[i].part = ida + (i*256);
540 ida_gendisk[i].sizes = ida_sizes + (i*256);
541 ida_gendisk[i].nr_real = 0;
542
543 /* Get on the disk list */
544 add_gendisk(&ida_gendisk[i]);
545
546 init_timer(&hba[i]->timer);
547 hba[i]->timer.expires = jiffies + IDA_TIMER;
548 hba[i]->timer.data = (unsigned long)hba[i];
549 hba[i]->timer.function = ida_timer;
550 add_timer(&hba[i]->timer);
551
552 ida_geninit(i);
553 for(j=0; j<NWD; j++)
554 register_disk(&ida_gendisk[i],
555 MKDEV(MAJOR_NR+i,j<<4),
556 16, &ida_fops, hba[i]->drv[j].nr_blks);
557
558 }
559 /* done ! */
560 return(num_cntlrs_reg);
561 }
562
563 /*
564 * Find the controller and initialize it
565 * Cannot use the class code to search, because older array controllers use
566 * 0x018000 and new ones use 0x010400. So I might as well search for each
567 * each device IDs, being there are only going to be three of them.
568 */
569 static int cpqarray_pci_detect(void)
570 {
571 struct pci_dev *pdev;
572
573 #define IDA_BOARD_TYPES 3
574 static int ida_vendor_id[IDA_BOARD_TYPES] = { PCI_VENDOR_ID_DEC,
575 PCI_VENDOR_ID_NCR, PCI_VENDOR_ID_COMPAQ };
576 static int ida_device_id[IDA_BOARD_TYPES] = { PCI_DEVICE_ID_COMPAQ_42XX, PCI_DEVICE_ID_NCR_53C1510, PCI_DEVICE_ID_COMPAQ_SMART2P };
577 int brdtype;
578
579 /* search for all PCI board types that could be for this driver */
580 for(brdtype=0; brdtype<IDA_BOARD_TYPES; brdtype++)
581 {
582 pdev = pci_find_device(ida_vendor_id[brdtype],
583 ida_device_id[brdtype], NULL);
584 while (pdev) {
585 printk(KERN_DEBUG "cpqarray: Device 0x%x has"
586 " been found at bus %d dev %d func %d\n",
587 ida_vendor_id[brdtype],
588 pdev->bus->number, PCI_SLOT(pdev->devfn),
589 PCI_FUNC(pdev->devfn));
590 if (nr_ctlr == 8) {
591 printk(KERN_WARNING "cpqarray: This driver"
592 " supports a maximum of 8 controllers.\n");
593 break;
594 }
595
596 /* if it is a PCI_DEVICE_ID_NCR_53C1510, make sure it's the Compaq version of the chip */
597
598 if (ida_device_id[brdtype] == PCI_DEVICE_ID_NCR_53C1510) {
599 unsigned short subvendor=pdev->subsystem_vendor;
600 if(subvendor != PCI_VENDOR_ID_COMPAQ)
601 {
602 printk(KERN_DEBUG
603 "cpqarray: not a Compaq integrated array controller\n");
604 continue;
605 }
606 }
607
608 hba[nr_ctlr] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL); if(hba[nr_ctlr]==NULL)
609 {
610 printk(KERN_ERR "cpqarray: out of memory.\n");
611 continue;
612 }
613 memset(hba[nr_ctlr], 0, sizeof(ctlr_info_t));
614 if (cpqarray_pci_init(hba[nr_ctlr], pdev) != 0)
615 {
616 kfree(hba[nr_ctlr]);
617 continue;
618 }
619 sprintf(hba[nr_ctlr]->devname, "ida%d", nr_ctlr);
620 hba[nr_ctlr]->ctlr = nr_ctlr;
621 nr_ctlr++;
622
623 pdev = pci_find_device(ida_vendor_id[brdtype],
624 ida_device_id[brdtype], pdev);
625 }
626 }
627
628 return nr_ctlr;
629 }
630
631 /*
632 * Find the IO address of the controller, its IRQ and so forth. Fill
633 * in some basic stuff into the ctlr_info_t structure.
634 */
635 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
636 {
637 ushort vendor_id, device_id, command;
638 unchar cache_line_size, latency_timer;
639 unchar irq, revision;
640 unsigned long addr[6];
641 __u32 board_id;
642
643 int i;
644
645 c->pci_dev = pdev;
646 vendor_id = pdev->vendor;
647 device_id = pdev->device;
648 irq = pdev->irq;
649
650 for(i=0; i<6; i++)
651 addr[i] = pci_resource_start(pdev, i);
652
653 if (pci_enable_device(pdev))
654 {
655 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
656 return -1;
657 }
658 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
659 {
660 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
661 return -1;
662 }
663
664 pci_read_config_word(pdev, PCI_COMMAND, &command);
665 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
666 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
667 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
668
669 pci_read_config_dword(pdev, 0x2c, &board_id);
670
671 DBGINFO(
672 printk("vendor_id = %x\n", vendor_id);
673 printk("device_id = %x\n", device_id);
674 printk("command = %x\n", command);
675 for(i=0; i<6; i++)
676 printk("addr[%d] = %lx\n", i, addr[i]);
677 printk("revision = %x\n", revision);
678 printk("irq = %x\n", irq);
679 printk("cache_line_size = %x\n", cache_line_size);
680 printk("latency_timer = %x\n", latency_timer);
681 printk("board_id = %x\n", board_id);
682 );
683
684 c->intr = irq;
685 c->ioaddr = addr[0];
686
687 c->paddr = 0;
688 for(i=0; i<6; i++)
689 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
690 c->paddr = pci_resource_start (pdev, i);
691 break;
692 }
693 if (!c->paddr)
694 return -1;
695 c->vaddr = remap_pci_mem(c->paddr, 128);
696 if (!c->vaddr)
697 return -1;
698 c->board_id = board_id;
699
700 for(i=0; i<NR_PRODUCTS; i++) {
701 if (board_id == products[i].board_id) {
702 c->product_name = products[i].product_name;
703 c->access = *(products[i].access);
704 break;
705 }
706 }
707 if (i == NR_PRODUCTS) {
708 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
709 " to access the SMART Array controller %08lx\n",
710 (unsigned long)board_id);
711 return -1;
712 }
713
714 return 0;
715 }
716
717 /*
718 * Map (physical) PCI mem into (virtual) kernel space
719 */
720 static void *remap_pci_mem(ulong base, ulong size)
721 {
722 ulong page_base = ((ulong) base) & PAGE_MASK;
723 ulong page_offs = ((ulong) base) - page_base;
724 void *page_remapped = ioremap(page_base, page_offs+size);
725
726 return (page_remapped ? (page_remapped + page_offs) : NULL);
727 }
728
729 #ifndef MODULE
730 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,13)
731 /*
732 * Config string is a comma seperated set of i/o addresses of EISA cards.
733 */
734 static int cpqarray_setup(char *str)
735 {
736 int i, ints[9];
737
738 (void)get_options(str, ARRAY_SIZE(ints), ints);
739
740 for(i=0; i<ints[0] && i<8; i++)
741 eisa[i] = ints[i+1];
742 return 1;
743 }
744
745 __setup("smart2=", cpqarray_setup);
746
747 #else
748
749 /*
750 * Copy the contents of the ints[] array passed to us by init.
751 */
752 void cpqarray_setup(char *str, int *ints)
753 {
754 int i;
755 for(i=0; i<ints[0] && i<8; i++)
756 eisa[i] = ints[i+1];
757 }
758 #endif
759 #endif
760
761 /*
762 * Find an EISA controller's signature. Set up an hba if we find it.
763 */
764 static int cpqarray_eisa_detect(void)
765 {
766 int i=0, j;
767 __u32 board_id;
768 int intr;
769
770 while(i<8 && eisa[i]) {
771 if (nr_ctlr == 8) {
772 printk(KERN_WARNING "cpqarray: This driver supports"
773 " a maximum of 8 controllers.\n");
774 break;
775 }
776 board_id = inl(eisa[i]+0xC80);
777 for(j=0; j < NR_PRODUCTS; j++)
778 if (board_id == products[j].board_id)
779 break;
780
781 if (j == NR_PRODUCTS) {
782 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
783 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
784 continue;
785 }
786 hba[nr_ctlr] = (ctlr_info_t *) kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
787 if(hba[nr_ctlr]==NULL)
788 {
789 printk(KERN_ERR "cpqarray: out of memory.\n");
790 continue;
791 }
792 memset(hba[nr_ctlr], 0, sizeof(ctlr_info_t));
793 hba[nr_ctlr]->ioaddr = eisa[i];
794
795 /*
796 * Read the config register to find our interrupt
797 */
798 intr = inb(eisa[i]+0xCC0) >> 4;
799 if (intr & 1) intr = 11;
800 else if (intr & 2) intr = 10;
801 else if (intr & 4) intr = 14;
802 else if (intr & 8) intr = 15;
803
804 hba[nr_ctlr]->intr = intr;
805 sprintf(hba[nr_ctlr]->devname, "ida%d", nr_ctlr);
806 hba[nr_ctlr]->product_name = products[j].product_name;
807 hba[nr_ctlr]->access = *(products[j].access);
808 hba[nr_ctlr]->ctlr = nr_ctlr;
809 hba[nr_ctlr]->board_id = board_id;
810 hba[nr_ctlr]->pci_dev = NULL; /* not PCI */
811
812 DBGINFO(
813 printk("i = %d, j = %d\n", i, j);
814 printk("irq = %x\n", intr);
815 printk("product name = %s\n", products[j].product_name);
816 printk("board_id = %x\n", board_id);
817 );
818
819 nr_ctlr++;
820 i++;
821 }
822
823 return nr_ctlr;
824 }
825
826
827 /*
828 * Open. Make sure the device is really there.
829 */
830 static int ida_open(struct inode *inode, struct file *filep)
831 {
832 int ctlr = MAJOR(inode->i_rdev) - MAJOR_NR;
833 int dsk = MINOR(inode->i_rdev) >> NWD_SHIFT;
834
835 DBGINFO(printk("ida_open %x (%x:%x)\n", inode->i_rdev, ctlr, dsk) );
836 if (ctlr > MAX_CTLR || hba[ctlr] == NULL)
837 return -ENXIO;
838
839 if (!suser() && ida_sizes[(ctlr << CTLR_SHIFT) +
840 MINOR(inode->i_rdev)] == 0)
841 return -ENXIO;
842
843 /*
844 * Root is allowed to open raw volume zero even if its not configured
845 * so array config can still work. I don't think I really like this,
846 * but I'm already using way to many device nodes to claim another one
847 * for "raw controller".
848 */
849 if (suser()
850 && ida_sizes[(ctlr << CTLR_SHIFT) + MINOR(inode->i_rdev)] == 0
851 && MINOR(inode->i_rdev) != 0)
852 return -ENXIO;
853
854 hba[ctlr]->drv[dsk].usage_count++;
855 hba[ctlr]->usage_count++;
856 MOD_INC_USE_COUNT;
857 return 0;
858 }
859
860 /*
861 * Close. Sync first.
862 */
863 static int ida_release(struct inode *inode, struct file *filep)
864 {
865 int ctlr = MAJOR(inode->i_rdev) - MAJOR_NR;
866 int dsk = MINOR(inode->i_rdev) >> NWD_SHIFT;
867
868 DBGINFO(printk("ida_release %x (%x:%x)\n", inode->i_rdev, ctlr, dsk) );
869
870 hba[ctlr]->drv[dsk].usage_count--;
871 hba[ctlr]->usage_count--;
872 MOD_DEC_USE_COUNT;
873 return 0;
874 }
875
876 /*
877 * Enqueuing and dequeuing functions for cmdlists.
878 */
879 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
880 {
881 if (*Qptr == NULL) {
882 *Qptr = c;
883 c->next = c->prev = c;
884 } else {
885 c->prev = (*Qptr)->prev;
886 c->next = (*Qptr);
887 (*Qptr)->prev->next = c;
888 (*Qptr)->prev = c;
889 }
890 }
891
892 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
893 {
894 if (c && c->next != c) {
895 if (*Qptr == c) *Qptr = c->next;
896 c->prev->next = c->next;
897 c->next->prev = c->prev;
898 } else {
899 *Qptr = NULL;
900 }
901 return c;
902 }
903
904 /*
905 * Get a request and submit it to the controller.
906 * This routine needs to grab all the requests it possibly can from the
907 * req Q and submit them. Interrupts are off (and need to be off) when you
908 * are in here (either via the dummy do_ida_request functions or by being
909 * called from the interrupt handler
910 */
911 static void do_ida_request(request_queue_t *q)
912 {
913 ctlr_info_t *h = q->queuedata;
914 cmdlist_t *c;
915 int seg, sect;
916 char *lastdataend;
917 struct list_head * queue_head = &q->queue_head;
918 struct buffer_head *bh;
919 struct request *creq;
920 struct my_sg tmp_sg[SG_MAX];
921 int i;
922
923 // Loop till the queue is empty if or it is plugged
924 while (1)
925 {
926 if (q->plugged || list_empty(queue_head)) {
927 start_io(h);
928 return;
929 }
930
931 creq = blkdev_entry_next_request(queue_head);
932 if (creq->nr_segments > SG_MAX)
933 BUG();
934
935 if (h->ctlr != MAJOR(creq->rq_dev)-MAJOR_NR || h->ctlr > nr_ctlr)
936 {
937 printk(KERN_WARNING "doreq cmd for %d, %x at %p\n",
938 h->ctlr, creq->rq_dev, creq);
939 blkdev_dequeue_request(creq);
940 complete_buffers(creq->bh, 0);
941 start_io(h);
942 return;
943 }
944
945 if ((c = cmd_alloc(h,1)) == NULL)
946 {
947 start_io(h);
948 return;
949 }
950
951 bh = creq->bh;
952
953 c->ctlr = h->ctlr;
954 c->hdr.unit = MINOR(creq->rq_dev) >> NWD_SHIFT;
955 c->hdr.size = sizeof(rblk_t) >> 2;
956 c->size += sizeof(rblk_t);
957
958 c->req.hdr.blk = ida[(h->ctlr<<CTLR_SHIFT) + MINOR(creq->rq_dev)].start_sect + creq->sector;
959 c->bh = bh;
960 DBGPX(
961 if (bh == NULL)
962 panic("bh == NULL?");
963
964 printk("sector=%d, nr_sectors=%d\n", creq->sector, creq->nr_sectors);
965 );
966 seg = 0; lastdataend = NULL;
967 sect = 0;
968 while(bh) {
969 sect += bh->b_size/512;
970 if (bh->b_data == lastdataend) {
971 tmp_sg[seg-1].size += bh->b_size;
972 lastdataend += bh->b_size;
973 } else {
974 if (seg == SG_MAX)
975 BUG();
976 tmp_sg[seg].size = bh->b_size;
977 tmp_sg[seg].start_addr = bh->b_data;
978 lastdataend = bh->b_data + bh->b_size;
979 seg++;
980 }
981 bh = bh->b_reqnext;
982 }
983 /* Now do all the DMA Mappings */
984 for( i=0; i < seg; i++)
985 {
986 c->req.sg[i].size = tmp_sg[i].size;
987 c->req.sg[i].addr = (__u32) pci_map_single(
988 h->pci_dev, tmp_sg[i].start_addr,
989 tmp_sg[i].size,
990 (creq->cmd == READ) ?
991 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
992 }
993 DBGPX( printk("Submitting %d sectors in %d segments\n", sect, seg); );
994 c->req.hdr.sg_cnt = seg;
995 c->req.hdr.blk_cnt = sect;
996
997 /*
998 * Since we control our own merging, we know that this request
999 * is now fully setup and there's nothing left.
1000 */
1001 if (creq->nr_sectors != sect) {
1002 printk("ida: %ld != %d sectors\n", creq->nr_sectors, sect);
1003 BUG();
1004 }
1005
1006 blkdev_dequeue_request(creq);
1007
1008 /*
1009 * ehh, we can't really end the request here since it's not
1010 * even started yet. for now it shouldn't hurt though
1011 */
1012 DBGPX( printk("Done with %p\n", creq); );
1013 end_that_request_last(creq);
1014
1015 c->req.hdr.cmd = (creq->cmd == READ) ? IDA_READ : IDA_WRITE;
1016 c->type = CMD_RWREQ;
1017
1018 /* Put the request on the tail of the request queue */
1019 addQ(&h->reqQ, c);
1020 h->Qdepth++;
1021 if (h->Qdepth > h->maxQsinceinit)
1022 h->maxQsinceinit = h->Qdepth;
1023 } // while loop
1024 }
1025
1026 /*
1027 * start_io submits everything on a controller's request queue
1028 * and moves it to the completion queue.
1029 *
1030 * Interrupts had better be off if you're in here
1031 */
1032 static void start_io(ctlr_info_t *h)
1033 {
1034 cmdlist_t *c;
1035
1036 while((c = h->reqQ) != NULL) {
1037 /* Can't do anything if we're busy */
1038 if (h->access.fifo_full(h) == 0)
1039 return;
1040
1041 /* Get the first entry from the request Q */
1042 removeQ(&h->reqQ, c);
1043 h->Qdepth--;
1044
1045 /* Tell the controller to do our bidding */
1046 h->access.submit_command(h, c);
1047
1048 /* Get onto the completion Q */
1049 addQ(&h->cmpQ, c);
1050 }
1051 }
1052
1053 static inline void complete_buffers(struct buffer_head *bh, int ok)
1054 {
1055 struct buffer_head *xbh;
1056 while(bh) {
1057 xbh = bh->b_reqnext;
1058 bh->b_reqnext = NULL;
1059
1060 blk_finished_io(bh->b_size >> 9);
1061 bh->b_end_io(bh, ok);
1062
1063 bh = xbh;
1064 }
1065 }
1066 /*
1067 * Mark all buffers that cmd was responsible for
1068 */
1069 static inline void complete_command(cmdlist_t *cmd, int timeout)
1070 {
1071 int ok=1;
1072 int i;
1073
1074 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
1075 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
1076 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
1077 cmd->ctlr, cmd->hdr.unit);
1078 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1079 }
1080 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1081 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1082 cmd->ctlr, cmd->hdr.unit);
1083 ok = 0;
1084 }
1085 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1086 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1087 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1088 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1089 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1090 ok = 0;
1091 }
1092 if (timeout) ok = 0;
1093 /* unmap the DMA mapping for all the scatter gather elements */
1094 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1095 {
1096 pci_unmap_single(hba[cmd->ctlr]->pci_dev,
1097 cmd->req.sg[i].addr, cmd->req.sg[i].size,
1098 (cmd->req.hdr.cmd == IDA_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
1099 }
1100 complete_buffers(cmd->bh, ok);
1101 }
1102
1103 /*
1104 * The controller will interrupt us upon completion of commands.
1105 * Find the command on the completion queue, remove it, tell the OS and
1106 * try to queue up more IO
1107 */
1108 static void do_ida_intr(int irq, void *dev_id, struct pt_regs *regs)
1109 {
1110 ctlr_info_t *h = dev_id;
1111 cmdlist_t *c;
1112 unsigned long istat;
1113 unsigned long flags;
1114 __u32 a,a1;
1115
1116 istat = h->access.intr_pending(h);
1117 /* Is this interrupt for us? */
1118 if (istat == 0)
1119 return;
1120
1121 /*
1122 * If there are completed commands in the completion queue,
1123 * we had better do something about it.
1124 */
1125 spin_lock_irqsave(&io_request_lock, flags);
1126 if (istat & FIFO_NOT_EMPTY) {
1127 while((a = h->access.command_completed(h))) {
1128 a1 = a; a &= ~3;
1129 if ((c = h->cmpQ) == NULL)
1130 {
1131 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1132 continue;
1133 }
1134 while(c->busaddr != a) {
1135 c = c->next;
1136 if (c == h->cmpQ)
1137 break;
1138 }
1139 /*
1140 * If we've found the command, take it off the
1141 * completion Q and free it
1142 */
1143 if (c->busaddr == a) {
1144 removeQ(&h->cmpQ, c);
1145 /* Check for invalid command.
1146 * Controller returns command error,
1147 * But rcode = 0.
1148 */
1149
1150 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1151 {
1152 c->req.hdr.rcode = RCODE_INVREQ;
1153 }
1154 if (c->type == CMD_RWREQ) {
1155 complete_command(c, 0);
1156 cmd_free(h, c, 1);
1157 } else if (c->type == CMD_IOCTL_PEND) {
1158 c->type = CMD_IOCTL_DONE;
1159 }
1160 continue;
1161 }
1162 }
1163 }
1164
1165 /*
1166 * See if we can queue up some more IO
1167 */
1168 do_ida_request(BLK_DEFAULT_QUEUE(MAJOR_NR + h->ctlr));
1169 spin_unlock_irqrestore(&io_request_lock, flags);
1170 }
1171
1172 /*
1173 * This timer was for timing out requests that haven't happened after
1174 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1175 * reset a flags structure so we don't flood the user with
1176 * "Non-Fatal error" messages.
1177 */
1178 static void ida_timer(unsigned long tdata)
1179 {
1180 ctlr_info_t *h = (ctlr_info_t*)tdata;
1181
1182 h->timer.expires = jiffies + IDA_TIMER;
1183 add_timer(&h->timer);
1184 h->misc_tflags = 0;
1185 }
1186
1187 /*
1188 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1189 * setting readahead and submitting commands from userspace to the controller.
1190 */
1191 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg)
1192 {
1193 int ctlr = MAJOR(inode->i_rdev) - MAJOR_NR;
1194 int dsk = MINOR(inode->i_rdev) >> NWD_SHIFT;
1195 int error;
1196 int diskinfo[4];
1197 struct hd_geometry *geo = (struct hd_geometry *)arg;
1198 ida_ioctl_t *io = (ida_ioctl_t*)arg;
1199 ida_ioctl_t my_io;
1200
1201 switch(cmd) {
1202 case HDIO_GETGEO:
1203 if (hba[ctlr]->drv[dsk].cylinders) {
1204 diskinfo[0] = hba[ctlr]->drv[dsk].heads;
1205 diskinfo[1] = hba[ctlr]->drv[dsk].sectors;
1206 diskinfo[2] = hba[ctlr]->drv[dsk].cylinders;
1207 } else {
1208 diskinfo[0] = 0xff;
1209 diskinfo[1] = 0x3f;
1210 diskinfo[2] = hba[ctlr]->drv[dsk].nr_blks / (0xff*0x3f);
1211 }
1212 put_user(diskinfo[0], &geo->heads);
1213 put_user(diskinfo[1], &geo->sectors);
1214 put_user(diskinfo[2], &geo->cylinders);
1215 put_user(ida[(ctlr<<CTLR_SHIFT)+MINOR(inode->i_rdev)].start_sect, &geo->start);
1216 return 0;
1217 case IDAGETDRVINFO:
1218 return copy_to_user(&io->c.drv,&hba[ctlr]->drv[dsk],sizeof(drv_info_t));
1219 case BLKGETSIZE:
1220 return put_user(ida[(ctlr<<CTLR_SHIFT)+MINOR(inode->i_rdev)].nr_sects, (long*)arg);
1221 case BLKGETSIZE64:
1222 return put_user((u64)(ida[(ctlr<<CTLR_SHIFT)+MINOR(inode->i_rdev)].nr_sects) << 9, (u64*)arg);
1223 case BLKRRPART:
1224 return revalidate_logvol(inode->i_rdev, 1);
1225 case IDAPASSTHRU:
1226 if (!suser()) return -EPERM;
1227 error = copy_from_user(&my_io, io, sizeof(my_io));
1228 if (error) return error;
1229 error = ida_ctlr_ioctl(ctlr, dsk, &my_io);
1230 if (error) return error;
1231 error = copy_to_user(io, &my_io, sizeof(my_io));
1232 return error;
1233 case IDAGETCTLRSIG:
1234 if (!arg) return -EINVAL;
1235 put_user(hba[ctlr]->ctlr_sig, (int*)arg);
1236 return 0;
1237 case IDAREVALIDATEVOLS:
1238 return revalidate_allvol(inode->i_rdev);
1239 case IDADRIVERVERSION:
1240 if (!arg) return -EINVAL;
1241 put_user(DRIVER_VERSION, (unsigned long*)arg);
1242 return 0;
1243 case IDAGETPCIINFO:
1244 {
1245
1246 ida_pci_info_struct pciinfo;
1247
1248 if (!arg) return -EINVAL;
1249 pciinfo.bus = hba[ctlr]->pci_dev->bus->number;
1250 pciinfo.dev_fn = hba[ctlr]->pci_dev->devfn;
1251 pciinfo.board_id = hba[ctlr]->board_id;
1252 if(copy_to_user((void *) arg, &pciinfo,
1253 sizeof( ida_pci_info_struct)))
1254 return -EFAULT;
1255 return(0);
1256 }
1257
1258 case BLKFLSBUF:
1259 case BLKBSZSET:
1260 case BLKBSZGET:
1261 case BLKROSET:
1262 case BLKROGET:
1263 case BLKRASET:
1264 case BLKRAGET:
1265 case BLKELVGET:
1266 case BLKELVSET:
1267 case BLKPG:
1268 return blk_ioctl(inode->i_rdev, cmd, arg);
1269
1270 default:
1271 return -EINVAL;
1272 }
1273
1274 }
1275 /*
1276 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1277 * The command block (io) has already been copied to kernel space for us,
1278 * however, any elements in the sglist need to be copied to kernel space
1279 * or copied back to userspace.
1280 *
1281 * Only root may perform a controller passthru command, however I'm not doing
1282 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1283 * putting a 64M buffer in the sglist is probably a *bad* idea.
1284 */
1285 static int ida_ctlr_ioctl(int ctlr, int dsk, ida_ioctl_t *io)
1286 {
1287 ctlr_info_t *h = hba[ctlr];
1288 cmdlist_t *c;
1289 void *p = NULL;
1290 unsigned long flags;
1291 int error;
1292
1293 if ((c = cmd_alloc(h, 0)) == NULL)
1294 return -ENOMEM;
1295 c->ctlr = ctlr;
1296 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1297 c->hdr.size = sizeof(rblk_t) >> 2;
1298 c->size += sizeof(rblk_t);
1299
1300 c->req.hdr.cmd = io->cmd;
1301 c->req.hdr.blk = io->blk;
1302 c->req.hdr.blk_cnt = io->blk_cnt;
1303 c->type = CMD_IOCTL_PEND;
1304
1305 /* Pre submit processing */
1306 switch(io->cmd) {
1307 case PASSTHRU_A:
1308 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1309 if (!p)
1310 {
1311 error = -ENOMEM;
1312 cmd_free(h, c, 0);
1313 return(error);
1314 }
1315 copy_from_user(p, (void*)io->sg[0].addr, io->sg[0].size);
1316 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1317 sizeof(ida_ioctl_t),
1318 PCI_DMA_BIDIRECTIONAL);
1319 c->req.sg[0].size = io->sg[0].size;
1320 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1321 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1322 c->req.hdr.sg_cnt = 1;
1323 break;
1324 case IDA_READ:
1325 case READ_FLASH_ROM:
1326 case SENSE_CONTROLLER_PERFORMANCE:
1327 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1328 if (!p)
1329 {
1330 error = -ENOMEM;
1331 cmd_free(h, c, 0);
1332 return(error);
1333 }
1334
1335 c->req.sg[0].size = io->sg[0].size;
1336 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1337 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1338 c->req.hdr.sg_cnt = 1;
1339 break;
1340 case IDA_WRITE:
1341 case IDA_WRITE_MEDIA:
1342 case DIAG_PASS_THRU:
1343 case COLLECT_BUFFER:
1344 case WRITE_FLASH_ROM:
1345 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1346 if (!p)
1347 {
1348 error = -ENOMEM;
1349 cmd_free(h, c, 0);
1350 return(error);
1351 }
1352 copy_from_user(p, (void*)io->sg[0].addr, io->sg[0].size);
1353 c->req.sg[0].size = io->sg[0].size;
1354 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1355 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1356 c->req.hdr.sg_cnt = 1;
1357 break;
1358 default:
1359 c->req.sg[0].size = sizeof(io->c);
1360 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1361 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1362 c->req.hdr.sg_cnt = 1;
1363 }
1364
1365 /* Put the request on the tail of the request queue */
1366 spin_lock_irqsave(&io_request_lock, flags);
1367 addQ(&h->reqQ, c);
1368 h->Qdepth++;
1369 start_io(h);
1370 spin_unlock_irqrestore(&io_request_lock, flags);
1371
1372 /* Wait for completion */
1373 while(c->type != CMD_IOCTL_DONE)
1374 schedule();
1375
1376 /* Unmap the DMA */
1377 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1378 PCI_DMA_BIDIRECTIONAL);
1379 /* Post submit processing */
1380 switch(io->cmd) {
1381 case PASSTHRU_A:
1382 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1383 sizeof(ida_ioctl_t),
1384 PCI_DMA_BIDIRECTIONAL);
1385 case IDA_READ:
1386 case DIAG_PASS_THRU:
1387 case SENSE_CONTROLLER_PERFORMANCE:
1388 case READ_FLASH_ROM:
1389 copy_to_user((void*)io->sg[0].addr, p, io->sg[0].size);
1390 /* fall through and free p */
1391 case IDA_WRITE:
1392 case IDA_WRITE_MEDIA:
1393 case COLLECT_BUFFER:
1394 case WRITE_FLASH_ROM:
1395 kfree(p);
1396 break;
1397 default:;
1398 /* Nothing to do */
1399 }
1400
1401 io->rcode = c->req.hdr.rcode;
1402 cmd_free(h, c, 0);
1403 return(0);
1404 }
1405
1406 /*
1407 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1408 * scheme to suballocte them to the driver. Operations that are not time
1409 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1410 * as the first argument to get a new command.
1411 */
1412 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1413 {
1414 cmdlist_t * c;
1415 int i;
1416 dma_addr_t cmd_dhandle;
1417
1418 if (!get_from_pool) {
1419 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1420 sizeof(cmdlist_t), &cmd_dhandle);
1421 if(c==NULL)
1422 return NULL;
1423 } else {
1424 do {
1425 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1426 if (i == NR_CMDS)
1427 return NULL;
1428 } while(test_and_set_bit(i%32, h->cmd_pool_bits+(i/32)) != 0);
1429 c = h->cmd_pool + i;
1430 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1431 h->nr_allocs++;
1432 }
1433
1434 memset(c, 0, sizeof(cmdlist_t));
1435 c->busaddr = cmd_dhandle;
1436 return c;
1437 }
1438
1439 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1440 {
1441 int i;
1442
1443 if (!got_from_pool) {
1444 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1445 c->busaddr);
1446 } else {
1447 i = c - h->cmd_pool;
1448 clear_bit(i%32, h->cmd_pool_bits+(i/32));
1449 h->nr_frees++;
1450 }
1451 }
1452
1453 /***********************************************************************
1454 name: sendcmd
1455 Send a command to an IDA using the memory mapped FIFO interface
1456 and wait for it to complete.
1457 This routine should only be called at init time.
1458 ***********************************************************************/
1459 static int sendcmd(
1460 __u8 cmd,
1461 int ctlr,
1462 void *buff,
1463 size_t size,
1464 unsigned int blk,
1465 unsigned int blkcnt,
1466 unsigned int log_unit )
1467 {
1468 cmdlist_t *c;
1469 int complete;
1470 unsigned long temp;
1471 unsigned long i;
1472 ctlr_info_t *info_p = hba[ctlr];
1473
1474 c = cmd_alloc(info_p, 1);
1475 if(!c)
1476 return IO_ERROR;
1477 c->ctlr = ctlr;
1478 c->hdr.unit = log_unit;
1479 c->hdr.prio = 0;
1480 c->hdr.size = sizeof(rblk_t) >> 2;
1481 c->size += sizeof(rblk_t);
1482
1483 /* The request information. */
1484 c->req.hdr.next = 0;
1485 c->req.hdr.rcode = 0;
1486 c->req.bp = 0;
1487 c->req.hdr.sg_cnt = 1;
1488 c->req.hdr.reserved = 0;
1489
1490 if (size == 0)
1491 c->req.sg[0].size = 512;
1492 else
1493 c->req.sg[0].size = size;
1494
1495 c->req.hdr.blk = blk;
1496 c->req.hdr.blk_cnt = blkcnt;
1497 c->req.hdr.cmd = (unsigned char) cmd;
1498 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1499 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1500 /*
1501 * Disable interrupt
1502 */
1503 info_p->access.set_intr_mask(info_p, 0);
1504 /* Make sure there is room in the command FIFO */
1505 /* Actually it should be completely empty at this time. */
1506 for (i = 200000; i > 0; i--) {
1507 temp = info_p->access.fifo_full(info_p);
1508 if (temp != 0) {
1509 break;
1510 }
1511 udelay(10);
1512 DBG(
1513 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1514 " waiting!\n", ctlr);
1515 );
1516 }
1517 /*
1518 * Send the cmd
1519 */
1520 info_p->access.submit_command(info_p, c);
1521 complete = pollcomplete(ctlr);
1522
1523 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1524 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1525 if (complete != 1) {
1526 if (complete != c->busaddr) {
1527 printk( KERN_WARNING
1528 "cpqarray ida%d: idaSendPciCmd "
1529 "Invalid command list address returned! (%08lx)\n",
1530 ctlr, (unsigned long)complete);
1531 cmd_free(info_p, c, 1);
1532 return (IO_ERROR);
1533 }
1534 } else {
1535 printk( KERN_WARNING
1536 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1537 "No command list address returned!\n",
1538 ctlr);
1539 cmd_free(info_p, c, 1);
1540 return (IO_ERROR);
1541 }
1542
1543 if (c->req.hdr.rcode & 0x00FE) {
1544 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1545 printk( KERN_WARNING
1546 "cpqarray ida%d: idaSendPciCmd, error: "
1547 "Controller failed at init time "
1548 "cmd: 0x%x, return code = 0x%x\n",
1549 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1550
1551 cmd_free(info_p, c, 1);
1552 return (IO_ERROR);
1553 }
1554 }
1555 cmd_free(info_p, c, 1);
1556 return (IO_OK);
1557 }
1558
1559 static int frevalidate_logvol(kdev_t dev)
1560 {
1561 return revalidate_logvol(dev, 0);
1562 }
1563
1564 /*
1565 * revalidate_allvol is for online array config utilities. After a
1566 * utility reconfigures the drives in the array, it can use this function
1567 * (through an ioctl) to make the driver zap any previous disk structs for
1568 * that controller and get new ones.
1569 *
1570 * Right now I'm using the getgeometry() function to do this, but this
1571 * function should probably be finer grained and allow you to revalidate one
1572 * particualar logical volume (instead of all of them on a particular
1573 * controller).
1574 */
1575 static int revalidate_allvol(kdev_t dev)
1576 {
1577 int ctlr, i;
1578 unsigned long flags;
1579
1580 ctlr = MAJOR(dev) - MAJOR_NR;
1581 if (MINOR(dev) != 0)
1582 return -ENXIO;
1583
1584 spin_lock_irqsave(&io_request_lock, flags);
1585 if (hba[ctlr]->usage_count > 1) {
1586 spin_unlock_irqrestore(&io_request_lock, flags);
1587 printk(KERN_WARNING "cpqarray: Device busy for volume"
1588 " revalidation (usage=%d)\n", hba[ctlr]->usage_count);
1589 return -EBUSY;
1590 }
1591 spin_unlock_irqrestore(&io_request_lock, flags);
1592 hba[ctlr]->usage_count++;
1593
1594 /*
1595 * Set the partition and block size structures for all volumes
1596 * on this controller to zero. We will reread all of this data
1597 */
1598 memset(ida+(ctlr*256), 0, sizeof(struct hd_struct)*NWD*16);
1599 memset(ida_sizes+(ctlr*256), 0, sizeof(int)*NWD*16);
1600 memset(ida_blocksizes+(ctlr*256), 0, sizeof(int)*NWD*16);
1601 memset(ida_hardsizes+(ctlr*256), 0, sizeof(int)*NWD*16);
1602 memset(hba[ctlr]->drv, 0, sizeof(drv_info_t)*NWD);
1603 ida_gendisk[ctlr].nr_real = 0;
1604
1605 /*
1606 * Tell the array controller not to give us any interrupts while
1607 * we check the new geometry. Then turn interrupts back on when
1608 * we're done.
1609 */
1610 hba[ctlr]->access.set_intr_mask(hba[ctlr], 0);
1611 getgeometry(ctlr);
1612 hba[ctlr]->access.set_intr_mask(hba[ctlr], FIFO_NOT_EMPTY);
1613
1614 ida_geninit(ctlr);
1615 for(i=0; i<NWD; i++)
1616 if (ida_sizes[(ctlr<<CTLR_SHIFT) + (i<<NWD_SHIFT)])
1617 revalidate_logvol(dev+(i<<NWD_SHIFT), 2);
1618
1619 hba[ctlr]->usage_count--;
1620 return 0;
1621 }
1622
1623 /* Borrowed and adapted from sd.c */
1624 static int revalidate_logvol(kdev_t dev, int maxusage)
1625 {
1626 int ctlr, target;
1627 struct gendisk *gdev;
1628 unsigned long flags;
1629 int max_p;
1630 int start;
1631 int i;
1632
1633 target = DEVICE_NR(dev);
1634 ctlr = MAJOR(dev) - MAJOR_NR;
1635 gdev = &ida_gendisk[ctlr];
1636
1637 spin_lock_irqsave(&io_request_lock, flags);
1638 if (hba[ctlr]->drv[target].usage_count > maxusage) {
1639 spin_unlock_irqrestore(&io_request_lock, flags);
1640 printk(KERN_WARNING "cpqarray: Device busy for "
1641 "revalidation (usage=%d)\n",
1642 hba[ctlr]->drv[target].usage_count);
1643 return -EBUSY;
1644 }
1645
1646 hba[ctlr]->drv[target].usage_count++;
1647 spin_unlock_irqrestore(&io_request_lock, flags);
1648
1649 max_p = gdev->max_p;
1650 start = target << gdev->minor_shift;
1651
1652 for(i=max_p-1; i>=0; i--) {
1653 int minor = start+i;
1654 invalidate_device(MKDEV(MAJOR_NR + ctlr, minor), 1);
1655 gdev->part[minor].start_sect = 0;
1656 gdev->part[minor].nr_sects = 0;
1657
1658 /* reset the blocksize so we can read the partition table */
1659 blksize_size[MAJOR_NR+ctlr][minor] = 1024;
1660 }
1661
1662 /* 16 minors per disk... */
1663 grok_partitions(gdev, target, 16, hba[ctlr]->drv[target].nr_blks);
1664 hba[ctlr]->drv[target].usage_count--;
1665 return 0;
1666 }
1667
1668
1669 /********************************************************************
1670 name: pollcomplete
1671 Wait polling for a command to complete.
1672 The memory mapped FIFO is polled for the completion.
1673 Used only at init time, interrupts disabled.
1674 ********************************************************************/
1675 static int pollcomplete(int ctlr)
1676 {
1677 int done;
1678 int i;
1679
1680 /* Wait (up to 2 seconds) for a command to complete */
1681
1682 for (i = 200000; i > 0; i--) {
1683 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1684 if (done == 0) {
1685 udelay(10); /* a short fixed delay */
1686 } else
1687 return (done);
1688 }
1689 /* Invalid address to tell caller we ran out of time */
1690 return 1;
1691 }
1692 /*****************************************************************
1693 start_fwbk
1694 Starts controller firmwares background processing.
1695 Currently only the Integrated Raid controller needs this done.
1696 If the PCI mem address registers are written to after this,
1697 data corruption may occur
1698 *****************************************************************/
1699 static void start_fwbk(int ctlr)
1700 {
1701 id_ctlr_t *id_ctlr_buf;
1702 int ret_code;
1703
1704 if( (hba[ctlr]->board_id != 0x40400E11)
1705 && (hba[ctlr]->board_id != 0x40480E11) )
1706
1707 /* Not a Integrated Raid, so there is nothing for us to do */
1708 return;
1709 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1710 " processing\n");
1711 /* Command does not return anything, but idasend command needs a
1712 buffer */
1713 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1714 if(id_ctlr_buf==NULL)
1715 {
1716 printk(KERN_WARNING "cpqarray: Out of memory. "
1717 "Unable to start background processing.\n");
1718 return;
1719 }
1720 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1721 id_ctlr_buf, 0, 0, 0, 0);
1722 if(ret_code != IO_OK)
1723 printk(KERN_WARNING "cpqarray: Unable to start"
1724 " background processing\n");
1725
1726 kfree(id_ctlr_buf);
1727 }
1728 /*****************************************************************
1729 getgeometry
1730 Get ida logical volume geometry from the controller
1731 This is a large bit of code which once existed in two flavors,
1732 It is used only at init time.
1733 *****************************************************************/
1734 static void getgeometry(int ctlr)
1735 {
1736 id_log_drv_t *id_ldrive;
1737 id_ctlr_t *id_ctlr_buf;
1738 sense_log_drv_stat_t *id_lstatus_buf;
1739 config_t *sense_config_buf;
1740 unsigned int log_unit, log_index;
1741 int ret_code, size;
1742 drv_info_t *drv;
1743 ctlr_info_t *info_p = hba[ctlr];
1744 int i;
1745
1746 info_p->log_drv_map = 0;
1747
1748 id_ldrive = (id_log_drv_t *)kmalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1749 if(id_ldrive == NULL)
1750 {
1751 printk( KERN_ERR "cpqarray: out of memory.\n");
1752 return;
1753 }
1754
1755 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1756 if(id_ctlr_buf == NULL)
1757 {
1758 kfree(id_ldrive);
1759 printk( KERN_ERR "cpqarray: out of memory.\n");
1760 return;
1761 }
1762
1763 id_lstatus_buf = (sense_log_drv_stat_t *)kmalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1764 if(id_lstatus_buf == NULL)
1765 {
1766 kfree(id_ctlr_buf);
1767 kfree(id_ldrive);
1768 printk( KERN_ERR "cpqarray: out of memory.\n");
1769 return;
1770 }
1771
1772 sense_config_buf = (config_t *)kmalloc(sizeof(config_t), GFP_KERNEL);
1773 if(sense_config_buf == NULL)
1774 {
1775 kfree(id_lstatus_buf);
1776 kfree(id_ctlr_buf);
1777 kfree(id_ldrive);
1778 printk( KERN_ERR "cpqarray: out of memory.\n");
1779 return;
1780 }
1781
1782 memset(id_ldrive, 0, sizeof(id_log_drv_t));
1783 memset(id_ctlr_buf, 0, sizeof(id_ctlr_t));
1784 memset(id_lstatus_buf, 0, sizeof(sense_log_drv_stat_t));
1785 memset(sense_config_buf, 0, sizeof(config_t));
1786
1787 info_p->phys_drives = 0;
1788 info_p->log_drv_map = 0;
1789 info_p->drv_assign_map = 0;
1790 info_p->drv_spare_map = 0;
1791 info_p->mp_failed_drv_map = 0; /* only initialized here */
1792 /* Get controllers info for this logical drive */
1793 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1794 if (ret_code == IO_ERROR) {
1795 /*
1796 * If can't get controller info, set the logical drive map to 0,
1797 * so the idastubopen will fail on all logical drives
1798 * on the controller.
1799 */
1800 /* Free all the buffers and return */
1801 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1802 kfree(sense_config_buf);
1803 kfree(id_lstatus_buf);
1804 kfree(id_ctlr_buf);
1805 kfree(id_ldrive);
1806 return;
1807 }
1808
1809 info_p->log_drives = id_ctlr_buf->nr_drvs;;
1810 for(i=0;i<4;i++)
1811 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1812 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1813
1814 printk(" (%s)\n", info_p->product_name);
1815 /*
1816 * Initialize logical drive map to zero
1817 */
1818 log_index = 0;
1819 /*
1820 * Get drive geometry for all logical drives
1821 */
1822 if (id_ctlr_buf->nr_drvs > 16)
1823 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1824 "16 logical drives per controller.\n. "
1825 " Additional drives will not be "
1826 "detected\n", ctlr);
1827
1828 for (log_unit = 0;
1829 (log_index < id_ctlr_buf->nr_drvs)
1830 && (log_unit < NWD);
1831 log_unit++) {
1832
1833 size = sizeof(sense_log_drv_stat_t);
1834
1835 /*
1836 Send "Identify logical drive status" cmd
1837 */
1838 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1839 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1840 if (ret_code == IO_ERROR) {
1841 /*
1842 If can't get logical drive status, set
1843 the logical drive map to 0, so the
1844 idastubopen will fail for all logical drives
1845 on the controller.
1846 */
1847 info_p->log_drv_map = 0;
1848 printk( KERN_WARNING
1849 "cpqarray ida%d: idaGetGeometry - Controller"
1850 " failed to report status of logical drive %d\n"
1851 "Access to this controller has been disabled\n",
1852 ctlr, log_unit);
1853 /* Free all the buffers and return */
1854 kfree(sense_config_buf);
1855 kfree(id_lstatus_buf);
1856 kfree(id_ctlr_buf);
1857 kfree(id_ldrive);
1858 return;
1859 }
1860 /*
1861 Make sure the logical drive is configured
1862 */
1863 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1864 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1865 sizeof(id_log_drv_t), 0, 0, log_unit);
1866 /*
1867 If error, the bit for this
1868 logical drive won't be set and
1869 idastubopen will return error.
1870 */
1871 if (ret_code != IO_ERROR) {
1872 drv = &info_p->drv[log_unit];
1873 drv->blk_size = id_ldrive->blk_size;
1874 drv->nr_blks = id_ldrive->nr_blks;
1875 drv->cylinders = id_ldrive->drv.cyl;
1876 drv->heads = id_ldrive->drv.heads;
1877 drv->sectors = id_ldrive->drv.sect_per_track;
1878 info_p->log_drv_map |= (1 << log_unit);
1879
1880 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1881 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1882 ret_code = sendcmd(SENSE_CONFIG,
1883 ctlr, sense_config_buf,
1884 sizeof(config_t), 0, 0, log_unit);
1885 if (ret_code == IO_ERROR) {
1886 info_p->log_drv_map = 0;
1887 /* Free all the buffers and return */
1888 printk(KERN_ERR "cpqarray: error sending sense config\n");
1889 kfree(sense_config_buf);
1890 kfree(id_lstatus_buf);
1891 kfree(id_ctlr_buf);
1892 kfree(id_ldrive);
1893 return;
1894
1895 }
1896 info_p->phys_drives =
1897 sense_config_buf->ctlr_phys_drv;
1898 info_p->drv_assign_map
1899 |= sense_config_buf->drv_asgn_map;
1900 info_p->drv_assign_map
1901 |= sense_config_buf->spare_asgn_map;
1902 info_p->drv_spare_map
1903 |= sense_config_buf->spare_asgn_map;
1904 } /* end of if no error on id_ldrive */
1905 log_index = log_index + 1;
1906 } /* end of if logical drive configured */
1907 } /* end of for log_unit */
1908 kfree(sense_config_buf);
1909 kfree(id_ldrive);
1910 kfree(id_lstatus_buf);
1911 kfree(id_ctlr_buf);
1912 return;
1913
1914 }
1915