File: /usr/src/linux/drivers/char/drm/r128_drv.h
1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel Dänzer <daenzerm@student.ethz.ch>
32 */
33
34 #ifndef __R128_DRV_H__
35 #define __R128_DRV_H__
36
37 #define GET_RING_HEAD( ring ) le32_to_cpu( *(ring)->head )
38 #define SET_RING_HEAD( ring, val ) *(ring)->head = cpu_to_le32( val )
39
40 typedef struct drm_r128_freelist {
41 unsigned int age;
42 drm_buf_t *buf;
43 struct drm_r128_freelist *next;
44 struct drm_r128_freelist *prev;
45 } drm_r128_freelist_t;
46
47 typedef struct drm_r128_ring_buffer {
48 u32 *start;
49 u32 *end;
50 int size;
51 int size_l2qw;
52
53 volatile u32 *head;
54 u32 tail;
55 u32 tail_mask;
56 int space;
57
58 int high_mark;
59 } drm_r128_ring_buffer_t;
60
61 typedef struct drm_r128_private {
62 drm_r128_ring_buffer_t ring;
63 drm_r128_sarea_t *sarea_priv;
64
65 int cce_mode;
66 int cce_fifo_size;
67 int cce_running;
68
69 drm_r128_freelist_t *head;
70 drm_r128_freelist_t *tail;
71
72 int usec_timeout;
73 int is_pci;
74 unsigned long phys_pci_gart;
75 dma_addr_t bus_pci_gart;
76 unsigned long cce_buffers_offset;
77
78 atomic_t idle_count;
79
80 int page_flipping;
81 int current_page;
82 u32 crtc_offset;
83 u32 crtc_offset_cntl;
84
85 u32 color_fmt;
86 unsigned int front_offset;
87 unsigned int front_pitch;
88 unsigned int back_offset;
89 unsigned int back_pitch;
90
91 u32 depth_fmt;
92 unsigned int depth_offset;
93 unsigned int depth_pitch;
94 unsigned int span_offset;
95
96 u32 front_pitch_offset_c;
97 u32 back_pitch_offset_c;
98 u32 depth_pitch_offset_c;
99 u32 span_pitch_offset_c;
100
101 drm_map_t *sarea;
102 drm_map_t *fb;
103 drm_map_t *mmio;
104 drm_map_t *cce_ring;
105 drm_map_t *ring_rptr;
106 drm_map_t *buffers;
107 drm_map_t *agp_textures;
108 } drm_r128_private_t;
109
110 typedef struct drm_r128_buf_priv {
111 u32 age;
112 int prim;
113 int discard;
114 int dispatched;
115 drm_r128_freelist_t *list_entry;
116 } drm_r128_buf_priv_t;
117
118 /* r128_cce.c */
119 extern int r128_cce_init( struct inode *inode, struct file *filp,
120 unsigned int cmd, unsigned long arg );
121 extern int r128_cce_start( struct inode *inode, struct file *filp,
122 unsigned int cmd, unsigned long arg );
123 extern int r128_cce_stop( struct inode *inode, struct file *filp,
124 unsigned int cmd, unsigned long arg );
125 extern int r128_cce_reset( struct inode *inode, struct file *filp,
126 unsigned int cmd, unsigned long arg );
127 extern int r128_cce_idle( struct inode *inode, struct file *filp,
128 unsigned int cmd, unsigned long arg );
129 extern int r128_engine_reset( struct inode *inode, struct file *filp,
130 unsigned int cmd, unsigned long arg );
131 extern int r128_fullscreen( struct inode *inode, struct file *filp,
132 unsigned int cmd, unsigned long arg );
133 extern int r128_cce_buffers( struct inode *inode, struct file *filp,
134 unsigned int cmd, unsigned long arg );
135
136 extern void r128_freelist_reset( drm_device_t *dev );
137 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
138
139 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
140
141 static inline void
142 r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
143 {
144 ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
145 if ( ring->space <= 0 )
146 ring->space += ring->size;
147 }
148
149 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
150 extern int r128_do_cleanup_cce( drm_device_t *dev );
151 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
152
153 /* r128_state.c */
154 extern int r128_cce_clear( struct inode *inode, struct file *filp,
155 unsigned int cmd, unsigned long arg );
156 extern int r128_cce_swap( struct inode *inode, struct file *filp,
157 unsigned int cmd, unsigned long arg );
158 extern int r128_cce_vertex( struct inode *inode, struct file *filp,
159 unsigned int cmd, unsigned long arg );
160 extern int r128_cce_indices( struct inode *inode, struct file *filp,
161 unsigned int cmd, unsigned long arg );
162 extern int r128_cce_blit( struct inode *inode, struct file *filp,
163 unsigned int cmd, unsigned long arg );
164 extern int r128_cce_depth( struct inode *inode, struct file *filp,
165 unsigned int cmd, unsigned long arg );
166 extern int r128_cce_stipple( struct inode *inode, struct file *filp,
167 unsigned int cmd, unsigned long arg );
168 extern int r128_cce_indirect( struct inode *inode, struct file *filp,
169 unsigned int cmd, unsigned long arg );
170
171
172 /* Register definitions, register access macros and drmAddMap constants
173 * for Rage 128 kernel driver.
174 */
175
176 #define R128_AUX_SC_CNTL 0x1660
177 # define R128_AUX1_SC_EN (1 << 0)
178 # define R128_AUX1_SC_MODE_OR (0 << 1)
179 # define R128_AUX1_SC_MODE_NAND (1 << 1)
180 # define R128_AUX2_SC_EN (1 << 2)
181 # define R128_AUX2_SC_MODE_OR (0 << 3)
182 # define R128_AUX2_SC_MODE_NAND (1 << 3)
183 # define R128_AUX3_SC_EN (1 << 4)
184 # define R128_AUX3_SC_MODE_OR (0 << 5)
185 # define R128_AUX3_SC_MODE_NAND (1 << 5)
186 #define R128_AUX1_SC_LEFT 0x1664
187 #define R128_AUX1_SC_RIGHT 0x1668
188 #define R128_AUX1_SC_TOP 0x166c
189 #define R128_AUX1_SC_BOTTOM 0x1670
190 #define R128_AUX2_SC_LEFT 0x1674
191 #define R128_AUX2_SC_RIGHT 0x1678
192 #define R128_AUX2_SC_TOP 0x167c
193 #define R128_AUX2_SC_BOTTOM 0x1680
194 #define R128_AUX3_SC_LEFT 0x1684
195 #define R128_AUX3_SC_RIGHT 0x1688
196 #define R128_AUX3_SC_TOP 0x168c
197 #define R128_AUX3_SC_BOTTOM 0x1690
198
199 #define R128_BRUSH_DATA0 0x1480
200 #define R128_BUS_CNTL 0x0030
201 # define R128_BUS_MASTER_DIS (1 << 6)
202
203 #define R128_CLOCK_CNTL_INDEX 0x0008
204 #define R128_CLOCK_CNTL_DATA 0x000c
205 # define R128_PLL_WR_EN (1 << 7)
206 #define R128_CONSTANT_COLOR_C 0x1d34
207 #define R128_CRTC_OFFSET 0x0224
208 #define R128_CRTC_OFFSET_CNTL 0x0228
209 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
210
211 #define R128_DP_GUI_MASTER_CNTL 0x146c
212 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
213 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
214 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
215 # define R128_GMC_BRUSH_NONE (15 << 4)
216 # define R128_GMC_DST_16BPP (4 << 8)
217 # define R128_GMC_DST_24BPP (5 << 8)
218 # define R128_GMC_DST_32BPP (6 << 8)
219 # define R128_GMC_DST_DATATYPE_SHIFT 8
220 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
221 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
222 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
223 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
224 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
225 # define R128_GMC_WR_MSK_DIS (1 << 30)
226 # define R128_ROP3_S 0x00cc0000
227 # define R128_ROP3_P 0x00f00000
228 #define R128_DP_WRITE_MASK 0x16cc
229 #define R128_DST_PITCH_OFFSET_C 0x1c80
230 # define R128_DST_TILE (1 << 31)
231
232 #define R128_GEN_RESET_CNTL 0x00f0
233 # define R128_SOFT_RESET_GUI (1 << 0)
234
235 #define R128_GUI_SCRATCH_REG0 0x15e0
236 #define R128_GUI_SCRATCH_REG1 0x15e4
237 #define R128_GUI_SCRATCH_REG2 0x15e8
238 #define R128_GUI_SCRATCH_REG3 0x15ec
239 #define R128_GUI_SCRATCH_REG4 0x15f0
240 #define R128_GUI_SCRATCH_REG5 0x15f4
241
242 #define R128_GUI_STAT 0x1740
243 # define R128_GUI_FIFOCNT_MASK 0x0fff
244 # define R128_GUI_ACTIVE (1 << 31)
245
246 #define R128_MCLK_CNTL 0x000f
247 # define R128_FORCE_GCP (1 << 16)
248 # define R128_FORCE_PIPE3D_CP (1 << 17)
249 # define R128_FORCE_RCP (1 << 18)
250
251 #define R128_PC_GUI_CTLSTAT 0x1748
252 #define R128_PC_NGUI_CTLSTAT 0x0184
253 # define R128_PC_FLUSH_GUI (3 << 0)
254 # define R128_PC_RI_GUI (1 << 2)
255 # define R128_PC_FLUSH_ALL 0x00ff
256 # define R128_PC_BUSY (1 << 31)
257
258 #define R128_PCI_GART_PAGE 0x017c
259 #define R128_PRIM_TEX_CNTL_C 0x1cb0
260
261 #define R128_SCALE_3D_CNTL 0x1a00
262 #define R128_SEC_TEX_CNTL_C 0x1d00
263 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
264 #define R128_SETUP_CNTL 0x1bc4
265 #define R128_STEN_REF_MASK_C 0x1d40
266
267 #define R128_TEX_CNTL_C 0x1c9c
268 # define R128_TEX_CACHE_FLUSH (1 << 23)
269
270 #define R128_WAIT_UNTIL 0x1720
271 # define R128_EVENT_CRTC_OFFSET (1 << 0)
272 #define R128_WINDOW_XY_OFFSET 0x1bcc
273
274
275 /* CCE registers
276 */
277 #define R128_PM4_BUFFER_OFFSET 0x0700
278 #define R128_PM4_BUFFER_CNTL 0x0704
279 # define R128_PM4_MASK (15 << 28)
280 # define R128_PM4_NONPM4 (0 << 28)
281 # define R128_PM4_192PIO (1 << 28)
282 # define R128_PM4_192BM (2 << 28)
283 # define R128_PM4_128PIO_64INDBM (3 << 28)
284 # define R128_PM4_128BM_64INDBM (4 << 28)
285 # define R128_PM4_64PIO_128INDBM (5 << 28)
286 # define R128_PM4_64BM_128INDBM (6 << 28)
287 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
288 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
289 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
290
291 #define R128_PM4_BUFFER_WM_CNTL 0x0708
292 # define R128_WMA_SHIFT 0
293 # define R128_WMB_SHIFT 8
294 # define R128_WMC_SHIFT 16
295 # define R128_WB_WM_SHIFT 24
296
297 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
298 #define R128_PM4_BUFFER_DL_RPTR 0x0710
299 #define R128_PM4_BUFFER_DL_WPTR 0x0714
300 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
301
302 #define R128_PM4_VC_FPU_SETUP 0x071c
303
304 #define R128_PM4_IW_INDOFF 0x0738
305 #define R128_PM4_IW_INDSIZE 0x073c
306
307 #define R128_PM4_STAT 0x07b8
308 # define R128_PM4_FIFOCNT_MASK 0x0fff
309 # define R128_PM4_BUSY (1 << 16)
310 # define R128_PM4_GUI_ACTIVE (1 << 31)
311
312 #define R128_PM4_MICROCODE_ADDR 0x07d4
313 #define R128_PM4_MICROCODE_RADDR 0x07d8
314 #define R128_PM4_MICROCODE_DATAH 0x07dc
315 #define R128_PM4_MICROCODE_DATAL 0x07e0
316
317 #define R128_PM4_BUFFER_ADDR 0x07f0
318 #define R128_PM4_MICRO_CNTL 0x07fc
319 # define R128_PM4_MICRO_FREERUN (1 << 30)
320
321 #define R128_PM4_FIFO_DATA_EVEN 0x1000
322 #define R128_PM4_FIFO_DATA_ODD 0x1004
323
324
325 /* CCE command packets
326 */
327 #define R128_CCE_PACKET0 0x00000000
328 #define R128_CCE_PACKET1 0x40000000
329 #define R128_CCE_PACKET2 0x80000000
330 #define R128_CCE_PACKET3 0xC0000000
331 # define R128_CNTL_HOSTDATA_BLT 0x00009400
332 # define R128_CNTL_PAINT_MULTI 0x00009A00
333 # define R128_CNTL_BITBLT_MULTI 0x00009B00
334 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
335
336 #define R128_CCE_PACKET_MASK 0xC0000000
337 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
338 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
339 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
340 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
341
342 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
343 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
344 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
345 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
346 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
347 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
348 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
349 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
350 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
351 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
352 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
353 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
354
355 #define R128_DATATYPE_CI8 2
356 #define R128_DATATYPE_ARGB1555 3
357 #define R128_DATATYPE_RGB565 4
358 #define R128_DATATYPE_RGB888 5
359 #define R128_DATATYPE_ARGB8888 6
360 #define R128_DATATYPE_RGB332 7
361 #define R128_DATATYPE_RGB8 9
362 #define R128_DATATYPE_ARGB4444 15
363
364 /* Constants */
365 #define R128_AGP_OFFSET 0x02000000
366
367 #define R128_WATERMARK_L 16
368 #define R128_WATERMARK_M 8
369 #define R128_WATERMARK_N 8
370 #define R128_WATERMARK_K 128
371
372 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
373
374 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
375 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
376 #define R128_MAX_VB_AGE 0x7fffffff
377 #define R128_MAX_VB_VERTS (0xffff)
378
379 #define R128_RING_HIGH_MARK 128
380
381 #define R128_PERFORMANCE_BOXES 0
382
383
384 #define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
385 #define R128_ADDR(reg) (R128_BASE( reg ) + reg)
386
387 #define R128_DEREF(reg) *(volatile u32 *)R128_ADDR( reg )
388 #ifdef __alpha__
389 #define R128_READ(reg) (_R128_READ((u32 *)R128_ADDR(reg)))
390 static inline u32 _R128_READ(u32 *addr)
391 {
392 mb();
393 return *(volatile u32 *)addr;
394 }
395 #define R128_WRITE(reg,val) \
396 do { \
397 wmb(); \
398 R128_DEREF(reg) = val; \
399 } while (0)
400 #else
401 #define R128_READ(reg) le32_to_cpu( R128_DEREF( reg ) )
402 #define R128_WRITE(reg,val) \
403 do { \
404 R128_DEREF( reg ) = cpu_to_le32( val ); \
405 } while (0)
406 #endif
407
408 #define R128_DEREF8(reg) *(volatile u8 *)R128_ADDR( reg )
409 #ifdef __alpha__
410 #define R128_READ8(reg) _R128_READ8((u8 *)R128_ADDR(reg))
411 static inline u8 _R128_READ8(u8 *addr)
412 {
413 mb();
414 return *(volatile u8 *)addr;
415 }
416 #define R128_WRITE8(reg,val) \
417 do { \
418 wmb(); \
419 R128_DEREF8(reg) = val; \
420 } while (0)
421 #else
422 #define R128_READ8(reg) R128_DEREF8( reg )
423 #define R128_WRITE8(reg,val) do { R128_DEREF8( reg ) = val; } while (0)
424 #endif
425
426 #define R128_WRITE_PLL(addr,val) \
427 do { \
428 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
429 ((addr) & 0x1f) | R128_PLL_WR_EN); \
430 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
431 } while (0)
432
433 extern int R128_READ_PLL(drm_device_t *dev, int addr);
434
435
436 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
437 ((n) << 16) | ((reg) >> 2))
438 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
439 (((reg1) >> 2) << 11) | ((reg0) >> 2))
440 #define CCE_PACKET2() (R128_CCE_PACKET2)
441 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
442 (pkt) | ((n) << 16))
443
444
445 /* ================================================================
446 * Misc helper macros
447 */
448
449 #define LOCK_TEST_WITH_RETURN( dev ) \
450 do { \
451 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
452 dev->lock.pid != current->pid ) { \
453 DRM_ERROR( "%s called without lock held\n", \
454 __FUNCTION__ ); \
455 return -EINVAL; \
456 } \
457 } while (0)
458
459 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
460 do { \
461 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
462 if ( ring->space < ring->high_mark ) { \
463 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
464 r128_update_ring_snapshot( ring ); \
465 if ( ring->space >= ring->high_mark ) \
466 goto __ring_space_done; \
467 udelay( 1 ); \
468 } \
469 DRM_ERROR( "ring space check failed!\n" ); \
470 return -EBUSY; \
471 } \
472 __ring_space_done: \
473 } while (0)
474
475 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
476 do { \
477 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
478 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
479 int __ret = r128_do_cce_idle( dev_priv ); \
480 if ( __ret < 0 ) return __ret; \
481 sarea_priv->last_dispatch = 0; \
482 r128_freelist_reset( dev ); \
483 } \
484 } while (0)
485
486 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
487 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
488 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
489 } while (0)
490
491
492 /* ================================================================
493 * Ring control
494 */
495
496 #define r128_flush_write_combine() mb()
497
498
499 #define R128_VERBOSE 0
500
501 #define RING_LOCALS \
502 int write; unsigned int tail_mask; volatile u32 *ring;
503
504 #define BEGIN_RING( n ) do { \
505 if ( R128_VERBOSE ) { \
506 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
507 (n), __FUNCTION__ ); \
508 } \
509 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
510 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
511 } \
512 dev_priv->ring.space -= (n) * sizeof(u32); \
513 ring = dev_priv->ring.start; \
514 write = dev_priv->ring.tail; \
515 tail_mask = dev_priv->ring.tail_mask; \
516 } while (0)
517
518 /* You can set this to zero if you want. If the card locks up, you'll
519 * need to keep this set. It works around a bug in early revs of the
520 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
521 * the ring buffer before wrapping around.
522 */
523 #define R128_BROKEN_CCE 1
524
525 #define ADVANCE_RING() do { \
526 if ( R128_VERBOSE ) { \
527 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
528 write, dev_priv->ring.tail ); \
529 } \
530 if ( R128_BROKEN_CCE && write < 32 ) { \
531 memcpy( dev_priv->ring.end, \
532 dev_priv->ring.start, \
533 write * sizeof(u32) ); \
534 } \
535 r128_flush_write_combine(); \
536 dev_priv->ring.tail = write; \
537 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
538 } while (0)
539
540 #define OUT_RING( x ) do { \
541 if ( R128_VERBOSE ) { \
542 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
543 (unsigned int)(x), write ); \
544 } \
545 ring[write++] = cpu_to_le32( x ); \
546 write &= tail_mask; \
547 } while (0)
548
549 #endif /* __R128_DRV_H__ */
550