File: /usr/src/linux/drivers/char/drm/r128_cce.c
1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 *
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #define __NO_VERSION__
32 #include "r128.h"
33 #include "drmP.h"
34 #include "r128_drv.h"
35
36 #include <linux/interrupt.h> /* For task queue support */
37 #include <linux/delay.h>
38
39 #define R128_FIFO_DEBUG 0
40
41
42 /* CCE microcode (from ATI) */
43 static u32 r128_cce_microcode[] = {
44 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
45 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
46 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
47 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
48 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
49 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
50 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
51 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
52 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
53 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
54 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
55 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
56 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
57 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
58 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
59 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
60 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
61 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
62 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
63 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
64 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
65 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
66 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
67 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
68 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
69 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
70 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
71 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
72 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
73 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
74 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
75 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
76 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
77 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
78 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
84 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
85 };
86
87
88 int R128_READ_PLL(drm_device_t *dev, int addr)
89 {
90 drm_r128_private_t *dev_priv = dev->dev_private;
91
92 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
93 return R128_READ(R128_CLOCK_CNTL_DATA);
94 }
95
96 #if R128_FIFO_DEBUG
97 static void r128_status( drm_r128_private_t *dev_priv )
98 {
99 printk( "GUI_STAT = 0x%08x\n",
100 (unsigned int)R128_READ( R128_GUI_STAT ) );
101 printk( "PM4_STAT = 0x%08x\n",
102 (unsigned int)R128_READ( R128_PM4_STAT ) );
103 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
104 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
105 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
106 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
107 printk( "PM4_MICRO_CNTL = 0x%08x\n",
108 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
109 printk( "PM4_BUFFER_CNTL = 0x%08x\n",
110 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
111 }
112 #endif
113
114
115 /* ================================================================
116 * Engine, FIFO control
117 */
118
119 static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
120 {
121 u32 tmp;
122 int i;
123
124 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
125 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
126
127 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
128 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
129 return 0;
130 }
131 udelay( 1 );
132 }
133
134 #if R128_FIFO_DEBUG
135 DRM_ERROR( "%s failed!\n", __FUNCTION__ );
136 #endif
137 return -EBUSY;
138 }
139
140 static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
141 {
142 int i;
143
144 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
145 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
146 if ( slots >= entries ) return 0;
147 udelay( 1 );
148 }
149
150 #if R128_FIFO_DEBUG
151 DRM_ERROR( "%s failed!\n", __FUNCTION__ );
152 #endif
153 return -EBUSY;
154 }
155
156 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
157 {
158 int i, ret;
159
160 ret = r128_do_wait_for_fifo( dev_priv, 64 );
161 if ( ret < 0 ) return ret;
162
163 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
164 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
165 r128_do_pixcache_flush( dev_priv );
166 return 0;
167 }
168 udelay( 1 );
169 }
170
171 #if R128_FIFO_DEBUG
172 DRM_ERROR( "%s failed!\n", __FUNCTION__ );
173 #endif
174 return -EBUSY;
175 }
176
177
178 /* ================================================================
179 * CCE control, initialization
180 */
181
182 /* Load the microcode for the CCE */
183 static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
184 {
185 int i;
186
187 DRM_DEBUG( "%s\n", __FUNCTION__ );
188
189 r128_do_wait_for_idle( dev_priv );
190
191 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
192 for ( i = 0 ; i < 256 ; i++ ) {
193 R128_WRITE( R128_PM4_MICROCODE_DATAH,
194 r128_cce_microcode[i * 2] );
195 R128_WRITE( R128_PM4_MICROCODE_DATAL,
196 r128_cce_microcode[i * 2 + 1] );
197 }
198 }
199
200 /* Flush any pending commands to the CCE. This should only be used just
201 * prior to a wait for idle, as it informs the engine that the command
202 * stream is ending.
203 */
204 static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
205 {
206 u32 tmp;
207
208 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
209 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
210 }
211
212 /* Wait for the CCE to go idle.
213 */
214 int r128_do_cce_idle( drm_r128_private_t *dev_priv )
215 {
216 int i;
217
218 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
219 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
220 int pm4stat = R128_READ( R128_PM4_STAT );
221 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
222 dev_priv->cce_fifo_size ) &&
223 !(pm4stat & (R128_PM4_BUSY |
224 R128_PM4_GUI_ACTIVE)) ) {
225 return r128_do_pixcache_flush( dev_priv );
226 }
227 }
228 udelay( 1 );
229 }
230
231 #if R128_FIFO_DEBUG
232 DRM_ERROR( "failed!\n" );
233 r128_status( dev_priv );
234 #endif
235 return -EBUSY;
236 }
237
238 /* Start the Concurrent Command Engine.
239 */
240 static void r128_do_cce_start( drm_r128_private_t *dev_priv )
241 {
242 r128_do_wait_for_idle( dev_priv );
243
244 R128_WRITE( R128_PM4_BUFFER_CNTL,
245 dev_priv->cce_mode | dev_priv->ring.size_l2qw );
246 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
247 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
248
249 dev_priv->cce_running = 1;
250 }
251
252 /* Reset the Concurrent Command Engine. This will not flush any pending
253 * commands, so you must wait for the CCE command stream to complete
254 * before calling this routine.
255 */
256 static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
257 {
258 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
259 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
260 SET_RING_HEAD( &dev_priv->ring, 0 );
261 dev_priv->ring.tail = 0;
262 }
263
264 /* Stop the Concurrent Command Engine. This will not flush any pending
265 * commands, so you must flush the command stream and wait for the CCE
266 * to go idle before calling this routine.
267 */
268 static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
269 {
270 R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
271 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
272
273 dev_priv->cce_running = 0;
274 }
275
276 /* Reset the engine. This will stop the CCE if it is running.
277 */
278 static int r128_do_engine_reset( drm_device_t *dev )
279 {
280 drm_r128_private_t *dev_priv = dev->dev_private;
281 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
282
283 r128_do_pixcache_flush( dev_priv );
284
285 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
286 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
287
288 R128_WRITE_PLL( R128_MCLK_CNTL,
289 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
290
291 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
292
293 /* Taken from the sample code - do not change */
294 R128_WRITE( R128_GEN_RESET_CNTL,
295 gen_reset_cntl | R128_SOFT_RESET_GUI );
296 R128_READ( R128_GEN_RESET_CNTL );
297 R128_WRITE( R128_GEN_RESET_CNTL,
298 gen_reset_cntl & ~R128_SOFT_RESET_GUI );
299 R128_READ( R128_GEN_RESET_CNTL );
300
301 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
302 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
303 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
304
305 /* Reset the CCE ring */
306 r128_do_cce_reset( dev_priv );
307
308 /* The CCE is no longer running after an engine reset */
309 dev_priv->cce_running = 0;
310
311 /* Reset any pending vertex, indirect buffers */
312 r128_freelist_reset( dev );
313
314 return 0;
315 }
316
317 static void r128_cce_init_ring_buffer( drm_device_t *dev,
318 drm_r128_private_t *dev_priv )
319 {
320 u32 ring_start;
321 u32 tmp;
322
323 DRM_DEBUG( "%s\n", __FUNCTION__ );
324
325 /* The manual (p. 2) says this address is in "VM space". This
326 * means it's an offset from the start of AGP space.
327 */
328 #if __REALLY_HAVE_AGP
329 if ( !dev_priv->is_pci )
330 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
331 else
332 #endif
333 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
334
335 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
336
337 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
338 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
339
340 /* DL_RPTR_ADDR is a physical address in AGP space. */
341 SET_RING_HEAD( &dev_priv->ring, 0 );
342
343 if ( !dev_priv->is_pci ) {
344 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
345 dev_priv->ring_rptr->offset );
346 } else {
347 drm_sg_mem_t *entry = dev->sg;
348 unsigned long tmp_ofs, page_ofs;
349
350 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
351 page_ofs = tmp_ofs >> PAGE_SHIFT;
352
353 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
354 entry->busaddr[page_ofs]);
355 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
356 entry->busaddr[page_ofs],
357 entry->handle + tmp_ofs );
358 }
359
360 /* Set watermark control */
361 R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
362 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
363 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
364 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
365 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
366
367 /* Force read. Why? Because it's in the examples... */
368 R128_READ( R128_PM4_BUFFER_ADDR );
369
370 /* Turn on bus mastering */
371 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
372 R128_WRITE( R128_BUS_CNTL, tmp );
373 }
374
375 static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
376 {
377 drm_r128_private_t *dev_priv;
378 struct list_head *list;
379
380 DRM_DEBUG( "%s\n", __FUNCTION__ );
381
382 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
383 if ( dev_priv == NULL )
384 return -ENOMEM;
385
386 memset( dev_priv, 0, sizeof(drm_r128_private_t) );
387
388 dev_priv->is_pci = init->is_pci;
389
390 if ( dev_priv->is_pci && !dev->sg ) {
391 DRM_ERROR( "PCI GART memory not allocated!\n" );
392 dev->dev_private = (void *)dev_priv;
393 r128_do_cleanup_cce( dev );
394 return -EINVAL;
395 }
396
397 dev_priv->usec_timeout = init->usec_timeout;
398 if ( dev_priv->usec_timeout < 1 ||
399 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
400 DRM_DEBUG( "TIMEOUT problem!\n" );
401 dev->dev_private = (void *)dev_priv;
402 r128_do_cleanup_cce( dev );
403 return -EINVAL;
404 }
405
406 dev_priv->cce_mode = init->cce_mode;
407
408 /* GH: Simple idle check.
409 */
410 atomic_set( &dev_priv->idle_count, 0 );
411
412 /* We don't support anything other than bus-mastering ring mode,
413 * but the ring can be in either AGP or PCI space for the ring
414 * read pointer.
415 */
416 if ( ( init->cce_mode != R128_PM4_192BM ) &&
417 ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
418 ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
419 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
420 DRM_DEBUG( "Bad cce_mode!\n" );
421 dev->dev_private = (void *)dev_priv;
422 r128_do_cleanup_cce( dev );
423 return -EINVAL;
424 }
425
426 switch ( init->cce_mode ) {
427 case R128_PM4_NONPM4:
428 dev_priv->cce_fifo_size = 0;
429 break;
430 case R128_PM4_192PIO:
431 case R128_PM4_192BM:
432 dev_priv->cce_fifo_size = 192;
433 break;
434 case R128_PM4_128PIO_64INDBM:
435 case R128_PM4_128BM_64INDBM:
436 dev_priv->cce_fifo_size = 128;
437 break;
438 case R128_PM4_64PIO_128INDBM:
439 case R128_PM4_64BM_128INDBM:
440 case R128_PM4_64PIO_64VCBM_64INDBM:
441 case R128_PM4_64BM_64VCBM_64INDBM:
442 case R128_PM4_64PIO_64VCPIO_64INDPIO:
443 dev_priv->cce_fifo_size = 64;
444 break;
445 }
446
447 switch ( init->fb_bpp ) {
448 case 16:
449 dev_priv->color_fmt = R128_DATATYPE_RGB565;
450 break;
451 case 32:
452 default:
453 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
454 break;
455 }
456 dev_priv->front_offset = init->front_offset;
457 dev_priv->front_pitch = init->front_pitch;
458 dev_priv->back_offset = init->back_offset;
459 dev_priv->back_pitch = init->back_pitch;
460
461 switch ( init->depth_bpp ) {
462 case 16:
463 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
464 break;
465 case 24:
466 case 32:
467 default:
468 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
469 break;
470 }
471 dev_priv->depth_offset = init->depth_offset;
472 dev_priv->depth_pitch = init->depth_pitch;
473 dev_priv->span_offset = init->span_offset;
474
475 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
476 (dev_priv->front_offset >> 5));
477 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
478 (dev_priv->back_offset >> 5));
479 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
480 (dev_priv->depth_offset >> 5) |
481 R128_DST_TILE);
482 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
483 (dev_priv->span_offset >> 5));
484
485 list_for_each(list, &dev->maplist->head) {
486 drm_map_list_t *r_list = (drm_map_list_t *)list;
487 if( r_list->map &&
488 r_list->map->type == _DRM_SHM &&
489 r_list->map->flags & _DRM_CONTAINS_LOCK ) {
490 dev_priv->sarea = r_list->map;
491 break;
492 }
493 }
494 if(!dev_priv->sarea) {
495 DRM_ERROR("could not find sarea!\n");
496 dev->dev_private = (void *)dev_priv;
497 r128_do_cleanup_cce( dev );
498 return -EINVAL;
499 }
500
501 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
502 if(!dev_priv->fb) {
503 DRM_ERROR("could not find framebuffer!\n");
504 dev->dev_private = (void *)dev_priv;
505 r128_do_cleanup_cce( dev );
506 return -EINVAL;
507 }
508 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
509 if(!dev_priv->mmio) {
510 DRM_ERROR("could not find mmio region!\n");
511 dev->dev_private = (void *)dev_priv;
512 r128_do_cleanup_cce( dev );
513 return -EINVAL;
514 }
515 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
516 if(!dev_priv->cce_ring) {
517 DRM_ERROR("could not find cce ring region!\n");
518 dev->dev_private = (void *)dev_priv;
519 r128_do_cleanup_cce( dev );
520 return -EINVAL;
521 }
522 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
523 if(!dev_priv->ring_rptr) {
524 DRM_ERROR("could not find ring read pointer!\n");
525 dev->dev_private = (void *)dev_priv;
526 r128_do_cleanup_cce( dev );
527 return -EINVAL;
528 }
529 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
530 if(!dev_priv->buffers) {
531 DRM_ERROR("could not find dma buffer region!\n");
532 dev->dev_private = (void *)dev_priv;
533 r128_do_cleanup_cce( dev );
534 return -EINVAL;
535 }
536
537 if ( !dev_priv->is_pci ) {
538 DRM_FIND_MAP( dev_priv->agp_textures,
539 init->agp_textures_offset );
540 if(!dev_priv->agp_textures) {
541 DRM_ERROR("could not find agp texture region!\n");
542 dev->dev_private = (void *)dev_priv;
543 r128_do_cleanup_cce( dev );
544 return -EINVAL;
545 }
546 }
547
548 dev_priv->sarea_priv =
549 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
550 init->sarea_priv_offset);
551
552 if ( !dev_priv->is_pci ) {
553 DRM_IOREMAP( dev_priv->cce_ring );
554 DRM_IOREMAP( dev_priv->ring_rptr );
555 DRM_IOREMAP( dev_priv->buffers );
556 if(!dev_priv->cce_ring->handle ||
557 !dev_priv->ring_rptr->handle ||
558 !dev_priv->buffers->handle) {
559 DRM_ERROR("Could not ioremap agp regions!\n");
560 dev->dev_private = (void *)dev_priv;
561 r128_do_cleanup_cce( dev );
562 return -ENOMEM;
563 }
564 } else {
565 dev_priv->cce_ring->handle =
566 (void *)dev_priv->cce_ring->offset;
567 dev_priv->ring_rptr->handle =
568 (void *)dev_priv->ring_rptr->offset;
569 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
570 }
571
572 #if __REALLY_HAVE_AGP
573 if ( !dev_priv->is_pci )
574 dev_priv->cce_buffers_offset = dev->agp->base;
575 else
576 #endif
577 dev_priv->cce_buffers_offset = dev->sg->handle;
578
579 dev_priv->ring.head = ((__volatile__ u32 *)
580 dev_priv->ring_rptr->handle);
581
582 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
583 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
584 + init->ring_size / sizeof(u32));
585 dev_priv->ring.size = init->ring_size;
586 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
587
588 dev_priv->ring.tail_mask =
589 (dev_priv->ring.size / sizeof(u32)) - 1;
590
591 dev_priv->ring.high_mark = 128;
592
593 dev_priv->sarea_priv->last_frame = 0;
594 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
595
596 dev_priv->sarea_priv->last_dispatch = 0;
597 R128_WRITE( R128_LAST_DISPATCH_REG,
598 dev_priv->sarea_priv->last_dispatch );
599
600 if ( dev_priv->is_pci ) {
601 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
602 &dev_priv->bus_pci_gart) ) {
603 DRM_ERROR( "failed to init PCI GART!\n" );
604 dev->dev_private = (void *)dev_priv;
605 r128_do_cleanup_cce( dev );
606 return -ENOMEM;
607 }
608 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
609 }
610
611 r128_cce_init_ring_buffer( dev, dev_priv );
612 r128_cce_load_microcode( dev_priv );
613
614 dev->dev_private = (void *)dev_priv;
615
616 r128_do_engine_reset( dev );
617
618 return 0;
619 }
620
621 int r128_do_cleanup_cce( drm_device_t *dev )
622 {
623 if ( dev->dev_private ) {
624 drm_r128_private_t *dev_priv = dev->dev_private;
625
626 if ( !dev_priv->is_pci ) {
627 DRM_IOREMAPFREE( dev_priv->cce_ring );
628 DRM_IOREMAPFREE( dev_priv->ring_rptr );
629 DRM_IOREMAPFREE( dev_priv->buffers );
630 } else {
631 if (!DRM(ati_pcigart_cleanup)( dev,
632 dev_priv->phys_pci_gart,
633 dev_priv->bus_pci_gart ))
634 DRM_ERROR( "failed to cleanup PCI GART!\n" );
635 }
636
637 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
638 DRM_MEM_DRIVER );
639 dev->dev_private = NULL;
640 }
641
642 return 0;
643 }
644
645 int r128_cce_init( struct inode *inode, struct file *filp,
646 unsigned int cmd, unsigned long arg )
647 {
648 drm_file_t *priv = filp->private_data;
649 drm_device_t *dev = priv->dev;
650 drm_r128_init_t init;
651
652 DRM_DEBUG( "%s\n", __FUNCTION__ );
653
654 if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) )
655 return -EFAULT;
656
657 switch ( init.func ) {
658 case R128_INIT_CCE:
659 return r128_do_init_cce( dev, &init );
660 case R128_CLEANUP_CCE:
661 return r128_do_cleanup_cce( dev );
662 }
663
664 return -EINVAL;
665 }
666
667 int r128_cce_start( struct inode *inode, struct file *filp,
668 unsigned int cmd, unsigned long arg )
669 {
670 drm_file_t *priv = filp->private_data;
671 drm_device_t *dev = priv->dev;
672 drm_r128_private_t *dev_priv = dev->dev_private;
673 DRM_DEBUG( "%s\n", __FUNCTION__ );
674
675 LOCK_TEST_WITH_RETURN( dev );
676
677 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
678 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
679 return 0;
680 }
681
682 r128_do_cce_start( dev_priv );
683
684 return 0;
685 }
686
687 /* Stop the CCE. The engine must have been idled before calling this
688 * routine.
689 */
690 int r128_cce_stop( struct inode *inode, struct file *filp,
691 unsigned int cmd, unsigned long arg )
692 {
693 drm_file_t *priv = filp->private_data;
694 drm_device_t *dev = priv->dev;
695 drm_r128_private_t *dev_priv = dev->dev_private;
696 drm_r128_cce_stop_t stop;
697 int ret;
698 DRM_DEBUG( "%s\n", __FUNCTION__ );
699
700 LOCK_TEST_WITH_RETURN( dev );
701
702 if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) )
703 return -EFAULT;
704
705 /* Flush any pending CCE commands. This ensures any outstanding
706 * commands are exectuted by the engine before we turn it off.
707 */
708 if ( stop.flush ) {
709 r128_do_cce_flush( dev_priv );
710 }
711
712 /* If we fail to make the engine go idle, we return an error
713 * code so that the DRM ioctl wrapper can try again.
714 */
715 if ( stop.idle ) {
716 ret = r128_do_cce_idle( dev_priv );
717 if ( ret < 0 ) return ret;
718 }
719
720 /* Finally, we can turn off the CCE. If the engine isn't idle,
721 * we will get some dropped triangles as they won't be fully
722 * rendered before the CCE is shut down.
723 */
724 r128_do_cce_stop( dev_priv );
725
726 /* Reset the engine */
727 r128_do_engine_reset( dev );
728
729 return 0;
730 }
731
732 /* Just reset the CCE ring. Called as part of an X Server engine reset.
733 */
734 int r128_cce_reset( struct inode *inode, struct file *filp,
735 unsigned int cmd, unsigned long arg )
736 {
737 drm_file_t *priv = filp->private_data;
738 drm_device_t *dev = priv->dev;
739 drm_r128_private_t *dev_priv = dev->dev_private;
740 DRM_DEBUG( "%s\n", __FUNCTION__ );
741
742 LOCK_TEST_WITH_RETURN( dev );
743
744 if ( !dev_priv ) {
745 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
746 return -EINVAL;
747 }
748
749 r128_do_cce_reset( dev_priv );
750
751 /* The CCE is no longer running after an engine reset */
752 dev_priv->cce_running = 0;
753
754 return 0;
755 }
756
757 int r128_cce_idle( struct inode *inode, struct file *filp,
758 unsigned int cmd, unsigned long arg )
759 {
760 drm_file_t *priv = filp->private_data;
761 drm_device_t *dev = priv->dev;
762 drm_r128_private_t *dev_priv = dev->dev_private;
763 DRM_DEBUG( "%s\n", __FUNCTION__ );
764
765 LOCK_TEST_WITH_RETURN( dev );
766
767 if ( dev_priv->cce_running ) {
768 r128_do_cce_flush( dev_priv );
769 }
770
771 return r128_do_cce_idle( dev_priv );
772 }
773
774 int r128_engine_reset( struct inode *inode, struct file *filp,
775 unsigned int cmd, unsigned long arg )
776 {
777 drm_file_t *priv = filp->private_data;
778 drm_device_t *dev = priv->dev;
779 DRM_DEBUG( "%s\n", __FUNCTION__ );
780
781 LOCK_TEST_WITH_RETURN( dev );
782
783 return r128_do_engine_reset( dev );
784 }
785
786
787 /* ================================================================
788 * Fullscreen mode
789 */
790
791 static int r128_do_init_pageflip( drm_device_t *dev )
792 {
793 drm_r128_private_t *dev_priv = dev->dev_private;
794 DRM_DEBUG( "%s\n", __FUNCTION__ );
795
796 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET );
797 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
798
799 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
800 R128_WRITE( R128_CRTC_OFFSET_CNTL,
801 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
802
803 dev_priv->page_flipping = 1;
804 dev_priv->current_page = 0;
805
806 return 0;
807 }
808
809 int r128_do_cleanup_pageflip( drm_device_t *dev )
810 {
811 drm_r128_private_t *dev_priv = dev->dev_private;
812 DRM_DEBUG( "%s\n", __FUNCTION__ );
813
814 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
815 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
816
817 dev_priv->page_flipping = 0;
818 dev_priv->current_page = 0;
819
820 return 0;
821 }
822
823 int r128_fullscreen( struct inode *inode, struct file *filp,
824 unsigned int cmd, unsigned long arg )
825 {
826 drm_file_t *priv = filp->private_data;
827 drm_device_t *dev = priv->dev;
828 drm_r128_fullscreen_t fs;
829
830 LOCK_TEST_WITH_RETURN( dev );
831
832 if ( copy_from_user( &fs, (drm_r128_fullscreen_t *)arg, sizeof(fs) ) )
833 return -EFAULT;
834
835 switch ( fs.func ) {
836 case R128_INIT_FULLSCREEN:
837 return r128_do_init_pageflip( dev );
838 case R128_CLEANUP_FULLSCREEN:
839 return r128_do_cleanup_pageflip( dev );
840 }
841
842 return -EINVAL;
843 }
844
845
846 /* ================================================================
847 * Freelist management
848 */
849 #define R128_BUFFER_USED 0xffffffff
850 #define R128_BUFFER_FREE 0
851
852 #if 0
853 static int r128_freelist_init( drm_device_t *dev )
854 {
855 drm_device_dma_t *dma = dev->dma;
856 drm_r128_private_t *dev_priv = dev->dev_private;
857 drm_buf_t *buf;
858 drm_r128_buf_priv_t *buf_priv;
859 drm_r128_freelist_t *entry;
860 int i;
861
862 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
863 DRM_MEM_DRIVER );
864 if ( dev_priv->head == NULL )
865 return -ENOMEM;
866
867 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
868 dev_priv->head->age = R128_BUFFER_USED;
869
870 for ( i = 0 ; i < dma->buf_count ; i++ ) {
871 buf = dma->buflist[i];
872 buf_priv = buf->dev_private;
873
874 entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
875 DRM_MEM_DRIVER );
876 if ( !entry ) return -ENOMEM;
877
878 entry->age = R128_BUFFER_FREE;
879 entry->buf = buf;
880 entry->prev = dev_priv->head;
881 entry->next = dev_priv->head->next;
882 if ( !entry->next )
883 dev_priv->tail = entry;
884
885 buf_priv->discard = 0;
886 buf_priv->dispatched = 0;
887 buf_priv->list_entry = entry;
888
889 dev_priv->head->next = entry;
890
891 if ( dev_priv->head->next )
892 dev_priv->head->next->prev = entry;
893 }
894
895 return 0;
896
897 }
898 #endif
899
900 drm_buf_t *r128_freelist_get( drm_device_t *dev )
901 {
902 drm_device_dma_t *dma = dev->dma;
903 drm_r128_private_t *dev_priv = dev->dev_private;
904 drm_r128_buf_priv_t *buf_priv;
905 drm_buf_t *buf;
906 int i, t;
907
908 /* FIXME: Optimize -- use freelist code */
909
910 for ( i = 0 ; i < dma->buf_count ; i++ ) {
911 buf = dma->buflist[i];
912 buf_priv = buf->dev_private;
913 if ( buf->pid == 0 )
914 return buf;
915 }
916
917 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
918 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
919
920 for ( i = 0 ; i < dma->buf_count ; i++ ) {
921 buf = dma->buflist[i];
922 buf_priv = buf->dev_private;
923 if ( buf->pending && buf_priv->age <= done_age ) {
924 /* The buffer has been processed, so it
925 * can now be used.
926 */
927 buf->pending = 0;
928 return buf;
929 }
930 }
931 udelay( 1 );
932 }
933
934 DRM_ERROR( "returning NULL!\n" );
935 return NULL;
936 }
937
938 void r128_freelist_reset( drm_device_t *dev )
939 {
940 drm_device_dma_t *dma = dev->dma;
941 int i;
942
943 for ( i = 0 ; i < dma->buf_count ; i++ ) {
944 drm_buf_t *buf = dma->buflist[i];
945 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
946 buf_priv->age = 0;
947 }
948 }
949
950
951 /* ================================================================
952 * CCE command submission
953 */
954
955 int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
956 {
957 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
958 int i;
959
960 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
961 r128_update_ring_snapshot( ring );
962 if ( ring->space >= n )
963 return 0;
964 udelay( 1 );
965 }
966
967 /* FIXME: This is being ignored... */
968 DRM_ERROR( "failed!\n" );
969 return -EBUSY;
970 }
971
972 static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
973 {
974 int i;
975 drm_buf_t *buf;
976
977 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
978 buf = r128_freelist_get( dev );
979 if ( !buf ) return -EAGAIN;
980
981 buf->pid = current->pid;
982
983 if ( copy_to_user( &d->request_indices[i], &buf->idx,
984 sizeof(buf->idx) ) )
985 return -EFAULT;
986 if ( copy_to_user( &d->request_sizes[i], &buf->total,
987 sizeof(buf->total) ) )
988 return -EFAULT;
989
990 d->granted_count++;
991 }
992 return 0;
993 }
994
995 int r128_cce_buffers( struct inode *inode, struct file *filp,
996 unsigned int cmd, unsigned long arg )
997 {
998 drm_file_t *priv = filp->private_data;
999 drm_device_t *dev = priv->dev;
1000 drm_device_dma_t *dma = dev->dma;
1001 int ret = 0;
1002 drm_dma_t d;
1003
1004 LOCK_TEST_WITH_RETURN( dev );
1005
1006 if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
1007 return -EFAULT;
1008
1009 /* Please don't send us buffers.
1010 */
1011 if ( d.send_count != 0 ) {
1012 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1013 current->pid, d.send_count );
1014 return -EINVAL;
1015 }
1016
1017 /* We'll send you buffers.
1018 */
1019 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1020 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1021 current->pid, d.request_count, dma->buf_count );
1022 return -EINVAL;
1023 }
1024
1025 d.granted_count = 0;
1026
1027 if ( d.request_count ) {
1028 ret = r128_cce_get_buffers( dev, &d );
1029 }
1030
1031 if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
1032 return -EFAULT;
1033
1034 return ret;
1035 }
1036