File: /usr/src/linux/drivers/char/drm/radeon_drv.h
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 typedef struct drm_radeon_freelist {
35 unsigned int age;
36 drm_buf_t *buf;
37 struct drm_radeon_freelist *next;
38 struct drm_radeon_freelist *prev;
39 } drm_radeon_freelist_t;
40
41 typedef struct drm_radeon_ring_buffer {
42 u32 *start;
43 u32 *end;
44 int size;
45 int size_l2qw;
46
47 volatile u32 *head;
48 u32 tail;
49 u32 tail_mask;
50 int space;
51
52 int high_mark;
53 } drm_radeon_ring_buffer_t;
54
55 typedef struct drm_radeon_depth_clear_t {
56 u32 rb3d_cntl;
57 u32 rb3d_zstencilcntl;
58 u32 se_cntl;
59 } drm_radeon_depth_clear_t;
60
61 typedef struct drm_radeon_private {
62 drm_radeon_ring_buffer_t ring;
63 drm_radeon_sarea_t *sarea_priv;
64
65 int agp_size;
66 u32 agp_vm_start;
67 unsigned long agp_buffers_offset;
68
69 int cp_mode;
70 int cp_running;
71
72 drm_radeon_freelist_t *head;
73 drm_radeon_freelist_t *tail;
74 /* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
75 code is used. Note this hides a problem with the scratch register
76 (used to keep track of last buffer completed) being written to before
77 the last buffer has actually completed rendering. */
78 #define ROTATE_BUFS 1
79 #if ROTATE_BUFS
80 int last_buf;
81 #endif
82 volatile u32 *scratch;
83
84 int usec_timeout;
85 int is_pci;
86 unsigned long phys_pci_gart;
87 dma_addr_t bus_pci_gart;
88
89 atomic_t idle_count;
90
91 int page_flipping;
92 int current_page;
93 u32 crtc_offset;
94 u32 crtc_offset_cntl;
95
96 u32 color_fmt;
97 unsigned int front_offset;
98 unsigned int front_pitch;
99 unsigned int back_offset;
100 unsigned int back_pitch;
101
102 u32 depth_fmt;
103 unsigned int depth_offset;
104 unsigned int depth_pitch;
105
106 u32 front_pitch_offset;
107 u32 back_pitch_offset;
108 u32 depth_pitch_offset;
109
110 drm_radeon_depth_clear_t depth_clear;
111
112 drm_map_t *sarea;
113 drm_map_t *fb;
114 drm_map_t *mmio;
115 drm_map_t *cp_ring;
116 drm_map_t *ring_rptr;
117 drm_map_t *buffers;
118 drm_map_t *agp_textures;
119 } drm_radeon_private_t;
120
121 typedef struct drm_radeon_buf_priv {
122 u32 age;
123 int prim;
124 int discard;
125 int dispatched;
126 drm_radeon_freelist_t *list_entry;
127 } drm_radeon_buf_priv_t;
128
129 /* radeon_cp.c */
130 extern int radeon_cp_init( struct inode *inode, struct file *filp,
131 unsigned int cmd, unsigned long arg );
132 extern int radeon_cp_start( struct inode *inode, struct file *filp,
133 unsigned int cmd, unsigned long arg );
134 extern int radeon_cp_stop( struct inode *inode, struct file *filp,
135 unsigned int cmd, unsigned long arg );
136 extern int radeon_cp_reset( struct inode *inode, struct file *filp,
137 unsigned int cmd, unsigned long arg );
138 extern int radeon_cp_idle( struct inode *inode, struct file *filp,
139 unsigned int cmd, unsigned long arg );
140 extern int radeon_engine_reset( struct inode *inode, struct file *filp,
141 unsigned int cmd, unsigned long arg );
142 extern int radeon_fullscreen( struct inode *inode, struct file *filp,
143 unsigned int cmd, unsigned long arg );
144 extern int radeon_cp_buffers( struct inode *inode, struct file *filp,
145 unsigned int cmd, unsigned long arg );
146
147 extern void radeon_freelist_reset( drm_device_t *dev );
148 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
149
150 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
151
152 static inline void
153 radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
154 {
155 ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);
156 if ( ring->space <= 0 )
157 ring->space += ring->size;
158 }
159
160 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
161 extern int radeon_do_cleanup_cp( drm_device_t *dev );
162 extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
163
164 /* radeon_state.c */
165 extern int radeon_cp_clear( struct inode *inode, struct file *filp,
166 unsigned int cmd, unsigned long arg );
167 extern int radeon_cp_swap( struct inode *inode, struct file *filp,
168 unsigned int cmd, unsigned long arg );
169 extern int radeon_cp_vertex( struct inode *inode, struct file *filp,
170 unsigned int cmd, unsigned long arg );
171 extern int radeon_cp_indices( struct inode *inode, struct file *filp,
172 unsigned int cmd, unsigned long arg );
173 extern int radeon_cp_texture( struct inode *inode, struct file *filp,
174 unsigned int cmd, unsigned long arg );
175 extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
176 unsigned int cmd, unsigned long arg );
177 extern int radeon_cp_indirect( struct inode *inode, struct file *filp,
178 unsigned int cmd, unsigned long arg );
179
180
181 /* Register definitions, register access macros and drmAddMap constants
182 * for Radeon kernel driver.
183 */
184
185 #define RADEON_AGP_COMMAND 0x0f60
186 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
187 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
188 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
189 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
190 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
191 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
192 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
193
194 #define RADEON_BUS_CNTL 0x0030
195 # define RADEON_BUS_MASTER_DIS (1 << 6)
196
197 #define RADEON_CLOCK_CNTL_DATA 0x000c
198 # define RADEON_PLL_WR_EN (1 << 7)
199 #define RADEON_CLOCK_CNTL_INDEX 0x0008
200 #define RADEON_CONFIG_APER_SIZE 0x0108
201 #define RADEON_CRTC_OFFSET 0x0224
202 #define RADEON_CRTC_OFFSET_CNTL 0x0228
203 # define RADEON_CRTC_TILE_EN (1 << 15)
204 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
205
206 #define RADEON_RB3D_COLORPITCH 0x1c48
207 #define RADEON_RB3D_DEPTHCLEARVALUE 0x1c30
208 #define RADEON_RB3D_DEPTHXY_OFFSET 0x1c60
209
210 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
211 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
212 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
213 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
214 # define RADEON_GMC_BRUSH_NONE (15 << 4)
215 # define RADEON_GMC_DST_16BPP (4 << 8)
216 # define RADEON_GMC_DST_24BPP (5 << 8)
217 # define RADEON_GMC_DST_32BPP (6 << 8)
218 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
219 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
220 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
221 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
222 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
223 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
224 # define RADEON_ROP3_S 0x00cc0000
225 # define RADEON_ROP3_P 0x00f00000
226 #define RADEON_DP_WRITE_MASK 0x16cc
227 #define RADEON_DST_PITCH_OFFSET 0x142c
228 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
229 # define RADEON_DST_TILE_LINEAR (0 << 30)
230 # define RADEON_DST_TILE_MACRO (1 << 30)
231 # define RADEON_DST_TILE_MICRO (2 << 30)
232 # define RADEON_DST_TILE_BOTH (3 << 30)
233
234 #define RADEON_SCRATCH_REG0 0x15e0
235 #define RADEON_SCRATCH_REG1 0x15e4
236 #define RADEON_SCRATCH_REG2 0x15e8
237 #define RADEON_SCRATCH_REG3 0x15ec
238 #define RADEON_SCRATCH_REG4 0x15f0
239 #define RADEON_SCRATCH_REG5 0x15f4
240 #define RADEON_SCRATCH_UMSK 0x0770
241 #define RADEON_SCRATCH_ADDR 0x0774
242
243 #define RADEON_HOST_PATH_CNTL 0x0130
244 # define RADEON_HDP_SOFT_RESET (1 << 26)
245 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
246 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
247
248 #define RADEON_ISYNC_CNTL 0x1724
249 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
250 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
251 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
252 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
253 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
254 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
255
256 #define RADEON_MC_AGP_LOCATION 0x014c
257 #define RADEON_MC_FB_LOCATION 0x0148
258 #define RADEON_MCLK_CNTL 0x0012
259 # define RADEON_FORCEON_MCLKA (1 << 16)
260 # define RADEON_FORCEON_MCLKB (1 << 17)
261 # define RADEON_FORCEON_YCLKA (1 << 18)
262 # define RADEON_FORCEON_YCLKB (1 << 19)
263 # define RADEON_FORCEON_MC (1 << 20)
264 # define RADEON_FORCEON_AIC (1 << 21)
265
266 #define RADEON_PP_BORDER_COLOR_0 0x1d40
267 #define RADEON_PP_BORDER_COLOR_1 0x1d44
268 #define RADEON_PP_BORDER_COLOR_2 0x1d48
269 #define RADEON_PP_CNTL 0x1c38
270 # define RADEON_SCISSOR_ENABLE (1 << 1)
271 #define RADEON_PP_LUM_MATRIX 0x1d00
272 #define RADEON_PP_MISC 0x1c14
273 #define RADEON_PP_ROT_MATRIX_0 0x1d58
274 #define RADEON_PP_TXFILTER_0 0x1c54
275 #define RADEON_PP_TXFILTER_1 0x1c6c
276 #define RADEON_PP_TXFILTER_2 0x1c84
277
278 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
279 # define RADEON_RB2D_DC_FLUSH (3 << 0)
280 # define RADEON_RB2D_DC_FREE (3 << 2)
281 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
282 # define RADEON_RB2D_DC_BUSY (1 << 31)
283 #define RADEON_RB3D_CNTL 0x1c3c
284 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
285 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
286 # define RADEON_DITHER_ENABLE (1 << 2)
287 # define RADEON_ROUND_ENABLE (1 << 3)
288 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
289 # define RADEON_DITHER_INIT (1 << 5)
290 # define RADEON_ROP_ENABLE (1 << 6)
291 # define RADEON_STENCIL_ENABLE (1 << 7)
292 # define RADEON_Z_ENABLE (1 << 8)
293 # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
294 # define RADEON_ZBLOCK8 (0 << 15)
295 # define RADEON_ZBLOCK16 (1 << 15)
296 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
297 #define RADEON_RB3D_PLANEMASK 0x1d84
298 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
299 #define RADEON_RB3D_ZCACHE_MODE 0x3250
300 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
301 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
302 # define RADEON_RB3D_ZC_FREE (1 << 2)
303 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
304 # define RADEON_RB3D_ZC_BUSY (1 << 31)
305 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
306 # define RADEON_Z_TEST_MASK (7 << 4)
307 # define RADEON_Z_TEST_ALWAYS (7 << 4)
308 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
309 # define RADEON_STENCIL_S_FAIL_KEEP (0 << 16)
310 # define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
311 # define RADEON_STENCIL_ZFAIL_KEEP (0 << 20)
312 # define RADEON_Z_WRITE_ENABLE (1 << 30)
313 #define RADEON_RBBM_SOFT_RESET 0x00f0
314 # define RADEON_SOFT_RESET_CP (1 << 0)
315 # define RADEON_SOFT_RESET_HI (1 << 1)
316 # define RADEON_SOFT_RESET_SE (1 << 2)
317 # define RADEON_SOFT_RESET_RE (1 << 3)
318 # define RADEON_SOFT_RESET_PP (1 << 4)
319 # define RADEON_SOFT_RESET_E2 (1 << 5)
320 # define RADEON_SOFT_RESET_RB (1 << 6)
321 # define RADEON_SOFT_RESET_HDP (1 << 7)
322 #define RADEON_RBBM_STATUS 0x0e40
323 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
324 # define RADEON_RBBM_ACTIVE (1 << 31)
325 #define RADEON_RE_LINE_PATTERN 0x1cd0
326 #define RADEON_RE_MISC 0x26c4
327 #define RADEON_RE_TOP_LEFT 0x26c0
328 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
329 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
330 #define RADEON_RE_STIPPLE_DATA 0x1ccc
331
332 #define RADEON_SCISSOR_TL_0 0x1cd8
333 #define RADEON_SCISSOR_BR_0 0x1cdc
334 #define RADEON_SCISSOR_TL_1 0x1ce0
335 #define RADEON_SCISSOR_BR_1 0x1ce4
336 #define RADEON_SCISSOR_TL_2 0x1ce8
337 #define RADEON_SCISSOR_BR_2 0x1cec
338 #define RADEON_SE_COORD_FMT 0x1c50
339 #define RADEON_SE_CNTL 0x1c4c
340 # define RADEON_FFACE_CULL_CW (0 << 0)
341 # define RADEON_BFACE_SOLID (3 << 1)
342 # define RADEON_FFACE_SOLID (3 << 3)
343 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
344 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
345 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
346 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
347 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
348 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
349 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
350 # define RADEON_FOG_SHADE_FLAT (1 << 14)
351 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
352 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
353 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
354 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
355 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
356 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
357 #define RADEON_SE_CNTL_STATUS 0x2140
358 #define RADEON_SE_LINE_WIDTH 0x1db8
359 #define RADEON_SE_VPORT_XSCALE 0x1d98
360 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
361 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
362 #define RADEON_SURFACE_CNTL 0x0b00
363 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
364 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
365 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
366 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
367 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
368 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
369 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
370 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
371 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
372 #define RADEON_SURFACE0_INFO 0x0b0c
373 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
374 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
375 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
376 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
377 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
378 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
379 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
380 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
381 #define RADEON_SURFACE1_INFO 0x0b1c
382 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
383 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
384 #define RADEON_SURFACE2_INFO 0x0b2c
385 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
386 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
387 #define RADEON_SURFACE3_INFO 0x0b3c
388 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
389 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
390 #define RADEON_SURFACE4_INFO 0x0b4c
391 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
392 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
393 #define RADEON_SURFACE5_INFO 0x0b5c
394 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
395 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
396 #define RADEON_SURFACE6_INFO 0x0b6c
397 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
398 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
399 #define RADEON_SURFACE7_INFO 0x0b7c
400 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
401 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
402 #define RADEON_SW_SEMAPHORE 0x013c
403
404 #define RADEON_WAIT_UNTIL 0x1720
405 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
406 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
407 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
408 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
409
410 #define RADEON_RB3D_ZMASKOFFSET 0x1c34
411 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
412 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
413 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
414
415
416 /* CP registers */
417 #define RADEON_CP_ME_RAM_ADDR 0x07d4
418 #define RADEON_CP_ME_RAM_RADDR 0x07d8
419 #define RADEON_CP_ME_RAM_DATAH 0x07dc
420 #define RADEON_CP_ME_RAM_DATAL 0x07e0
421
422 #define RADEON_CP_RB_BASE 0x0700
423 #define RADEON_CP_RB_CNTL 0x0704
424 #define RADEON_CP_RB_RPTR_ADDR 0x070c
425 #define RADEON_CP_RB_RPTR 0x0710
426 #define RADEON_CP_RB_WPTR 0x0714
427
428 #define RADEON_CP_RB_WPTR_DELAY 0x0718
429 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
430 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
431
432 #define RADEON_CP_IB_BASE 0x0738
433
434 #define RADEON_CP_CSQ_CNTL 0x0740
435 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
436 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
437 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
438 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
439 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
440 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
441 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
442
443 #define RADEON_AIC_CNTL 0x01d0
444 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
445 #define RADEON_AIC_STAT 0x01d4
446 #define RADEON_AIC_PT_BASE 0x01d8
447 #define RADEON_AIC_LO_ADDR 0x01dc
448 #define RADEON_AIC_HI_ADDR 0x01e0
449 #define RADEON_AIC_TLB_ADDR 0x01e4
450 #define RADEON_AIC_TLB_DATA 0x01e8
451
452 /* CP command packets */
453 #define RADEON_CP_PACKET0 0x00000000
454 # define RADEON_ONE_REG_WR (1 << 15)
455 #define RADEON_CP_PACKET1 0x40000000
456 #define RADEON_CP_PACKET2 0x80000000
457 #define RADEON_CP_PACKET3 0xC0000000
458 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
459 # define RADEON_WAIT_FOR_IDLE 0x00002600
460 # define RADEON_3D_DRAW_IMMD 0x00002900
461 # define RADEON_3D_CLEAR_ZMASK 0x00003200
462 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
463 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
464 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
465
466 #define RADEON_CP_PACKET_MASK 0xC0000000
467 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
468 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
469 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
470 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
471
472 #define RADEON_VTX_Z_PRESENT (1 << 31)
473
474 #define RADEON_PRIM_TYPE_NONE (0 << 0)
475 #define RADEON_PRIM_TYPE_POINT (1 << 0)
476 #define RADEON_PRIM_TYPE_LINE (2 << 0)
477 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
478 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
479 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
480 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
481 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
482 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
483 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
484 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
485 #define RADEON_PRIM_WALK_IND (1 << 4)
486 #define RADEON_PRIM_WALK_LIST (2 << 4)
487 #define RADEON_PRIM_WALK_RING (3 << 4)
488 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
489 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
490 #define RADEON_MAOS_ENABLE (1 << 7)
491 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
492 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
493 #define RADEON_NUM_VERTICES_SHIFT 16
494
495 #define RADEON_COLOR_FORMAT_CI8 2
496 #define RADEON_COLOR_FORMAT_ARGB1555 3
497 #define RADEON_COLOR_FORMAT_RGB565 4
498 #define RADEON_COLOR_FORMAT_ARGB8888 6
499 #define RADEON_COLOR_FORMAT_RGB332 7
500 #define RADEON_COLOR_FORMAT_RGB8 9
501 #define RADEON_COLOR_FORMAT_ARGB4444 15
502
503 #define RADEON_TXFORMAT_I8 0
504 #define RADEON_TXFORMAT_AI88 1
505 #define RADEON_TXFORMAT_RGB332 2
506 #define RADEON_TXFORMAT_ARGB1555 3
507 #define RADEON_TXFORMAT_RGB565 4
508 #define RADEON_TXFORMAT_ARGB4444 5
509 #define RADEON_TXFORMAT_ARGB8888 6
510 #define RADEON_TXFORMAT_RGBA8888 7
511
512 /* Constants */
513 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
514
515 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
516 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
517 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
518 #define RADEON_LAST_DISPATCH 1
519
520 #define RADEON_MAX_VB_AGE 0x7fffffff
521 #define RADEON_MAX_VB_VERTS (0xffff)
522
523 #define RADEON_RING_HIGH_MARK 128
524
525
526 #define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
527 #define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg)
528
529 #define RADEON_DEREF(reg) *(volatile u32 *)RADEON_ADDR( reg )
530 #ifdef __alpha__
531 #define RADEON_READ(reg) (_RADEON_READ((u32 *)RADEON_ADDR( reg )))
532 static inline u32 _RADEON_READ(u32 *addr)
533 {
534 mb();
535 return *(volatile u32 *)addr;
536 }
537 #define RADEON_WRITE(reg,val) \
538 do { \
539 wmb(); \
540 RADEON_DEREF(reg) = val; \
541 } while (0)
542 #else
543 #define RADEON_READ(reg) RADEON_DEREF( reg )
544 #define RADEON_WRITE(reg, val) do { RADEON_DEREF( reg ) = val; } while (0)
545 #endif
546
547 #define RADEON_DEREF8(reg) *(volatile u8 *)RADEON_ADDR( reg )
548 #ifdef __alpha__
549 #define RADEON_READ8(reg) _RADEON_READ8((u8 *)RADEON_ADDR( reg ))
550 static inline u8 _RADEON_READ8(u8 *addr)
551 {
552 mb();
553 return *(volatile u8 *)addr;
554 }
555 #define RADEON_WRITE8(reg,val) \
556 do { \
557 wmb(); \
558 RADEON_DEREF8( reg ) = val; \
559 } while (0)
560 #else
561 #define RADEON_READ8(reg) RADEON_DEREF8( reg )
562 #define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0)
563 #endif
564
565 #define RADEON_WRITE_PLL( addr, val ) \
566 do { \
567 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
568 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
569 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
570 } while (0)
571
572 extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
573
574
575 #define CP_PACKET0( reg, n ) \
576 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
577 #define CP_PACKET0_TABLE( reg, n ) \
578 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
579 #define CP_PACKET1( reg0, reg1 ) \
580 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
581 #define CP_PACKET2() \
582 (RADEON_CP_PACKET2)
583 #define CP_PACKET3( pkt, n ) \
584 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
585
586
587 /* ================================================================
588 * Engine control helper macros
589 */
590
591 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
592 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
593 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
594 RADEON_WAIT_HOST_IDLECLEAN) ); \
595 } while (0)
596
597 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
598 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
599 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
600 RADEON_WAIT_HOST_IDLECLEAN) ); \
601 } while (0)
602
603 #define RADEON_WAIT_UNTIL_IDLE() do { \
604 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
605 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
606 RADEON_WAIT_3D_IDLECLEAN | \
607 RADEON_WAIT_HOST_IDLECLEAN) ); \
608 } while (0)
609
610 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
611 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
612 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
613 } while (0)
614
615 #define RADEON_FLUSH_CACHE() do { \
616 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
617 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
618 } while (0)
619
620 #define RADEON_PURGE_CACHE() do { \
621 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
622 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
623 } while (0)
624
625 #define RADEON_FLUSH_ZCACHE() do { \
626 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
627 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
628 } while (0)
629
630 #define RADEON_PURGE_ZCACHE() do { \
631 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
632 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
633 } while (0)
634
635
636 /* ================================================================
637 * Misc helper macros
638 */
639
640 #define LOCK_TEST_WITH_RETURN( dev ) \
641 do { \
642 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
643 dev->lock.pid != current->pid ) { \
644 DRM_ERROR( "%s called without lock held\n", \
645 __FUNCTION__ ); \
646 return -EINVAL; \
647 } \
648 } while (0)
649
650 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
651 do { \
652 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \
653 if ( ring->space < ring->high_mark ) { \
654 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
655 radeon_update_ring_snapshot( ring ); \
656 if ( ring->space >= ring->high_mark ) \
657 goto __ring_space_done; \
658 udelay( 1 ); \
659 } \
660 DRM_ERROR( "ring space check failed!\n" ); \
661 return -EBUSY; \
662 } \
663 __ring_space_done: \
664 } while (0)
665
666 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
667 do { \
668 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
669 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
670 int __ret = radeon_do_cp_idle( dev_priv ); \
671 if ( __ret < 0 ) return __ret; \
672 sarea_priv->last_dispatch = 0; \
673 radeon_freelist_reset( dev ); \
674 } \
675 } while (0)
676
677 #define RADEON_DISPATCH_AGE( age ) do { \
678 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
679 OUT_RING( age ); \
680 } while (0)
681
682 #define RADEON_FRAME_AGE( age ) do { \
683 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
684 OUT_RING( age ); \
685 } while (0)
686
687 #define RADEON_CLEAR_AGE( age ) do { \
688 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
689 OUT_RING( age ); \
690 } while (0)
691
692
693 /* ================================================================
694 * Ring control
695 */
696
697 #define radeon_flush_write_combine() mb()
698
699
700 #define RADEON_VERBOSE 0
701
702 #define RING_LOCALS int write; unsigned int mask; volatile u32 *ring;
703
704 #define BEGIN_RING( n ) do { \
705 if ( RADEON_VERBOSE ) { \
706 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
707 n, __FUNCTION__ ); \
708 } \
709 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
710 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
711 } \
712 dev_priv->ring.space -= (n) * sizeof(u32); \
713 ring = dev_priv->ring.start; \
714 write = dev_priv->ring.tail; \
715 mask = dev_priv->ring.tail_mask; \
716 } while (0)
717
718 #define ADVANCE_RING() do { \
719 if ( RADEON_VERBOSE ) { \
720 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
721 write, dev_priv->ring.tail ); \
722 } \
723 radeon_flush_write_combine(); \
724 dev_priv->ring.tail = write; \
725 RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \
726 } while (0)
727
728 #define OUT_RING( x ) do { \
729 if ( RADEON_VERBOSE ) { \
730 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
731 (unsigned int)(x), write ); \
732 } \
733 ring[write++] = (x); \
734 write &= mask; \
735 } while (0)
736
737 #define RADEON_PERFORMANCE_BOXES 0
738
739 #endif /* __RADEON_DRV_H__ */
740