File: /usr/src/linux/drivers/char/ip2/i2ellis.c
1 /*******************************************************************************
2 *
3 * (c) 1998 by Computone Corporation
4 *
5 ********************************************************************************
6 *
7 *
8 * PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
9 * serial I/O controllers.
10 *
11 * DESCRIPTION: Low-level interface code for the device driver
12 * (This is included source code, not a separate compilation
13 * module.)
14 *
15 *******************************************************************************/
16 //---------------------------------------------
17 // Function declarations private to this module
18 //---------------------------------------------
19 // Functions called only indirectly through i2eBordStr entries.
20
21 static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int);
22 static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int);
23 static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int);
24 static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int);
25
26 static unsigned short iiReadWord16(i2eBordStrPtr);
27 static unsigned short iiReadWord8(i2eBordStrPtr);
28 static void iiWriteWord16(i2eBordStrPtr, unsigned short);
29 static void iiWriteWord8(i2eBordStrPtr, unsigned short);
30
31 static int iiWaitForTxEmptyII(i2eBordStrPtr, int);
32 static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int);
33 static int iiTxMailEmptyII(i2eBordStrPtr);
34 static int iiTxMailEmptyIIEX(i2eBordStrPtr);
35 static int iiTrySendMailII(i2eBordStrPtr, unsigned char);
36 static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char);
37
38 static unsigned short iiGetMailII(i2eBordStrPtr);
39 static unsigned short iiGetMailIIEX(i2eBordStrPtr);
40
41 static void iiEnableMailIrqII(i2eBordStrPtr);
42 static void iiEnableMailIrqIIEX(i2eBordStrPtr);
43 static void iiWriteMaskII(i2eBordStrPtr, unsigned char);
44 static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char);
45
46 static void ii2DelayTimer(unsigned int);
47 static void ii2DelayWakeup(unsigned long id);
48 static void ii2Nop(void);
49
50 //***************
51 //* Static Data *
52 //***************
53
54 static int ii2Safe; // Safe I/O address for delay routine
55
56 static int iiDelayed; // Set when the iiResetDelay function is
57 // called. Cleared when ANY board is reset.
58 static struct timer_list * pDelayTimer; // Used by iiDelayTimer
59 static wait_queue_head_t pDelayWait; // Used by iiDelayTimer
60 static rwlock_t Dl_spinlock;
61
62 //********
63 //* Code *
64 //********
65
66 //=======================================================
67 // Initialization Routines
68 //
69 // iiSetAddress
70 // iiReset
71 // iiResetDelay
72 // iiInitialize
73 //=======================================================
74
75 //******************************************************************************
76 // Function: iiEllisInit()
77 // Parameters: None
78 //
79 // Returns: Nothing
80 //
81 // Description:
82 //
83 // This routine performs any required initialization of the iiEllis subsystem.
84 //
85 //******************************************************************************
86 static void
87 iiEllisInit(void)
88 {
89 pDelayTimer = kmalloc ( sizeof (struct timer_list), GFP_KERNEL );
90 init_waitqueue_head(&pDelayWait);
91 LOCK_INIT(&Dl_spinlock);
92 }
93
94 //******************************************************************************
95 // Function: iiEllisCleanup()
96 // Parameters: None
97 //
98 // Returns: Nothing
99 //
100 // Description:
101 //
102 // This routine performs any required cleanup of the iiEllis subsystem.
103 //
104 //******************************************************************************
105 static void
106 iiEllisCleanup(void)
107 {
108 if ( pDelayTimer != NULL ) {
109 kfree ( pDelayTimer );
110 }
111 }
112
113 //******************************************************************************
114 // Function: iiSetAddress(pB, address, delay)
115 // Parameters: pB - pointer to the board structure
116 // address - the purported I/O address of the board
117 // delay - pointer to the 1-ms delay function to use
118 // in this and any future operations to this board
119 //
120 // Returns: True if everything appears copacetic.
121 // False if there is any error: the pB->i2eError field has the error
122 //
123 // Description:
124 //
125 // This routine (roughly) checks for address validity, sets the i2eValid OK and
126 // sets the state to II_STATE_COLD which means that we haven't even sent a reset
127 // yet.
128 //
129 //******************************************************************************
130 static int
131 iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay )
132 {
133 // Should any failure occur before init is finished...
134 pB->i2eValid = I2E_INCOMPLETE;
135
136 // Cannot check upper limit except extremely: Might be microchannel
137 // Address must be on an 8-byte boundary
138
139 if ((unsigned int)address <= 0x100
140 || (unsigned int)address >= 0xfff8
141 || (address & 0x7)
142 )
143 {
144 COMPLETE(pB,I2EE_BADADDR);
145 }
146
147 // Initialize accelerators
148 pB->i2eBase = address;
149 pB->i2eData = address + FIFO_DATA;
150 pB->i2eStatus = address + FIFO_STATUS;
151 pB->i2ePointer = address + FIFO_PTR;
152 pB->i2eXMail = address + FIFO_MAIL;
153 pB->i2eXMask = address + FIFO_MASK;
154
155 // Initialize i/o address for ii2DelayIO
156 ii2Safe = address + FIFO_NOP;
157
158 // Initialize the delay routine
159 pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop);
160
161 pB->i2eValid = I2E_MAGIC;
162 pB->i2eState = II_STATE_COLD;
163
164 COMPLETE(pB, I2EE_GOOD);
165 }
166
167 //******************************************************************************
168 // Function: iiReset(pB)
169 // Parameters: pB - pointer to the board structure
170 //
171 // Returns: True if everything appears copacetic.
172 // False if there is any error: the pB->i2eError field has the error
173 //
174 // Description:
175 //
176 // Attempts to reset the board (see also i2hw.h). Normally, we would use this to
177 // reset a board immediately after iiSetAddress(), but it is valid to reset a
178 // board from any state, say, in order to change or re-load loadware. (Under
179 // such circumstances, no reason to re-run iiSetAddress(), which is why it is a
180 // separate routine and not included in this routine.
181 //
182 //******************************************************************************
183 static int
184 iiReset(i2eBordStrPtr pB)
185 {
186 // Magic number should be set, else even the address is suspect
187 if (pB->i2eValid != I2E_MAGIC)
188 {
189 COMPLETE(pB, I2EE_BADMAGIC);
190 }
191
192 OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do
193 iiDelay(pB, 50); // Pause between resets
194 OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset
195
196 // We must wait before even attempting to read anything from the FIFO: the
197 // board's P.O.S.T may actually attempt to read and write its end of the
198 // FIFO in order to check flags, loop back (where supported), etc. On
199 // completion of this testing it would reset the FIFO, and on completion
200 // of all // P.O.S.T., write the message. We must not mistake data which
201 // might have been sent for testing as part of the reset message. To
202 // better utilize time, say, when resetting several boards, we allow the
203 // delay to be performed externally; in this way the caller can reset
204 // several boards, delay a single time, then call the initialization
205 // routine for all.
206
207 pB->i2eState = II_STATE_RESET;
208
209 iiDelayed = 0; // i.e., the delay routine hasn't been called since the most
210 // recent reset.
211
212 // Ensure anything which would have been of use to standard loadware is
213 // blanked out, since board has now forgotten everything!.
214
215 pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet
216 pB->i2eWaitingForEmptyFifo = 0;
217 pB->i2eOutMailWaiting = 0;
218 pB->i2eChannelPtr = NULL;
219 pB->i2eChannelCnt = 0;
220
221 pB->i2eLeadoffWord[0] = 0;
222 pB->i2eFifoInInts = 0;
223 pB->i2eFifoOutInts = 0;
224 pB->i2eFatalTrap = NULL;
225 pB->i2eFatal = 0;
226
227 COMPLETE(pB, I2EE_GOOD);
228 }
229
230 //******************************************************************************
231 // Function: iiResetDelay(pB)
232 // Parameters: pB - pointer to the board structure
233 //
234 // Returns: True if everything appears copacetic.
235 // False if there is any error: the pB->i2eError field has the error
236 //
237 // Description:
238 //
239 // Using the delay defined in board structure, waits two seconds (for board to
240 // reset).
241 //
242 //******************************************************************************
243 static int
244 iiResetDelay(i2eBordStrPtr pB)
245 {
246 if (pB->i2eValid != I2E_MAGIC) {
247 COMPLETE(pB, I2EE_BADMAGIC);
248 }
249 if (pB->i2eState != II_STATE_RESET) {
250 COMPLETE(pB, I2EE_BADSTATE);
251 }
252 iiDelay(pB,2000); /* Now we wait for two seconds. */
253 iiDelayed = 1; /* Delay has been called: ok to initialize */
254 COMPLETE(pB, I2EE_GOOD);
255 }
256
257 //******************************************************************************
258 // Function: iiInitialize(pB)
259 // Parameters: pB - pointer to the board structure
260 //
261 // Returns: True if everything appears copacetic.
262 // False if there is any error: the pB->i2eError field has the error
263 //
264 // Description:
265 //
266 // Attempts to read the Power-on reset message. Initializes any remaining fields
267 // in the pB structure.
268 //
269 // This should be called as the third step of a process beginning with
270 // iiReset(), then iiResetDelay(). This routine checks to see that the structure
271 // is "valid" and in the reset state, also confirms that the delay routine has
272 // been called since the latest reset (to any board! overly strong!).
273 //
274 //******************************************************************************
275 static int
276 iiInitialize(i2eBordStrPtr pB)
277 {
278 int itemp;
279 unsigned char c;
280 unsigned short utemp;
281 unsigned int ilimit;
282
283 if (pB->i2eValid != I2E_MAGIC)
284 {
285 COMPLETE(pB, I2EE_BADMAGIC);
286 }
287
288 if (pB->i2eState != II_STATE_RESET || !iiDelayed)
289 {
290 COMPLETE(pB, I2EE_BADSTATE);
291 }
292
293 // In case there is a failure short of our completely reading the power-up
294 // message.
295 pB->i2eValid = I2E_INCOMPLETE;
296
297
298 // Now attempt to read the message.
299
300 for (itemp = 0; itemp < sizeof(porStr); itemp++)
301 {
302 // We expect the entire message is ready.
303 if (HAS_NO_INPUT(pB))
304 {
305 pB->i2ePomSize = itemp;
306 COMPLETE(pB, I2EE_PORM_SHORT);
307 }
308
309 pB->i2ePom.c[itemp] = c = BYTE_FROM(pB);
310
311 // We check the magic numbers as soon as they are supposed to be read
312 // (rather than after) to minimize effect of reading something we
313 // already suspect can't be "us".
314 if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) ||
315 (itemp == POR_2_INDEX && c != POR_MAGIC_2))
316 {
317 pB->i2ePomSize = itemp+1;
318 COMPLETE(pB, I2EE_BADMAGIC);
319 }
320 }
321
322 pB->i2ePomSize = itemp;
323
324 // Ensure that this was all the data...
325 if (HAS_INPUT(pB))
326 COMPLETE(pB, I2EE_PORM_LONG);
327
328 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper:
329 // Implying we will not be able to download any code either: That's ok: the
330 // condition is pretty explicit.
331 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER)
332 {
333 COMPLETE(pB, I2EE_POSTERR);
334 }
335
336 // Determine anything which must be done differently depending on the family
337 // of boards!
338 switch (pB->i2ePom.e.porID & POR_ID_FAMILY)
339 {
340 case POR_ID_FII: // IntelliPort-II
341
342 pB->i2eFifoStyle = FIFO_II;
343 pB->i2eFifoSize = 512; // 512 bytes, always
344 pB->i2eDataWidth16 = NO;
345
346 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit
347 // slot, we do allow it to be done (documentation!)
348
349 pB->i2eGoodMap[1] =
350 pB->i2eGoodMap[2] =
351 pB->i2eGoodMap[3] =
352 pB->i2eChannelMap[1] =
353 pB->i2eChannelMap[2] =
354 pB->i2eChannelMap[3] = 0;
355
356 switch (pB->i2ePom.e.porID & POR_ID_SIZE)
357 {
358 case POR_ID_II_4:
359 pB->i2eGoodMap[0] =
360 pB->i2eChannelMap[0] = 0x0f; // four-port
361
362 // Since porPorts1 is based on the Hardware ID register, the numbers
363 // should always be consistent for IntelliPort-II. Ditto below...
364 if (pB->i2ePom.e.porPorts1 != 4)
365 {
366 COMPLETE(pB, I2EE_INCONSIST);
367 }
368 break;
369
370 case POR_ID_II_8:
371 case POR_ID_II_8R:
372 pB->i2eGoodMap[0] =
373 pB->i2eChannelMap[0] = 0xff; // Eight port
374 if (pB->i2ePom.e.porPorts1 != 8)
375 {
376 COMPLETE(pB, I2EE_INCONSIST);
377 }
378 break;
379
380 case POR_ID_II_6:
381 pB->i2eGoodMap[0] =
382 pB->i2eChannelMap[0] = 0x3f; // Six Port
383 if (pB->i2ePom.e.porPorts1 != 6)
384 {
385 COMPLETE(pB, I2EE_INCONSIST);
386 }
387 break;
388 }
389
390 // Fix up the "good channel list based on any errors reported.
391 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1)
392 {
393 pB->i2eGoodMap[0] &= ~0x0f;
394 }
395
396 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2)
397 {
398 pB->i2eGoodMap[0] &= ~0xf0;
399 }
400
401 break; // POR_ID_FII case
402
403 case POR_ID_FIIEX: // IntelliPort-IIEX
404
405 pB->i2eFifoStyle = FIFO_IIEX;
406
407 itemp = pB->i2ePom.e.porFifoSize;
408
409 // Implicit assumption that fifo would not grow beyond 32k,
410 // nor would ever be less than 256.
411
412 if (itemp < 8 || itemp > 15)
413 {
414 COMPLETE(pB, I2EE_INCONSIST);
415 }
416 pB->i2eFifoSize = (1 << itemp);
417
418 // These are based on what P.O.S.T thinks should be there, based on
419 // box ID registers
420 ilimit = pB->i2ePom.e.porNumBoxes;
421 if (ilimit > ABS_MAX_BOXES)
422 {
423 ilimit = ABS_MAX_BOXES;
424 }
425
426 // For as many boxes as EXIST, gives the type of box.
427 // Added 8/6/93: check for the ISA-4 (asic) which looks like an
428 // expandable but for whom "8 or 16?" is not the right question.
429
430 utemp = pB->i2ePom.e.porFlags;
431 if (utemp & POR_CEX4)
432 {
433 pB->i2eChannelMap[0] = 0x000f;
434 } else {
435 utemp &= POR_BOXES;
436 for (itemp = 0; itemp < ilimit; itemp++)
437 {
438 pB->i2eChannelMap[itemp] =
439 ((utemp & POR_BOX_16) ? 0xffff : 0x00ff);
440 utemp >>= 1;
441 }
442 }
443
444 // These are based on what P.O.S.T actually found.
445
446 utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1;
447
448 for (itemp = 0; itemp < ilimit; itemp++)
449 {
450 pB->i2eGoodMap[itemp] = 0;
451 if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f;
452 if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0;
453 if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00;
454 if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000;
455 utemp >>= 4;
456 }
457
458 // Now determine whether we should transfer in 8 or 16-bit mode.
459 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) )
460 {
461 case POR_BUS_SLOT16 | POR_BUS_DIP16:
462 pB->i2eDataWidth16 = YES;
463 pB->i2eMaxIrq = 15;
464 break;
465
466 case POR_BUS_SLOT16:
467 pB->i2eDataWidth16 = NO;
468 pB->i2eMaxIrq = 15;
469 break;
470
471 case 0:
472 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care.
473 default:
474 pB->i2eDataWidth16 = NO;
475 pB->i2eMaxIrq = 7;
476 break;
477 }
478 break; // POR_ID_FIIEX case
479
480 default: // Unknown type of board
481 COMPLETE(pB, I2EE_BAD_FAMILY);
482 break;
483 } // End the switch based on family
484
485 // Temporarily, claim there is no room in the outbound fifo.
486 // We will maintain this whenever we check for an empty outbound FIFO.
487 pB->i2eFifoRemains = 0;
488
489 // Now, based on the bus type, should we expect to be able to re-configure
490 // interrupts (say, for testing purposes).
491 switch (pB->i2ePom.e.porBus & POR_BUS_TYPE)
492 {
493 case POR_BUS_T_ISA:
494 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok.
495 pB->i2eChangeIrq = YES;
496 break;
497 case POR_BUS_T_MCA:
498 case POR_BUS_T_EISA:
499 pB->i2eChangeIrq = NO;
500 break;
501 default:
502 COMPLETE(pB, I2EE_BADBUS);
503 }
504
505 if (pB->i2eDataWidth16 == YES)
506 {
507 pB->i2eWriteBuf = iiWriteBuf16;
508 pB->i2eReadBuf = iiReadBuf16;
509 pB->i2eWriteWord = iiWriteWord16;
510 pB->i2eReadWord = iiReadWord16;
511 } else {
512 pB->i2eWriteBuf = iiWriteBuf8;
513 pB->i2eReadBuf = iiReadBuf8;
514 pB->i2eWriteWord = iiWriteWord8;
515 pB->i2eReadWord = iiReadWord8;
516 }
517
518 switch(pB->i2eFifoStyle)
519 {
520 case FIFO_II:
521 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII;
522 pB->i2eTxMailEmpty = iiTxMailEmptyII;
523 pB->i2eTrySendMail = iiTrySendMailII;
524 pB->i2eGetMail = iiGetMailII;
525 pB->i2eEnableMailIrq = iiEnableMailIrqII;
526 pB->i2eWriteMask = iiWriteMaskII;
527
528 break;
529
530 case FIFO_IIEX:
531 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX;
532 pB->i2eTxMailEmpty = iiTxMailEmptyIIEX;
533 pB->i2eTrySendMail = iiTrySendMailIIEX;
534 pB->i2eGetMail = iiGetMailIIEX;
535 pB->i2eEnableMailIrq = iiEnableMailIrqIIEX;
536 pB->i2eWriteMask = iiWriteMaskIIEX;
537
538 break;
539
540 default:
541 COMPLETE(pB, I2EE_INCONSIST);
542 }
543
544 // Initialize state information.
545 pB->i2eState = II_STATE_READY; // Ready to load loadware.
546
547 // Some Final cleanup:
548 // For some boards, the bootstrap firmware may perform some sort of test
549 // resulting in a stray character pending in the incoming mailbox. If one is
550 // there, it should be read and discarded, especially since for the standard
551 // firmware, it's the mailbox that interrupts the host.
552
553 pB->i2eStartMail = iiGetMail(pB);
554
555 // Everything is ok now, return with good status/
556
557 pB->i2eValid = I2E_MAGIC;
558 COMPLETE(pB, I2EE_GOOD);
559 }
560
561 //=======================================================
562 // Delay Routines
563 //
564 // iiDelayIO
565 // iiNop
566 //=======================================================
567
568 static void
569 ii2DelayWakeup(unsigned long id)
570 {
571 wake_up_interruptible ( &pDelayWait );
572 }
573
574 //******************************************************************************
575 // Function: ii2DelayTimer(mseconds)
576 // Parameters: mseconds - number of milliseconds to delay
577 //
578 // Returns: Nothing
579 //
580 // Description:
581 //
582 // This routine delays for approximately mseconds milliseconds and is intended
583 // to be called indirectly through i2Delay field in i2eBordStr. It uses the
584 // Linux timer_list mechanism.
585 //
586 // The Linux timers use a unit called "jiffies" which are 10mS in the Intel
587 // architecture. This function rounds the delay period up to the next "jiffy".
588 // In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended
589 // for Alpha platforms at this time.
590 //
591 //******************************************************************************
592 static void
593 ii2DelayTimer(unsigned int mseconds)
594 {
595 init_timer ( pDelayTimer );
596
597 pDelayTimer->expires = jiffies + ( mseconds + 9 ) / 10;
598 pDelayTimer->function = ii2DelayWakeup;
599 pDelayTimer->data = 0;
600
601 add_timer ( pDelayTimer );
602 interruptible_sleep_on ( &pDelayWait );
603 del_timer ( pDelayTimer );
604 }
605
606 #if 0
607 //static void ii2DelayIO(unsigned int);
608 //******************************************************************************
609 // !!! Not Used, this is DOS crap, some of you young folks may be interested in
610 // in how things were done in the stone age of caculating machines !!!
611 // Function: ii2DelayIO(mseconds)
612 // Parameters: mseconds - number of milliseconds to delay
613 //
614 // Returns: Nothing
615 //
616 // Description:
617 //
618 // This routine delays for approximately mseconds milliseconds and is intended
619 // to be called indirectly through i2Delay field in i2eBordStr. It is intended
620 // for use where a clock-based function is impossible: for example, DOS drivers.
621 //
622 // This function uses the IN instruction to place bounds on the timing and
623 // assumes that ii2Safe has been set. This is because I/O instructions are not
624 // subject to caching and will therefore take a certain minimum time. To ensure
625 // the delay is at least long enough on fast machines, it is based on some
626 // fastest-case calculations. On slower machines this may cause VERY long
627 // delays. (3 x fastest case). In the fastest case, everything is cached except
628 // the I/O instruction itself.
629 //
630 // Timing calculations:
631 // The fastest bus speed for I/O operations is likely to be 10 MHz. The I/O
632 // operation in question is a byte operation to an odd address. For 8-bit
633 // operations, the architecture generally enforces two wait states. At 10 MHz, a
634 // single cycle time is 100nS. A read operation at two wait states takes 6
635 // cycles for a total time of 600nS. Therefore approximately 1666 iterations
636 // would be required to generate a single millisecond delay. The worst
637 // (reasonable) case would be an 8MHz system with no cacheing. In this case, the
638 // I/O instruction would take 125nS x 6 cyles = 750 nS. More importantly, code
639 // fetch of other instructions in the loop would take time (zero wait states,
640 // however) and would be hard to estimate. This is minimized by using in-line
641 // assembler for the in inner loop of IN instructions. This consists of just a
642 // few bytes. So we'll guess about four code fetches per loop. Each code fetch
643 // should take four cycles, so we have 125nS * 8 = 1000nS. Worst case then is
644 // that what should have taken 1 mS takes instead 1666 * (1750) = 2.9 mS.
645 //
646 // So much for theoretical timings: results using 1666 value on some actual
647 // machines:
648 // IBM 286 6MHz 3.15 mS
649 // Zenith 386 33MHz 2.45 mS
650 // (brandX) 386 33MHz 1.90 mS (has cache)
651 // (brandY) 486 33MHz 2.35 mS
652 // NCR 486 ?? 1.65 mS (microchannel)
653 //
654 // For most machines, it is probably safe to scale this number back (remember,
655 // for robust operation use an actual timed delay if possible), so we are using
656 // a value of 1190. This yields 1.17 mS for the fastest machine in our sample,
657 // 1.75 mS for typical 386 machines, and 2.25 mS the absolute slowest machine.
658 //
659 // 1/29/93:
660 // The above timings are too slow. Actual cycle times might be faster. ISA cycle
661 // times could approach 500 nS, and ...
662 // The IBM model 77 being microchannel has no wait states for 8-bit reads and
663 // seems to be accessing the I/O at 440 nS per access (from start of one to
664 // start of next). This would imply we need 1000/.440 = 2272 iterations to
665 // guarantee we are fast enough. In actual testing, we see that 2 * 1190 are in
666 // fact enough. For diagnostics, we keep the level at 1190, but developers note
667 // this needs tuning.
668 //
669 // Safe assumption: 2270 i/o reads = 1 millisecond
670 //
671 //******************************************************************************
672
673
674 static int ii2DelValue = 1190; // See timing calculations below
675 // 1666 for fastest theoretical machine
676 // 1190 safe for most fast 386 machines
677 // 1000 for fastest machine tested here
678 // 540 (sic) for AT286/6Mhz
679 static void
680 ii2DelayIO(unsigned int mseconds)
681 {
682 if (!ii2Safe)
683 return; /* Do nothing if this variable uninitialized */
684
685 while(mseconds--) {
686 int i = ii2DelValue;
687 while ( i-- ) {
688 INB ( ii2Safe );
689 }
690 }
691 }
692 #endif
693
694 //******************************************************************************
695 // Function: ii2Nop()
696 // Parameters: None
697 //
698 // Returns: Nothing
699 //
700 // Description:
701 //
702 // iiInitialize will set i2eDelay to this if the delay parameter is NULL. This
703 // saves checking for a NULL pointer at every call.
704 //******************************************************************************
705 static void
706 ii2Nop(void)
707 {
708 return; // no mystery here
709 }
710
711 //=======================================================
712 // Routines which are available in 8/16-bit versions, or
713 // in different fifo styles. These are ALL called
714 // indirectly through the board structure.
715 //=======================================================
716
717 //******************************************************************************
718 // Function: iiWriteBuf16(pB, address, count)
719 // Parameters: pB - pointer to board structure
720 // address - address of data to write
721 // count - number of data bytes to write
722 //
723 // Returns: True if everything appears copacetic.
724 // False if there is any error: the pB->i2eError field has the error
725 //
726 // Description:
727 //
728 // Writes 'count' bytes from 'address' to the data fifo specified by the board
729 // structure pointer pB. Should count happen to be odd, an extra pad byte is
730 // sent (identity unknown...). Uses 16-bit (word) operations. Is called
731 // indirectly through pB->i2eWriteBuf.
732 //
733 //******************************************************************************
734 static int
735 iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
736 {
737 // Rudimentary sanity checking here.
738 if (pB->i2eValid != I2E_MAGIC)
739 COMPLETE(pB, I2EE_INVALID);
740
741 OUTSW ( pB->i2eData, address, count);
742
743 COMPLETE(pB, I2EE_GOOD);
744 }
745
746 //******************************************************************************
747 // Function: iiWriteBuf8(pB, address, count)
748 // Parameters: pB - pointer to board structure
749 // address - address of data to write
750 // count - number of data bytes to write
751 //
752 // Returns: True if everything appears copacetic.
753 // False if there is any error: the pB->i2eError field has the error
754 //
755 // Description:
756 //
757 // Writes 'count' bytes from 'address' to the data fifo specified by the board
758 // structure pointer pB. Should count happen to be odd, an extra pad byte is
759 // sent (identity unknown...). This is to be consistant with the 16-bit version.
760 // Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf.
761 //
762 //******************************************************************************
763 static int
764 iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
765 {
766 /* Rudimentary sanity checking here */
767 if (pB->i2eValid != I2E_MAGIC)
768 COMPLETE(pB, I2EE_INVALID);
769
770 OUTSB ( pB->i2eData, address, count );
771
772 COMPLETE(pB, I2EE_GOOD);
773 }
774
775 //******************************************************************************
776 // Function: iiReadBuf16(pB, address, count)
777 // Parameters: pB - pointer to board structure
778 // address - address to put data read
779 // count - number of data bytes to read
780 //
781 // Returns: True if everything appears copacetic.
782 // False if there is any error: the pB->i2eError field has the error
783 //
784 // Description:
785 //
786 // Reads 'count' bytes into 'address' from the data fifo specified by the board
787 // structure pointer pB. Should count happen to be odd, an extra pad byte is
788 // received (identity unknown...). Uses 16-bit (word) operations. Is called
789 // indirectly through pB->i2eReadBuf.
790 //
791 //******************************************************************************
792 static int
793 iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count)
794 {
795 // Rudimentary sanity checking here.
796 if (pB->i2eValid != I2E_MAGIC)
797 COMPLETE(pB, I2EE_INVALID);
798
799 INSW ( pB->i2eData, address, count);
800
801 COMPLETE(pB, I2EE_GOOD);
802 }
803
804 //******************************************************************************
805 // Function: iiReadBuf8(pB, address, count)
806 // Parameters: pB - pointer to board structure
807 // address - address to put data read
808 // count - number of data bytes to read
809 //
810 // Returns: True if everything appears copacetic.
811 // False if there is any error: the pB->i2eError field has the error
812 //
813 // Description:
814 //
815 // Reads 'count' bytes into 'address' from the data fifo specified by the board
816 // structure pointer pB. Should count happen to be odd, an extra pad byte is
817 // received (identity unknown...). This to match the 16-bit behaviour. Uses
818 // 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf.
819 //
820 //******************************************************************************
821 static int
822 iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count)
823 {
824 // Rudimentary sanity checking here.
825 if (pB->i2eValid != I2E_MAGIC)
826 COMPLETE(pB, I2EE_INVALID);
827
828 INSB ( pB->i2eData, address, count);
829
830 COMPLETE(pB, I2EE_GOOD);
831 }
832
833 //******************************************************************************
834 // Function: iiReadWord16(pB)
835 // Parameters: pB - pointer to board structure
836 //
837 // Returns: True if everything appears copacetic.
838 // False if there is any error: the pB->i2eError field has the error
839 //
840 // Description:
841 //
842 // Returns the word read from the data fifo specified by the board-structure
843 // pointer pB. Uses a 16-bit operation. Is called indirectly through
844 // pB->i2eReadWord.
845 //
846 //******************************************************************************
847 static unsigned short
848 iiReadWord16(i2eBordStrPtr pB)
849 {
850 return (unsigned short)( INW(pB->i2eData) );
851 }
852
853 //******************************************************************************
854 // Function: iiReadWord8(pB)
855 // Parameters: pB - pointer to board structure
856 //
857 // Returns: True if everything appears copacetic.
858 // False if there is any error: the pB->i2eError field has the error
859 //
860 // Description:
861 //
862 // Returns the word read from the data fifo specified by the board-structure
863 // pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is
864 // called indirectly through pB->i2eReadWord.
865 //
866 //******************************************************************************
867 static unsigned short
868 iiReadWord8(i2eBordStrPtr pB)
869 {
870 unsigned short urs;
871
872 urs = INB ( pB->i2eData );
873
874 return ( ( INB ( pB->i2eData ) << 8 ) | urs );
875 }
876
877 //******************************************************************************
878 // Function: iiWriteWord16(pB, value)
879 // Parameters: pB - pointer to board structure
880 // value - data to write
881 //
882 // Returns: True if everything appears copacetic.
883 // False if there is any error: the pB->i2eError field has the error
884 //
885 // Description:
886 //
887 // Writes the word 'value' to the data fifo specified by the board-structure
888 // pointer pB. Uses 16-bit operation. Is called indirectly through
889 // pB->i2eWriteWord.
890 //
891 //******************************************************************************
892 static void
893 iiWriteWord16(i2eBordStrPtr pB, unsigned short value)
894 {
895 WORD_TO(pB, (int)value);
896 }
897
898 //******************************************************************************
899 // Function: iiWriteWord8(pB, value)
900 // Parameters: pB - pointer to board structure
901 // value - data to write
902 //
903 // Returns: True if everything appears copacetic.
904 // False if there is any error: the pB->i2eError field has the error
905 //
906 // Description:
907 //
908 // Writes the word 'value' to the data fifo specified by the board-structure
909 // pointer pB. Uses two 8-bit operations (writes LSB first). Is called
910 // indirectly through pB->i2eWriteWord.
911 //
912 //******************************************************************************
913 static void
914 iiWriteWord8(i2eBordStrPtr pB, unsigned short value)
915 {
916 BYTE_TO(pB, (char)value);
917 BYTE_TO(pB, (char)(value >> 8) );
918 }
919
920 //******************************************************************************
921 // Function: iiWaitForTxEmptyII(pB, mSdelay)
922 // Parameters: pB - pointer to board structure
923 // mSdelay - period to wait before returning
924 //
925 // Returns: True if the FIFO is empty.
926 // False if it not empty in the required time: the pB->i2eError
927 // field has the error.
928 //
929 // Description:
930 //
931 // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
932 // not empty by the required time, returns false and error in pB->i2eError,
933 // otherwise returns true.
934 //
935 // mSdelay == 0 is taken to mean must be empty on the first test.
936 //
937 // This version operates on IntelliPort-II - style FIFO's
938 //
939 // Note this routine is organized so that if status is ok there is no delay at
940 // all called either before or after the test. Is called indirectly through
941 // pB->i2eWaitForTxEmpty.
942 //
943 //******************************************************************************
944 static int
945 iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay)
946 {
947 unsigned long flags;
948 int itemp;
949
950 for (;;)
951 {
952 // This routine hinges on being able to see the "other" status register
953 // (as seen by the local processor). His incoming fifo is our outgoing
954 // FIFO.
955 //
956 // By the nature of this routine, you would be using this as part of a
957 // larger atomic context: i.e., you would use this routine to ensure the
958 // fifo empty, then act on this information. Between these two halves,
959 // you will generally not want to service interrupts or in any way
960 // disrupt the assumptions implicit in the larger context.
961 //
962 // Even worse, however, this routine "shifts" the status register to
963 // point to the local status register which is not the usual situation.
964 // Therefore for extra safety, we force the critical section to be
965 // completely atomic, and pick up after ourselves before allowing any
966 // interrupts of any kind.
967
968
969 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
970 OUTB(pB->i2ePointer, SEL_COMMAND);
971 OUTB(pB->i2ePointer, SEL_CMD_SH);
972
973 itemp = INB(pB->i2eStatus);
974
975 OUTB(pB->i2ePointer, SEL_COMMAND);
976 OUTB(pB->i2ePointer, SEL_CMD_UNSH);
977
978 if (itemp & ST_IN_EMPTY)
979 {
980 UPDATE_FIFO_ROOM(pB);
981 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
982 COMPLETE(pB, I2EE_GOOD);
983 }
984
985 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
986
987 if (mSdelay-- == 0)
988 break;
989
990 iiDelay(pB, 1); /* 1 mS granularity on checking condition */
991 }
992 COMPLETE(pB, I2EE_TXE_TIME);
993 }
994
995 //******************************************************************************
996 // Function: iiWaitForTxEmptyIIEX(pB, mSdelay)
997 // Parameters: pB - pointer to board structure
998 // mSdelay - period to wait before returning
999 //
1000 // Returns: True if the FIFO is empty.
1001 // False if it not empty in the required time: the pB->i2eError
1002 // field has the error.
1003 //
1004 // Description:
1005 //
1006 // Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if
1007 // not empty by the required time, returns false and error in pB->i2eError,
1008 // otherwise returns true.
1009 //
1010 // mSdelay == 0 is taken to mean must be empty on the first test.
1011 //
1012 // This version operates on IntelliPort-IIEX - style FIFO's
1013 //
1014 // Note this routine is organized so that if status is ok there is no delay at
1015 // all called either before or after the test. Is called indirectly through
1016 // pB->i2eWaitForTxEmpty.
1017 //
1018 //******************************************************************************
1019 static int
1020 iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay)
1021 {
1022 unsigned long flags;
1023
1024 for (;;)
1025 {
1026 // By the nature of this routine, you would be using this as part of a
1027 // larger atomic context: i.e., you would use this routine to ensure the
1028 // fifo empty, then act on this information. Between these two halves,
1029 // you will generally not want to service interrupts or in any way
1030 // disrupt the assumptions implicit in the larger context.
1031
1032 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags)
1033
1034 if (INB(pB->i2eStatus) & STE_OUT_MT) {
1035 UPDATE_FIFO_ROOM(pB);
1036 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
1037 COMPLETE(pB, I2EE_GOOD);
1038 }
1039 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags)
1040
1041 if (mSdelay-- == 0)
1042 break;
1043
1044 iiDelay(pB, 1); // 1 mS granularity on checking condition
1045 }
1046 COMPLETE(pB, I2EE_TXE_TIME);
1047 }
1048
1049 //******************************************************************************
1050 // Function: iiTxMailEmptyII(pB)
1051 // Parameters: pB - pointer to board structure
1052 //
1053 // Returns: True if the transmit mailbox is empty.
1054 // False if it not empty.
1055 //
1056 // Description:
1057 //
1058 // Returns true or false according to whether the transmit mailbox is empty (and
1059 // therefore able to accept more mail)
1060 //
1061 // This version operates on IntelliPort-II - style FIFO's
1062 //
1063 //******************************************************************************
1064 static int
1065 iiTxMailEmptyII(i2eBordStrPtr pB)
1066 {
1067 int port = pB->i2ePointer;
1068 OUTB ( port, SEL_OUTMAIL );
1069 return ( INB(port) == 0 );
1070 }
1071
1072 //******************************************************************************
1073 // Function: iiTxMailEmptyIIEX(pB)
1074 // Parameters: pB - pointer to board structure
1075 //
1076 // Returns: True if the transmit mailbox is empty.
1077 // False if it not empty.
1078 //
1079 // Description:
1080 //
1081 // Returns true or false according to whether the transmit mailbox is empty (and
1082 // therefore able to accept more mail)
1083 //
1084 // This version operates on IntelliPort-IIEX - style FIFO's
1085 //
1086 //******************************************************************************
1087 static int
1088 iiTxMailEmptyIIEX(i2eBordStrPtr pB)
1089 {
1090 return !(INB(pB->i2eStatus) & STE_OUT_MAIL);
1091 }
1092
1093 //******************************************************************************
1094 // Function: iiTrySendMailII(pB,mail)
1095 // Parameters: pB - pointer to board structure
1096 // mail - value to write to mailbox
1097 //
1098 // Returns: True if the transmit mailbox is empty, and mail is sent.
1099 // False if it not empty.
1100 //
1101 // Description:
1102 //
1103 // If outgoing mailbox is empty, sends mail and returns true. If outgoing
1104 // mailbox is not empty, returns false.
1105 //
1106 // This version operates on IntelliPort-II - style FIFO's
1107 //
1108 //******************************************************************************
1109 static int
1110 iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail)
1111 {
1112 int port = pB->i2ePointer;
1113
1114 OUTB(port, SEL_OUTMAIL);
1115 if (INB(port) == 0) {
1116 OUTB(port, SEL_OUTMAIL);
1117 OUTB(port, mail);
1118 return 1;
1119 }
1120 return 0;
1121 }
1122
1123 //******************************************************************************
1124 // Function: iiTrySendMailIIEX(pB,mail)
1125 // Parameters: pB - pointer to board structure
1126 // mail - value to write to mailbox
1127 //
1128 // Returns: True if the transmit mailbox is empty, and mail is sent.
1129 // False if it not empty.
1130 //
1131 // Description:
1132 //
1133 // If outgoing mailbox is empty, sends mail and returns true. If outgoing
1134 // mailbox is not empty, returns false.
1135 //
1136 // This version operates on IntelliPort-IIEX - style FIFO's
1137 //
1138 //******************************************************************************
1139 static int
1140 iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail)
1141 {
1142 if(INB(pB->i2eStatus) & STE_OUT_MAIL) {
1143 return 0;
1144 }
1145 OUTB(pB->i2eXMail, mail);
1146 return 1;
1147 }
1148
1149 //******************************************************************************
1150 // Function: iiGetMailII(pB,mail)
1151 // Parameters: pB - pointer to board structure
1152 //
1153 // Returns: Mailbox data or NO_MAIL_HERE.
1154 //
1155 // Description:
1156 //
1157 // If no mail available, returns NO_MAIL_HERE otherwise returns the data from
1158 // the mailbox, which is guaranteed != NO_MAIL_HERE.
1159 //
1160 // This version operates on IntelliPort-II - style FIFO's
1161 //
1162 //******************************************************************************
1163 static unsigned short
1164 iiGetMailII(i2eBordStrPtr pB)
1165 {
1166 if (HAS_MAIL(pB)) {
1167 OUTB(pB->i2ePointer, SEL_INMAIL);
1168 return INB(pB->i2ePointer);
1169 } else {
1170 return NO_MAIL_HERE;
1171 }
1172 }
1173
1174 //******************************************************************************
1175 // Function: iiGetMailIIEX(pB,mail)
1176 // Parameters: pB - pointer to board structure
1177 //
1178 // Returns: Mailbox data or NO_MAIL_HERE.
1179 //
1180 // Description:
1181 //
1182 // If no mail available, returns NO_MAIL_HERE otherwise returns the data from
1183 // the mailbox, which is guaranteed != NO_MAIL_HERE.
1184 //
1185 // This version operates on IntelliPort-IIEX - style FIFO's
1186 //
1187 //******************************************************************************
1188 static unsigned short
1189 iiGetMailIIEX(i2eBordStrPtr pB)
1190 {
1191 if (HAS_MAIL(pB)) {
1192 return INB(pB->i2eXMail);
1193 } else {
1194 return NO_MAIL_HERE;
1195 }
1196 }
1197
1198 //******************************************************************************
1199 // Function: iiEnableMailIrqII(pB)
1200 // Parameters: pB - pointer to board structure
1201 //
1202 // Returns: Nothing
1203 //
1204 // Description:
1205 //
1206 // Enables board to interrupt host (only) by writing to host's in-bound mailbox.
1207 //
1208 // This version operates on IntelliPort-II - style FIFO's
1209 //
1210 //******************************************************************************
1211 static void
1212 iiEnableMailIrqII(i2eBordStrPtr pB)
1213 {
1214 OUTB(pB->i2ePointer, SEL_MASK);
1215 OUTB(pB->i2ePointer, ST_IN_MAIL);
1216 }
1217
1218 //******************************************************************************
1219 // Function: iiEnableMailIrqIIEX(pB)
1220 // Parameters: pB - pointer to board structure
1221 //
1222 // Returns: Nothing
1223 //
1224 // Description:
1225 //
1226 // Enables board to interrupt host (only) by writing to host's in-bound mailbox.
1227 //
1228 // This version operates on IntelliPort-IIEX - style FIFO's
1229 //
1230 //******************************************************************************
1231 static void
1232 iiEnableMailIrqIIEX(i2eBordStrPtr pB)
1233 {
1234 OUTB(pB->i2eXMask, MX_IN_MAIL);
1235 }
1236
1237 //******************************************************************************
1238 // Function: iiWriteMaskII(pB)
1239 // Parameters: pB - pointer to board structure
1240 //
1241 // Returns: Nothing
1242 //
1243 // Description:
1244 //
1245 // Writes arbitrary value to the mask register.
1246 //
1247 // This version operates on IntelliPort-II - style FIFO's
1248 //
1249 //******************************************************************************
1250 static void
1251 iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
1252 {
1253 OUTB(pB->i2ePointer, SEL_MASK);
1254 OUTB(pB->i2ePointer, value);
1255 }
1256
1257 //******************************************************************************
1258 // Function: iiWriteMaskIIEX(pB)
1259 // Parameters: pB - pointer to board structure
1260 //
1261 // Returns: Nothing
1262 //
1263 // Description:
1264 //
1265 // Writes arbitrary value to the mask register.
1266 //
1267 // This version operates on IntelliPort-IIEX - style FIFO's
1268 //
1269 //******************************************************************************
1270 static void
1271 iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value)
1272 {
1273 OUTB(pB->i2eXMask, value);
1274 }
1275
1276 //******************************************************************************
1277 // Function: iiDownloadBlock(pB, pSource, isStandard)
1278 // Parameters: pB - pointer to board structure
1279 // pSource - loadware block to download
1280 // isStandard - True if "standard" loadware, else false.
1281 //
1282 // Returns: Success or Failure
1283 //
1284 // Description:
1285 //
1286 // Downloads a single block (at pSource)to the board referenced by pB. Caller
1287 // sets isStandard to true/false according to whether the "standard" loadware is
1288 // what's being loaded. The normal process, then, is to perform an iiInitialize
1289 // to the board, then perform some number of iiDownloadBlocks using the returned
1290 // state to determine when download is complete.
1291 //
1292 // Possible return values: (see I2ELLIS.H)
1293 // II_DOWN_BADVALID
1294 // II_DOWN_BADFILE
1295 // II_DOWN_CONTINUING
1296 // II_DOWN_GOOD
1297 // II_DOWN_BAD
1298 // II_DOWN_BADSTATE
1299 // II_DOWN_TIMEOUT
1300 //
1301 // Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to
1302 // determine whether this is the first block, whether to check for magic
1303 // numbers, how many blocks there are to go...
1304 //
1305 //******************************************************************************
1306 static int
1307 iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard)
1308 {
1309 int itemp;
1310 int loadedFirst;
1311
1312 if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID;
1313
1314 switch(pB->i2eState)
1315 {
1316 case II_STATE_READY:
1317
1318 // Loading the first block after reset. Must check the magic number of the
1319 // loadfile, store the number of blocks we expect to load.
1320 if (pSource->e.loadMagic != MAGIC_LOADFILE)
1321 {
1322 return II_DOWN_BADFILE;
1323 }
1324
1325 // Next we store the total number of blocks to load, including this one.
1326 pB->i2eToLoad = 1 + pSource->e.loadBlocksMore;
1327
1328 // Set the state, store the version numbers. ('Cause this may have come
1329 // from a file - we might want to report these versions and revisions in
1330 // case of an error!
1331 pB->i2eState = II_STATE_LOADING;
1332 pB->i2eLVersion = pSource->e.loadVersion;
1333 pB->i2eLRevision = pSource->e.loadRevision;
1334 pB->i2eLSub = pSource->e.loadSubRevision;
1335
1336 // The time and date of compilation is also available but don't bother
1337 // storing it for normal purposes.
1338 loadedFirst = 1;
1339 break;
1340
1341 case II_STATE_LOADING:
1342 loadedFirst = 0;
1343 break;
1344
1345 default:
1346 return II_DOWN_BADSTATE;
1347 }
1348
1349 // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad
1350 // must be positive still, because otherwise we would have cleaned up last
1351 // time and set the state to II_STATE_LOADED.
1352 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
1353 return II_DOWN_TIMEOUT;
1354 }
1355
1356 if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) {
1357 return II_DOWN_BADVALID;
1358 }
1359
1360 // If we just loaded the first block, wait for the fifo to empty an extra
1361 // long time to allow for any special startup code in the firmware, like
1362 // sending status messages to the LCD's.
1363
1364 if (loadedFirst) {
1365 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) {
1366 return II_DOWN_TIMEOUT;
1367 }
1368 }
1369
1370 // Determine whether this was our last block!
1371 if (--(pB->i2eToLoad)) {
1372 return II_DOWN_CONTINUING; // more to come...
1373 }
1374
1375 // It WAS our last block: Clean up operations...
1376 // ...Wait for last buffer to drain from the board...
1377 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) {
1378 return II_DOWN_TIMEOUT;
1379 }
1380 // If there were only a single block written, this would come back
1381 // immediately and be harmless, though not strictly necessary.
1382 itemp = MAX_DLOAD_ACK_TIME/10;
1383 while (--itemp) {
1384 if (HAS_INPUT(pB)) {
1385 switch(BYTE_FROM(pB))
1386 {
1387 case LOADWARE_OK:
1388 pB->i2eState =
1389 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED;
1390
1391 // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2)
1392 // will, // if there is a debug port attached, require some
1393 // time to send information to the debug port now. It will do
1394 // this before // executing any of the code we just downloaded.
1395 // It may take up to 700 milliseconds.
1396 if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) {
1397 iiDelay(pB, 700);
1398 }
1399
1400 return II_DOWN_GOOD;
1401
1402 case LOADWARE_BAD:
1403 default:
1404 return II_DOWN_BAD;
1405 }
1406 }
1407
1408 iiDelay(pB, 10); // 10 mS granularity on checking condition
1409 }
1410
1411 // Drop-through --> timed out waiting for firmware confirmation
1412
1413 pB->i2eState = II_STATE_BADLOAD;
1414 return II_DOWN_TIMEOUT;
1415 }
1416
1417 //******************************************************************************
1418 // Function: iiDownloadAll(pB, pSource, isStandard, size)
1419 // Parameters: pB - pointer to board structure
1420 // pSource - loadware block to download
1421 // isStandard - True if "standard" loadware, else false.
1422 // size - size of data to download (in bytes)
1423 //
1424 // Returns: Success or Failure
1425 //
1426 // Description:
1427 //
1428 // Given a pointer to a board structure, a pointer to the beginning of some
1429 // loadware, whether it is considered the "standard loadware", and the size of
1430 // the array in bytes loads the entire array to the board as loadware.
1431 //
1432 // Assumes the board has been freshly reset and the power-up reset message read.
1433 // (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be
1434 // too much or too little data to load, or if iiDownloadBlock complains.
1435 //******************************************************************************
1436 static int
1437 iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size)
1438 {
1439 int status;
1440
1441 // We know (from context) board should be ready for the first block of
1442 // download. Complain if not.
1443 if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE;
1444
1445 while (size > 0) {
1446 size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to
1447 // load after the following operation ?
1448
1449 // Note we just bump pSource by "one", because its size is actually that
1450 // of an entire block, same as LOADWARE_BLOCK_SIZE.
1451 status = iiDownloadBlock(pB, pSource++, isStandard);
1452
1453 switch(status)
1454 {
1455 case II_DOWN_GOOD:
1456 return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD);
1457
1458 case II_DOWN_CONTINUING:
1459 break;
1460
1461 default:
1462 return status;
1463 }
1464 }
1465
1466 // We shouldn't drop out: it means "while" caught us with nothing left to
1467 // download, yet the previous DownloadBlock did not return complete. Ergo,
1468 // not enough data to match the size byte in the header.
1469 return II_DOWN_UNDER;
1470 }
1471