File: /usr/src/linux/drivers/char/rio/cirrus.h
1 /****************************************************************************
2 ******* *******
3 ******* CIRRUS.H *******
4 ******* *******
5 ****************************************************************************
6
7 Author : Jeremy Rolls
8 Date : 3 Aug 1990
9
10 *
11 * (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26
27 Version : 0.01
28
29
30 Mods
31 ----------------------------------------------------------------------------
32 Date By Description
33 ----------------------------------------------------------------------------
34
35 ***************************************************************************/
36
37 #ifndef _cirrus_h
38 #ifndef lint
39 /* static char* _cirrus_h_sccs = "@(#)cirrus.h 1.16"; */
40 #endif
41 #define _cirrus_h 1
42
43 #ifdef RTA
44 #define TO_UART RX
45 #define TO_DRIVER TX
46 #endif
47
48 #ifdef HOST
49 #define TO_UART TX
50 #define TO_DRIVER RX
51 #endif
52 #ifdef RTA
53 /* Miscellaneous defines for CIRRUS addresses and related logic for
54 interrupts etc.
55 */
56 #define MAP(a) ((short *)(cirrus_base + (a)))
57 #define outp(a,b) (*MAP (a) =(b))
58 #define inp(a) ((*MAP (a)) & 0xff)
59 #define CIRRUS_FIRST (short*)0x7300
60 #define CIRRUS_SECOND (short*)0x7200
61 #define CIRRUS_THIRD (short*)0x7100
62 #define CIRRUS_FOURTH (short*)0x7000
63 #define PORTS_ON_CIRRUS 4
64 #define CIRRUS_FIFO_SIZE 12
65 #define SPACE 0x20
66 #define TAB 0x09
67 #define LINE_FEED 0x0a
68 #define CARRIAGE_RETURN 0x0d
69 #define BACKSPACE 0x08
70 #define SPACES_IN_TABS 8
71 #define SEND_ESCAPE 0x00
72 #define START_BREAK 0x81
73 #define TIMER_TICK 0x82
74 #define STOP_BREAK 0x83
75 #define BASE(a) ((a) < 4 ? (short*)CIRRUS_FIRST : ((a) < 8 ? (short *)CIRRUS_SECOND : ((a) < 12 ? (short*)CIRRUS_THIRD : (short *)CIRRUS_FOURTH)))
76 #define txack1 ((short *)0x7104)
77 #define rxack1 ((short *)0x7102)
78 #define mdack1 ((short *)0x7106)
79 #define txack2 ((short *)0x7006)
80 #define rxack2 ((short *)0x7004)
81 #define mdack2 ((short *)0x7100)
82 #define int_latch ((short *) 0x7800)
83 #define int_status ((short *) 0x7c00)
84 #define tx1_pending 0x20
85 #define rx1_pending 0x10
86 #define md1_pending 0x40
87 #define tx2_pending 0x02
88 #define rx2_pending 0x01
89 #define md2_pending 0x40
90 #define module1_bits 0x07
91 #define module1_modern 0x08
92 #define module2_bits 0x70
93 #define module2_modern 0x80
94 #define module_blank 0xf
95 #define rs232_d25 0x0
96 #define rs232_rj45 0x1
97 #define rs422_d25 0x3
98 #define parallel 0x5
99
100 #define CLK0 0x00
101 #define CLK1 0x01
102 #define CLK2 0x02
103 #define CLK3 0x03
104 #define CLK4 0x04
105
106 #define CIRRUS_REVC 0x42
107 #define CIRRUS_REVE 0x44
108
109 #define TURNON 1
110 #define TURNOFF 0
111
112 /* The list of CIRRUS registers.
113 NB. These registers are relative values on 8 bit boundaries whereas
114 on the RTA's the CIRRUS registers are on word boundaries. Use pointer
115 arithmetic (short *) to obtain the real addresses required */
116 #define ccr 0x05 /* Channel Command Register */
117 #define ier 0x06 /* Interrupt Enable Register */
118 #define cor1 0x08 /* Channel Option Register 1 */
119 #define cor2 0x09 /* Channel Option Register 2 */
120 #define cor3 0x0a /* Channel Option Register 3 */
121 #define cor4 0x1e /* Channel Option Register 4 */
122 #define cor5 0x1f /* Channel Option Register 5 */
123
124 #define ccsr 0x0b /* Channel Control Status Register */
125 #define rdcr 0x0e /* Receive Data Count Register */
126 #define tdcr 0x12 /* Transmit Data Count Register */
127 #define mcor1 0x15 /* Modem Change Option Register 1 */
128 #define mcor2 0x16 /* Modem Change Option Regsiter 2 */
129
130 #define livr 0x18 /* Local Interrupt Vector Register */
131 #define schr1 0x1a /* Special Character Register 1 */
132 #define schr2 0x1b /* Special Character Register 2 */
133 #define schr3 0x1c /* Special Character Register 3 */
134 #define schr4 0x1d /* Special Character Register 4 */
135
136 #define rtr 0x20 /* Receive Timer Register */
137 #define rtpr 0x21 /* Receive Timeout Period Register */
138 #define lnc 0x24 /* Lnext character */
139
140 #define rivr 0x43 /* Receive Interrupt Vector Register */
141 #define tivr 0x42 /* Transmit Interrupt Vector Register */
142 #define mivr 0x41 /* Modem Interrupt Vector Register */
143 #define gfrcr 0x40 /* Global Firmware Revision code Reg */
144 #define ricr 0x44 /* Receive Interrupting Channel Reg */
145 #define ticr 0x45 /* Transmit Interrupting Channel Reg */
146 #define micr 0x46 /* Modem Interrupting Channel Register */
147
148 #define gcr 0x4b /* Global configuration register*/
149 #define misr 0x4c /* Modem interrupt status register */
150
151 #define rbusr 0x59
152 #define tbusr 0x5a
153 #define mbusr 0x5b
154
155 #define eoir 0x60 /* End Of Interrupt Register */
156 #define rdsr 0x62 /* Receive Data / Status Register */
157 #define tdr 0x63 /* Transmit Data Register */
158 #define svrr 0x67 /* Service Request Register */
159
160 #define car 0x68 /* Channel Access Register */
161 #define mir 0x69 /* Modem Interrupt Register */
162 #define tir 0x6a /* Transmit Interrupt Register */
163 #define rir 0x6b /* Receive Interrupt Register */
164 #define msvr1 0x6c /* Modem Signal Value Register 1 */
165 #define msvr2 0x6d /* Modem Signal Value Register 2*/
166 #define psvr 0x6f /* Printer Signal Value Register*/
167
168 #define tbpr 0x72 /* Transmit Baud Rate Period Register */
169 #define tcor 0x76 /* Transmit Clock Option Register */
170
171 #define rbpr 0x78 /* Receive Baud Rate Period Register */
172 #define rber 0x7a /* Receive Baud Rate Extension Register */
173 #define rcor 0x7c /* Receive Clock Option Register*/
174 #define ppr 0x7e /* Prescalar Period Register */
175
176 /* Misc registers used for forcing the 1400 out of its reset woes */
177 #define airl 0x6d
178 #define airm 0x6e
179 #define airh 0x6f
180 #define btcr 0x66
181 #define mtcr 0x6c
182 #define tber 0x74
183
184 #endif /* #ifdef RTA */
185
186
187 /* Bit fields for particular registers */
188
189 /* GCR */
190 #define GCR_SERIAL 0x00 /* Configure as serial channel */
191 #define GCR_PARALLEL 0x80 /* Configure as parallel channel */
192
193 /* RDSR - when status read from FIFO */
194 #define RDSR_BREAK 0x08 /* Break received */
195 #define RDSR_TIMEOUT 0x80 /* No new data timeout */
196 #define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */
197 #define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */
198 #define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */
199
200 /* PPR */
201 #define PPR_DEFAULT 0x31 /* Default value - for a 25Mhz clock gives
202 a timeout period of 1ms */
203
204 /* LIVR */
205 #define LIVR_EXCEPTION 0x07 /* Receive exception interrupt */
206
207 /* CCR */
208 #define CCR_RESET 0x80 /* Reset channel */
209 #define CCR_CHANGE 0x4e /* COR's have changed - NB always change all
210 COR's */
211 #define CCR_WFLUSH 0x82 /* Flush transmit FIFO and TSR / THR */
212
213 #define CCR_SENDSC1 0x21 /* Send special character one */
214 #define CCR_SENDSC2 0x22 /* Send special character two */
215 #define CCR_SENDSC3 0x23 /* Send special character three */
216 #define CCR_SENDSC4 0x24 /* Send special character four */
217
218 #define CCR_TENABLE 0x18 /* Enable transmitter */
219 #define CCR_TDISABLE 0x14 /* Disable transmitter */
220 #define CCR_RENABLE 0x12 /* Enable receiver */
221 #define CCR_RDISABLE 0x11 /* Disable receiver */
222
223 #define CCR_READY 0x00 /* CCR is ready for another command */
224
225 /* CCSR */
226 #define CCSR_TXENABLE 0x08 /* Transmitter enable */
227 #define CCSR_RXENABLE 0x80 /* Receiver enable */
228 #define CCSR_TXFLOWOFF 0x04 /* Transmit flow off */
229 #define CCSR_TXFLOWON 0x02 /* Transmit flow on */
230
231 /* SVRR */
232 #define SVRR_RECEIVE 0x01 /* Receive interrupt pending */
233 #define SVRR_TRANSMIT 0x02 /* Transmit interrupt pending */
234 #define SVRR_MODEM 0x04 /* Modem interrupt pending */
235
236 /* CAR */
237 #define CAR_PORTS 0x03 /* Bit fields for ports */
238
239 /* IER */
240 #define IER_MODEM 0x80 /* Change in modem status */
241 #define IER_RECEIVE 0x10 /* Good data / data exception */
242 #define IER_TRANSMITR 0x04 /* Transmit ready (FIFO empty) */
243 #define IER_TRANSMITE 0x02 /* Transmit empty */
244 #define IER_TIMEOUT 0x01 /* Timeout on no data */
245
246 #define IER_DEFAULT 0x94 /* Default values */
247 #define IER_PARALLEL 0x84 /* Default for Parallel */
248 #define IER_EMPTY 0x92 /* Transmitter empty rather than ready */
249
250 /* COR1 - Driver only */
251 #define COR1_INPCK 0x10 /* Check parity of received characters */
252
253 /* COR1 - driver and RTA */
254 #define COR1_ODD 0x80 /* Odd parity */
255 #define COR1_EVEN 0x00 /* Even parity */
256 #define COR1_NOP 0x00 /* No parity */
257 #define COR1_FORCE 0x20 /* Force parity */
258 #define COR1_NORMAL 0x40 /* With parity */
259 #define COR1_1STOP 0x00 /* 1 stop bit */
260 #define COR1_15STOP 0x04 /* 1.5 stop bits */
261 #define COR1_2STOP 0x08 /* 2 stop bits */
262 #define COR1_5BITS 0x00 /* 5 data bits */
263 #define COR1_6BITS 0x01 /* 6 data bits */
264 #define COR1_7BITS 0x02 /* 7 data bits */
265 #define COR1_8BITS 0x03 /* 8 data bits */
266
267 #define COR1_HOST 0xef /* Safe host bits */
268
269 /* RTA only */
270 #define COR1_CINPCK 0x00 /* Check parity of received characters */
271 #define COR1_CNINPCK 0x10 /* Don't check parity */
272
273 /* COR2 bits for both RTA and driver use */
274 #define COR2_IXANY 0x80 /* IXANY - any character is XON */
275 #define COR2_IXON 0x40 /* IXON - enable tx soft flowcontrol */
276 #define COR2_RTSFLOW 0x02 /* Enable tx hardware flow control */
277
278 /* Additional driver bits */
279 #define COR2_HUPCL 0x20 /* Hang up on close */
280 #define COR2_CTSFLOW 0x04 /* Enable rx hardware flow control */
281 #define COR2_IXOFF 0x01 /* Enable rx software flow control */
282 #define COR2_DTRFLOW 0x08 /* Enable tx hardware flow control */
283
284 /* RTA use only */
285 #define COR2_ETC 0x20 /* Embedded transmit options */
286 #define COR2_LOCAL 0x10 /* Local loopback mode */
287 #define COR2_REMOTE 0x08 /* Remote loopback mode */
288 #define COR2_HOST 0xc2 /* Safe host bits */
289
290 /* COR3 - RTA use only */
291 #define COR3_SCDRNG 0x80 /* Enable special char detect for range */
292 #define COR3_SCD34 0x40 /* Special character detect for SCHR's 3 + 4 */
293 #define COR3_FCT 0x20 /* Flow control transparency */
294 #define COR3_SCD12 0x10 /* Special character detect for SCHR's 1 + 2 */
295 #define COR3_FIFO12 0x0c /* 12 chars for receive FIFO threshold */
296 #define COR3_FIFO10 0x0a /* 10 chars for receive FIFO threshold */
297 #define COR3_FIFO8 0x08 /* 8 chars for receive FIFO threshold */
298 #define COR3_FIFO6 0x06 /* 6 chars for receive FIFO threshold */
299
300 #define COR3_THRESHOLD COR3_FIFO8 /* MUST BE LESS THAN MCOR_THRESHOLD */
301
302 #define COR3_DEFAULT (COR3_FCT | COR3_THRESHOLD)
303 /* Default bits for COR3 */
304
305 /* COR4 driver and RTA use */
306 #define COR4_IGNCR 0x80 /* Throw away CR's on input */
307 #define COR4_ICRNL 0x40 /* Map CR -> NL on input */
308 #define COR4_INLCR 0x20 /* Map NL -> CR on input */
309 #define COR4_IGNBRK 0x10 /* Ignore Break */
310 #define COR4_NBRKINT 0x08 /* No interrupt on break (-BRKINT) */
311 #define COR4_RAISEMOD 0x01 /* Raise modem output lines on non-zero baud */
312
313
314 /* COR4 driver only */
315 #define COR4_IGNPAR 0x04 /* IGNPAR (ignore characters with errors) */
316 #define COR4_PARMRK 0x02 /* PARMRK */
317
318 #define COR4_HOST 0xf8 /* Safe host bits */
319
320 /* COR4 RTA only */
321 #define COR4_CIGNPAR 0x02 /* Thrown away bad characters */
322 #define COR4_CPARMRK 0x04 /* PARMRK characters */
323 #define COR4_CNPARMRK 0x03 /* Don't PARMRK */
324
325 /* COR5 driver and RTA use */
326 #define COR5_ISTRIP 0x80 /* Strip input chars to 7 bits */
327 #define COR5_LNE 0x40 /* Enable LNEXT processing */
328 #define COR5_CMOE 0x20 /* Match good and errored characters */
329 #define COR5_ONLCR 0x02 /* NL -> CR NL on output */
330 #define COR5_OCRNL 0x01 /* CR -> NL on output */
331
332 /*
333 ** Spare bits - these are not used in the CIRRUS registers, so we use
334 ** them to set various other features.
335 */
336 /*
337 ** tstop and tbusy indication
338 */
339 #define COR5_TSTATE_ON 0x08 /* Turn on monitoring of tbusy and tstop */
340 #define COR5_TSTATE_OFF 0x04 /* Turn off monitoring of tbusy and tstop */
341 /*
342 ** TAB3
343 */
344 #define COR5_TAB3 0x10 /* TAB3 mode */
345
346 #define COR5_HOST 0xc3 /* Safe host bits */
347
348 /* CCSR */
349 #define CCSR_TXFLOFF 0x04 /* Tx is xoffed */
350
351 /* MSVR1 */
352 /* NB. DTR / CD swapped from Cirrus spec as the pins are also reversed on the
353 RTA. This is because otherwise DCD would get lost on the 1 parallel / 3
354 serial option.
355 */
356 #define MSVR1_CD 0x80 /* CD (DSR on Cirrus) */
357 #define MSVR1_RTS 0x40 /* RTS (CTS on Cirrus) */
358 #define MSVR1_RI 0x20 /* RI */
359 #define MSVR1_DTR 0x10 /* DTR (CD on Cirrus) */
360 #define MSVR1_CTS 0x01 /* CTS output pin (RTS on Cirrus) */
361 /* Next two used to indicate state of tbusy and tstop to driver */
362 #define MSVR1_TSTOP 0x08 /* Set if port flow controlled */
363 #define MSVR1_TEMPTY 0x04 /* Set if port tx buffer empty */
364
365 #define MSVR1_HOST 0xf3 /* The bits the host wants */
366
367 /* MSVR2 */
368 #define MSVR2_DSR 0x02 /* DSR output pin (DTR on Cirrus) */
369
370 /* MCOR */
371 #define MCOR_CD 0x80 /* CD (DSR on Cirrus) */
372 #define MCOR_RTS 0x40 /* RTS (CTS on Cirrus) */
373 #define MCOR_RI 0x20 /* RI */
374 #define MCOR_DTR 0x10 /* DTR (CD on Cirrus) */
375
376 #define MCOR_DEFAULT (MCOR_CD | MCOR_RTS | MCOR_RI | MCOR_DTR)
377 #define MCOR_FULLMODEM MCOR_DEFAULT
378 #define MCOR_RJ45 (MCOR_CD | MCOR_RTS | MCOR_DTR)
379 #define MCOR_RESTRICTED (MCOR_CD | MCOR_RTS)
380
381 /* More MCOR - H/W Handshake (flowcontrol) stuff */
382 #define MCOR_THRESH8 0x08 /* eight characters then we stop */
383 #define MCOR_THRESH9 0x09 /* nine characters then we stop */
384 #define MCOR_THRESH10 0x0A /* ten characters then we stop */
385 #define MCOR_THRESH11 0x0B /* eleven characters then we stop */
386
387 #define MCOR_THRESHBITS 0x0F /* mask for ANDing out the above */
388
389 #define MCOR_THRESHOLD MCOR_THRESH9 /* MUST BE GREATER THAN COR3_THRESHOLD */
390
391
392 /* RTPR */
393 #define RTPR_DEFAULT 0x02 /* Default */
394
395
396 /* Defines for the subscripts of a CONFIG packet */
397 #define CONFIG_COR1 1 /* Option register 1 */
398 #define CONFIG_COR2 2 /* Option register 2 */
399 #define CONFIG_COR4 3 /* Option register 4 */
400 #define CONFIG_COR5 4 /* Option register 5 */
401 #define CONFIG_TXXON 5 /* Tx XON character */
402 #define CONFIG_TXXOFF 6 /* Tx XOFF character */
403 #define CONFIG_RXXON 7 /* Rx XON character */
404 #define CONFIG_RXXOFF 8 /* Rx XOFF character */
405 #define CONFIG_LNEXT 9 /* LNEXT character */
406 #define CONFIG_TXBAUD 10 /* Tx baud rate */
407 #define CONFIG_RXBAUD 11 /* Rx baud rate */
408
409 /* Port status stuff */
410 #define IDLE_CLOSED 0 /* Closed */
411 #define IDLE_OPEN 1 /* Idle open */
412 #define IDLE_BREAK 2 /* Idle on break */
413
414 /* Subscript of MODEM STATUS packet */
415 #define MODEM_VALUE 3 /* Current values of handshake pins */
416 /* Subscript of SBREAK packet */
417 #define BREAK_LENGTH 1 /* Length of a break in slices of 0.01 seconds
418 0 = stay on break until an EBREAK command
419 is sent */
420
421
422 #define PRE_EMPTIVE 0x80 /* Pre-emptive bit in command field */
423
424 /* Packet types going from Host to remote - with the exception of OPEN, MOPEN,
425 CONFIG, SBREAK and MEMDUMP the remaining bytes of the data array will not
426 be used
427 */
428 #define OPEN 0x00 /* Open a port */
429 #define CONFIG 0x01 /* Configure a port */
430 #define MOPEN 0x02 /* Modem open (block for DCD) */
431 #define CLOSE 0x03 /* Close a port */
432 #define WFLUSH (0x04 | PRE_EMPTIVE) /* Write flush */
433 #define RFLUSH (0x05 | PRE_EMPTIVE) /* Read flush */
434 #define RESUME (0x06 | PRE_EMPTIVE) /* Resume if xoffed */
435 #define SBREAK 0x07 /* Start break */
436 #define EBREAK 0x08 /* End break */
437 #define SUSPEND (0x09 | PRE_EMPTIVE) /* Susp op (behave as tho xoffed) */
438 #define FCLOSE (0x0a | PRE_EMPTIVE) /* Force close */
439 #define XPRINT 0x0b /* Xprint packet */
440 #define MBIS (0x0c | PRE_EMPTIVE) /* Set modem lines */
441 #define MBIC (0x0d | PRE_EMPTIVE) /* Clear modem lines */
442 #define MSET (0x0e | PRE_EMPTIVE) /* Set modem lines */
443 #define PCLOSE 0x0f /* Pseudo close - Leaves rx/tx enabled */
444 #define MGET (0x10 | PRE_EMPTIVE) /* Force update of modem status */
445 #define MEMDUMP (0x11 | PRE_EMPTIVE) /* Send back mem from addr supplied */
446 #define READ_REGISTER (0x12 | PRE_EMPTIVE) /* Read CD1400 register (debug) */
447
448 /* "Command" packets going from remote to host COMPLETE and MODEM_STATUS
449 use data[4] / data[3] to indicate current state and modem status respectively
450 */
451
452 #define COMPLETE (0x20 | PRE_EMPTIVE)
453 /* Command complete */
454 #define BREAK_RECEIVED (0x21 | PRE_EMPTIVE)
455 /* Break received */
456 #define MODEM_STATUS (0x22 | PRE_EMPTIVE)
457 /* Change in modem status */
458
459 /* "Command" packet that could go either way - handshake wake-up */
460 #define HANDSHAKE (0x23 | PRE_EMPTIVE)
461 /* Wake-up to HOST / RTA */
462
463 #endif
464