File: /usr/src/linux/drivers/char/rocket_int.h
1 /*
2 * rocket_int.h --- internal header file for rocket.c
3 *
4 * Written by Theodore Ts'o, Copyright 1997.
5 *
6 * Portions of this file are....
7 *
8 * Copyright 1994 Comtrol Corporation. All Rights Reserved.
9 *
10 * The following source code is subject to Comtrol Corporation's
11 * Developer's License Agreement.
12 *
13 * This source code is protected by United States copyright law and
14 * international copyright treaties.
15 *
16 * This source code may only be used to develop software products that
17 * will operate with Comtrol brand hardware.
18 *
19 * You may not reproduce nor distribute this source code in its original
20 * form but must produce a derivative work which includes portions of
21 * this source code only.
22 *
23 * The portions of this source code which you use in your derivative
24 * work must bear Comtrol's copyright notice:
25 *
26 * Copyright 1994 Comtrol Corporation.
27 *
28 */
29
30 /*
31 * Begin Comtrol-provided headers, et. al.
32 */
33
34 /*
35 user definitions for Rocket Toolkit
36
37 The following typedefs and defines must be established
38 depending on the platform the toolkit is being used
39 with.
40
41 */
42
43 /************************************************************
44 The following sets up the world for use with Linux
45 ************************************************************/
46
47 #include <asm/io.h>
48
49 typedef unsigned char Byte_t;
50 typedef unsigned int ByteIO_t;
51
52 typedef unsigned int Word_t;
53 typedef unsigned int WordIO_t;
54
55 typedef unsigned long DWord_t;
56 typedef unsigned int DWordIO_t;
57
58 #define sOutB(a, b) outb_p(b, a)
59 #define sOutW(a, b) outw_p(b, a)
60 #define sOutDW(a, b) outl_p(b, a)
61 #define sInB(a) (inb_p(a))
62 #define sInW(a) (inw_p(a))
63
64 #define sOutStrW(port, addr, count) outsw(port, addr, count)
65
66 #define sInStrW(port, addr, count) insw(port, addr, count)
67
68 #define CTL_SIZE 4
69 #define AIOP_CTL_SIZE 4
70 #define CHAN_AIOP_SIZE 8
71 #define MAX_PORTS_PER_AIOP 8
72 #define MAX_AIOPS_PER_BOARD 4
73 #define MAX_PORTS_PER_BOARD 32
74
75 /* Bus type ID */
76 #define isISA 0
77 #define isPCI 1
78 #define isMC 2
79
80 /* Controller ID numbers */
81 #define CTLID_NULL -1 /* no controller exists */
82 #define CTLID_0001 0x0001 /* controller release 1 */
83
84 /* AIOP ID numbers, identifies AIOP type implementing channel */
85 #define AIOPID_NULL -1 /* no AIOP or channel exists */
86 #define AIOPID_0001 0x0001 /* AIOP release 1 */
87
88 #define NULLDEV -1 /* identifies non-existant device */
89 #define NULLCTL -1 /* identifies non-existant controller */
90 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
91 #define NULLAIOP -1 /* identifies non-existant AIOP */
92 #define NULLCHAN -1 /* identifies non-existant channel */
93
94 /************************************************************************
95 Global Register Offsets - Direct Access - Fixed values
96 ************************************************************************/
97
98 #define _CMD_REG 0x38 /* Command Register 8 Write */
99 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
100 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
101 #define _UNUSED 0x3B /* Unused 8 */
102 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
103 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
104
105 /************************************************************************
106 Channel Register Offsets for 1st channel in AIOP - Direct Access
107 ************************************************************************/
108 #define _TD0 0x00 /* Transmit Data 16 Write */
109 #define _RD0 0x00 /* Receive Data 16 Read */
110 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
111 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
112 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
113
114 /************************************************************************
115 Tx Control Register Offsets - Indexed - External - Fixed
116 ************************************************************************/
117 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
118 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
119 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
120 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
121 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
122 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
123
124 /************************************************************************
125 Memory Controller Register Offsets - Indexed - External - Fixed
126 ************************************************************************/
127 #define _RX_FIFO 0x000 /* Rx FIFO */
128 #define _TX_FIFO 0x800 /* Tx FIFO */
129 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
130 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
131 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
132 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
133 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
134 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
135
136 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
137 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
138 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
139
140 /************************************************************************
141 Tx Priority Buffer - Indexed - External - Fixed
142 ************************************************************************/
143 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
144 #define TXP_SIZE 0x20 /* 32 bytes */
145
146 /************************************************************************
147 Channel Register Offsets - Indexed - Internal - Fixed
148 ************************************************************************/
149
150 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
151 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
152 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
153 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
154
155 #if 0
156 #define CLOCK_PRESC 0x14 /* ?????? new mod 4 (divide by 5) prescale */
157
158 #define BRD50 9215
159 #define BRD75 6143
160 #define BRD110 4188
161 #define BRD134 3438
162 #define BRD150 3071
163 #define BRD200 2303
164 #define BRD300 1535
165 #define BRD600 767
166 #define BRD1200 383
167 #define BRD1800 255
168 #define BRD2000 229
169 #define BRD2400 191
170 #define BRD3600 127
171 #define BRD4800 95
172 #define BRD7200 63
173 #define BRD9600 47
174 #define BRD14400 31
175 #define BRD19200 23
176 #define BRD38400 11
177 #define BRD57600 7
178 #define BRD76800 5
179 #define BRD115200 3
180 #define BRD230400 1
181 #define BRD460800 0
182 #endif
183
184 #if 0
185
186 /* Old clock prescale definition and baud rates associated with it */
187
188 #define CLOCK_PRESC 0x19 */ /* mod 9 (divide by 10) prescale */
189 #define BRD50 4607
190 #define BRD75 3071
191 #define BRD110 2094
192 #define BRD134 1712
193 #define BRD150 1535
194 #define BRD200 1151
195 #define BRD300 767
196 #define BRD600 383
197 #define BRD1200 191
198 #define BRD1800 127
199 #define BRD2000 114
200 #define BRD2400 95
201 #define BRD3600 64
202 #define BRD4800 47
203 #define BRD7200 31
204 #define BRD9600 23
205 #define BRD14400 15
206 #define BRD19200 11
207 #define BRD38400 5
208 #define BRD57600 3
209 #define BRD76800 2
210 #define BRD115200 1
211 #define BRD230400 0
212
213 #endif
214
215 #define STMBREAK 0x08 /* BREAK */
216 #define STMFRAME 0x04 /* framing error */
217 #define STMRCVROVR 0x02 /* receiver over run error */
218 #define STMPARITY 0x01 /* parity error */
219 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
220 #define STMBREAKH 0x800 /* BREAK */
221 #define STMFRAMEH 0x400 /* framing error */
222 #define STMRCVROVRH 0x200 /* receiver over run error */
223 #define STMPARITYH 0x100 /* parity error */
224 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
225
226 #define CTS_ACT 0x20 /* CTS input asserted */
227 #define DSR_ACT 0x10 /* DSR input asserted */
228 #define CD_ACT 0x08 /* CD input asserted */
229 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
230 #define TXSHRMT 0x02 /* Tx shift register is empty */
231 #define RDA 0x01 /* Rx data available */
232 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
233
234 #define STATMODE 0x8000 /* status mode enable bit */
235 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
236 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
237 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
238 #define RXBREAK 0x0400 /* received BREAK */
239 #define RXFRAME 0x0200 /* received framing error */
240 #define RXPARITY 0x0100 /* received parity error */
241 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
242
243 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
244 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
245 #define TXINT_EN 0x10 /* transmit interrupt enable */
246 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
247 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
248 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
249 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
250
251 #define SETBREAK 0x10 /* send break condition (must clear) */
252 #define LOCALLOOP 0x08 /* local loopback set for test */
253 #define SET_DTR 0x04 /* assert DTR */
254 #define SET_RTS 0x02 /* assert RTS */
255 #define TX_ENABLE 0x01 /* enable transmitter */
256
257 #define RTSFC_EN 0x40 /* RTS flow control enable */
258 #define RXPROC_EN 0x20 /* receive processor enable */
259 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
260 #define TRIG_1 0x08 /* trigger level 1 char */
261 #define TRIG_1_2 0x10 /* trigger level 1/2 */
262 #define TRIG_7_8 0x18 /* trigger level 7/8 */
263 #define TRIG_MASK 0x18 /* trigger level mask */
264 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
265 #define RXINT_EN 0x02 /* Rx interrupt enable */
266 #define MCINT_EN 0x01 /* modem change interrupt enable */
267
268 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
269 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
270 #define SRC_INT 0x08 /* special receive condition interrupt */
271 #define DELTA_CD 0x04 /* CD change interrupt */
272 #define DELTA_CTS 0x02 /* CTS change interrupt */
273 #define DELTA_DSR 0x01 /* DSR change interrupt */
274
275 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
276 #define IGN2_EN 0x08 /* ignore byte 2 enable */
277 #define IGN1_EN 0x04 /* ignore byte 1 enable */
278 #define COMP2_EN 0x02 /* compare byte 2 enable */
279 #define COMP1_EN 0x01 /* compare byte 1 enable */
280
281 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
282 #define TXOVERIDE 0x40 /* Transmit software off override */
283 #define RESETUART 0x20 /* reset channel's UART */
284 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
285 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
286
287 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
288 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
289 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
290 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
291
292 #define INTR_EN 0x08 /* allow interrupts to host */
293 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
294
295 /**************************************************************************
296 MUDBAC remapped for PCI
297 **************************************************************************/
298
299 #define _CFG_INT_PCI 0x40
300 #define _PCI_INT_FUNC 0x3A
301
302 #define PCI_STROB 0x2000 /* bit 13 of int aiop register */
303 #define INTR_EN_PCI 0x0010 /* allow interrupts to host */
304
305
306 #define CHAN3_EN 0x08 /* enable AIOP 3 */
307 #define CHAN2_EN 0x04 /* enable AIOP 2 */
308 #define CHAN1_EN 0x02 /* enable AIOP 1 */
309 #define CHAN0_EN 0x01 /* enable AIOP 0 */
310 #define FREQ_DIS 0x00
311 #define FREQ_274HZ 0x60
312 #define FREQ_137HZ 0x50
313 #define FREQ_69HZ 0x40
314 #define FREQ_34HZ 0x30
315 #define FREQ_17HZ 0x20
316 #define FREQ_9HZ 0x10
317 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
318
319 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
320
321 #define RDATASIZE 72
322 #define RREGDATASIZE 52
323
324 /* Controller level information structure */
325 typedef struct
326 {
327 int CtlID;
328 int CtlNum;
329 int BusType;
330 WordIO_t PCIIO;
331 ByteIO_t MBaseIO;
332 ByteIO_t MReg1IO;
333 ByteIO_t MReg2IO;
334 ByteIO_t MReg3IO;
335 Byte_t MReg2;
336 Byte_t MReg3;
337 int NumAiop;
338 WordIO_t AiopIO[AIOP_CTL_SIZE];
339 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
340 int AiopID[AIOP_CTL_SIZE];
341 int AiopNumChan[AIOP_CTL_SIZE];
342 } CONTROLLER_T;
343
344 typedef CONTROLLER_T CONTROLLER_t;
345
346 /* Channel level information structure */
347 typedef struct
348 {
349 CONTROLLER_T *CtlP;
350 int AiopNum;
351 int ChanID;
352 int ChanNum;
353
354 ByteIO_t Cmd;
355 ByteIO_t IntChan;
356 ByteIO_t IntMask;
357 DWordIO_t IndexAddr;
358 WordIO_t IndexData;
359
360 WordIO_t TxRxData;
361 WordIO_t ChanStat;
362 WordIO_t TxRxCount;
363 ByteIO_t IntID;
364
365 Word_t TxFIFO;
366 Word_t TxFIFOPtrs;
367 Word_t RxFIFO;
368 Word_t RxFIFOPtrs;
369 Word_t TxPrioCnt;
370 Word_t TxPrioPtr;
371 Word_t TxPrioBuf;
372
373 Byte_t R[RREGDATASIZE];
374
375 Byte_t BaudDiv[4];
376 Byte_t TxControl[4];
377 Byte_t RxControl[4];
378 Byte_t TxEnables[4];
379 Byte_t TxCompare[4];
380 Byte_t TxReplace1[4];
381 Byte_t TxReplace2[4];
382 } CHANNEL_T;
383
384 typedef CHANNEL_T CHANNEL_t;
385 typedef CHANNEL_T * CHANPTR_T;
386
387 /***************************************************************************
388 Function: sClrBreak
389 Purpose: Stop sending a transmit BREAK signal
390 Call: sClrBreak(ChP)
391 CHANNEL_T *ChP; Ptr to channel structure
392 */
393 #define sClrBreak(ChP) \
394 { \
395 (ChP)->TxControl[3] &= ~SETBREAK; \
396 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
397 }
398
399 /***************************************************************************
400 Function: sClrDTR
401 Purpose: Clr the DTR output
402 Call: sClrDTR(ChP)
403 CHANNEL_T *ChP; Ptr to channel structure
404 */
405 #define sClrDTR(ChP) \
406 { \
407 (ChP)->TxControl[3] &= ~SET_DTR; \
408 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
409 }
410
411 /***************************************************************************
412 Function: sClrRTS
413 Purpose: Clr the RTS output
414 Call: sClrRTS(ChP)
415 CHANNEL_T *ChP; Ptr to channel structure
416 */
417 #define sClrRTS(ChP) \
418 { \
419 (ChP)->TxControl[3] &= ~SET_RTS; \
420 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
421 }
422
423 /***************************************************************************
424 Function: sClrTxXOFF
425 Purpose: Clear any existing transmit software flow control off condition
426 Call: sClrTxXOFF(ChP)
427 CHANNEL_T *ChP; Ptr to channel structure
428 */
429 #define sClrTxXOFF(ChP) \
430 { \
431 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
432 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
433 }
434
435 /***************************************************************************
436 Function: sCtlNumToCtlPtr
437 Purpose: Convert a controller number to controller structure pointer
438 Call: sCtlNumToCtlPtr(CtlNum)
439 int CtlNum; Controller number
440 Return: CONTROLLER_T *: Ptr to controller structure
441 */
442 #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
443
444 /***************************************************************************
445 Function: sControllerEOI
446 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
447 Call: sControllerEOI(CtlP)
448 CONTROLLER_T *CtlP; Ptr to controller structure
449 */
450 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
451
452 /***************************************************************************
453 Function: sPCIControllerEOI
454 Purpose: Strobe the PCI End Of Interrupt bit.
455 Call: sPCIControllerEOI(CtlP)
456 CONTROLLER_T *CtlP; Ptr to controller structure
457 */
458 #define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB)
459
460 /***************************************************************************
461 Function: sDisAiop
462 Purpose: Disable I/O access to an AIOP
463 Call: sDisAiop(CltP)
464 CONTROLLER_T *CtlP; Ptr to controller structure
465 int AiopNum; Number of AIOP on controller
466 */
467 #define sDisAiop(CTLP,AIOPNUM) \
468 { \
469 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
470 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
471 }
472
473 /***************************************************************************
474 Function: sDisCTSFlowCtl
475 Purpose: Disable output flow control using CTS
476 Call: sDisCTSFlowCtl(ChP)
477 CHANNEL_T *ChP; Ptr to channel structure
478 */
479 #define sDisCTSFlowCtl(ChP) \
480 { \
481 (ChP)->TxControl[2] &= ~CTSFC_EN; \
482 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
483 }
484
485 /***************************************************************************
486 Function: sDisIXANY
487 Purpose: Disable IXANY Software Flow Control
488 Call: sDisIXANY(ChP)
489 CHANNEL_T *ChP; Ptr to channel structure
490 */
491 #define sDisIXANY(ChP) \
492 { \
493 (ChP)->R[0x0e] = 0x86; \
494 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
495 }
496
497 /***************************************************************************
498 Function: DisParity
499 Purpose: Disable parity
500 Call: sDisParity(ChP)
501 CHANNEL_T *ChP; Ptr to channel structure
502 Comments: Function sSetParity() can be used in place of functions sEnParity(),
503 sDisParity(), sSetOddParity(), and sSetEvenParity().
504 */
505 #define sDisParity(ChP) \
506 { \
507 (ChP)->TxControl[2] &= ~PARITY_EN; \
508 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
509 }
510
511 /***************************************************************************
512 Function: sDisRxFIFO
513 Purpose: Disable Rx FIFO
514 Call: sDisRxFIFO(ChP)
515 CHANNEL_T *ChP; Ptr to channel structure
516 */
517 #define sDisRxFIFO(ChP) \
518 { \
519 (ChP)->R[0x32] = 0x0a; \
520 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
521 }
522
523 /***************************************************************************
524 Function: sDisRxStatusMode
525 Purpose: Disable the Rx status mode
526 Call: sDisRxStatusMode(ChP)
527 CHANNEL_T *ChP; Ptr to channel structure
528 Comments: This takes the channel out of the receive status mode. All
529 subsequent reads of receive data using sReadRxWord() will return
530 two data bytes.
531 */
532 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
533
534 /***************************************************************************
535 Function: sDisTransmit
536 Purpose: Disable transmit
537 Call: sDisTransmit(ChP)
538 CHANNEL_T *ChP; Ptr to channel structure
539 This disables movement of Tx data from the Tx FIFO into the 1 byte
540 Tx buffer. Therefore there could be up to a 2 byte latency
541 between the time sDisTransmit() is called and the transmit buffer
542 and transmit shift register going completely empty.
543 */
544 #define sDisTransmit(ChP) \
545 { \
546 (ChP)->TxControl[3] &= ~TX_ENABLE; \
547 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
548 }
549
550 /***************************************************************************
551 Function: sDisTxSoftFlowCtl
552 Purpose: Disable Tx Software Flow Control
553 Call: sDisTxSoftFlowCtl(ChP)
554 CHANNEL_T *ChP; Ptr to channel structure
555 */
556 #define sDisTxSoftFlowCtl(ChP) \
557 { \
558 (ChP)->R[0x06] = 0x8a; \
559 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
560 }
561
562 /***************************************************************************
563 Function: sEnAiop
564 Purpose: Enable I/O access to an AIOP
565 Call: sEnAiop(CltP)
566 CONTROLLER_T *CtlP; Ptr to controller structure
567 int AiopNum; Number of AIOP on controller
568 */
569 #define sEnAiop(CTLP,AIOPNUM) \
570 { \
571 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
572 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
573 }
574
575 /***************************************************************************
576 Function: sEnCTSFlowCtl
577 Purpose: Enable output flow control using CTS
578 Call: sEnCTSFlowCtl(ChP)
579 CHANNEL_T *ChP; Ptr to channel structure
580 */
581 #define sEnCTSFlowCtl(ChP) \
582 { \
583 (ChP)->TxControl[2] |= CTSFC_EN; \
584 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
585 }
586
587 /***************************************************************************
588 Function: sEnIXANY
589 Purpose: Enable IXANY Software Flow Control
590 Call: sEnIXANY(ChP)
591 CHANNEL_T *ChP; Ptr to channel structure
592 */
593 #define sEnIXANY(ChP) \
594 { \
595 (ChP)->R[0x0e] = 0x21; \
596 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
597 }
598
599 /***************************************************************************
600 Function: EnParity
601 Purpose: Enable parity
602 Call: sEnParity(ChP)
603 CHANNEL_T *ChP; Ptr to channel structure
604 Comments: Function sSetParity() can be used in place of functions sEnParity(),
605 sDisParity(), sSetOddParity(), and sSetEvenParity().
606
607 Warnings: Before enabling parity odd or even parity should be chosen using
608 functions sSetOddParity() or sSetEvenParity().
609 */
610 #define sEnParity(ChP) \
611 { \
612 (ChP)->TxControl[2] |= PARITY_EN; \
613 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
614 }
615
616 /***************************************************************************
617 Function: sEnRxFIFO
618 Purpose: Enable Rx FIFO
619 Call: sEnRxFIFO(ChP)
620 CHANNEL_T *ChP; Ptr to channel structure
621 */
622 #define sEnRxFIFO(ChP) \
623 { \
624 (ChP)->R[0x32] = 0x08; \
625 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
626 }
627
628 /***************************************************************************
629 Function: sEnRxProcessor
630 Purpose: Enable the receive processor
631 Call: sEnRxProcessor(ChP)
632 CHANNEL_T *ChP; Ptr to channel structure
633 Comments: This function is used to start the receive processor. When
634 the channel is in the reset state the receive processor is not
635 running. This is done to prevent the receive processor from
636 executing invalid microcode instructions prior to the
637 downloading of the microcode.
638
639 Warnings: This function must be called after valid microcode has been
640 downloaded to the AIOP, and it must not be called before the
641 microcode has been downloaded.
642 */
643 #define sEnRxProcessor(ChP) \
644 { \
645 (ChP)->RxControl[2] |= RXPROC_EN; \
646 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
647 }
648
649 /***************************************************************************
650 Function: sEnRxStatusMode
651 Purpose: Enable the Rx status mode
652 Call: sEnRxStatusMode(ChP)
653 CHANNEL_T *ChP; Ptr to channel structure
654 Comments: This places the channel in the receive status mode. All subsequent
655 reads of receive data using sReadRxWord() will return a data byte
656 in the low word and a status byte in the high word.
657
658 */
659 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
660
661 /***************************************************************************
662 Function: sEnTransmit
663 Purpose: Enable transmit
664 Call: sEnTransmit(ChP)
665 CHANNEL_T *ChP; Ptr to channel structure
666 */
667 #define sEnTransmit(ChP) \
668 { \
669 (ChP)->TxControl[3] |= TX_ENABLE; \
670 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
671 }
672
673 /***************************************************************************
674 Function: sEnTxSoftFlowCtl
675 Purpose: Enable Tx Software Flow Control
676 Call: sEnTxSoftFlowCtl(ChP)
677 CHANNEL_T *ChP; Ptr to channel structure
678 */
679 #define sEnTxSoftFlowCtl(ChP) \
680 { \
681 (ChP)->R[0x06] = 0xc5; \
682 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
683 }
684
685 /***************************************************************************
686 Function: sGetAiopIntStatus
687 Purpose: Get the AIOP interrupt status
688 Call: sGetAiopIntStatus(CtlP,AiopNum)
689 CONTROLLER_T *CtlP; Ptr to controller structure
690 int AiopNum; AIOP number
691 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
692 represent channels 0 through 7 respectively. If a
693 bit is set that channel is interrupting.
694 */
695 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
696
697 /***************************************************************************
698 Function: sGetAiopNumChan
699 Purpose: Get the number of channels supported by an AIOP
700 Call: sGetAiopNumChan(CtlP,AiopNum)
701 CONTROLLER_T *CtlP; Ptr to controller structure
702 int AiopNum; AIOP number
703 Return: int: The number of channels supported by the AIOP
704 */
705 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
706
707 /***************************************************************************
708 Function: sGetChanIntID
709 Purpose: Get a channel's interrupt identification byte
710 Call: sGetChanIntID(ChP)
711 CHANNEL_T *ChP; Ptr to channel structure
712 Return: Byte_t: The channel interrupt ID. Can be any
713 combination of the following flags:
714 RXF_TRIG: Rx FIFO trigger level interrupt
715 TXFIFO_MT: Tx FIFO empty interrupt
716 SRC_INT: Special receive condition interrupt
717 DELTA_CD: CD change interrupt
718 DELTA_CTS: CTS change interrupt
719 DELTA_DSR: DSR change interrupt
720 */
721 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
722
723 /***************************************************************************
724 Function: sGetChanNum
725 Purpose: Get the number of a channel within an AIOP
726 Call: sGetChanNum(ChP)
727 CHANNEL_T *ChP; Ptr to channel structure
728 Return: int: Channel number within AIOP, or NULLCHAN if channel does
729 not exist.
730 */
731 #define sGetChanNum(ChP) (ChP)->ChanNum
732
733 /***************************************************************************
734 Function: sGetChanStatus
735 Purpose: Get the channel status
736 Call: sGetChanStatus(ChP)
737 CHANNEL_T *ChP; Ptr to channel structure
738 Return: Word_t: The channel status. Can be any combination of
739 the following flags:
740 LOW BYTE FLAGS
741 CTS_ACT: CTS input asserted
742 DSR_ACT: DSR input asserted
743 CD_ACT: CD input asserted
744 TXFIFOMT: Tx FIFO is empty
745 TXSHRMT: Tx shift register is empty
746 RDA: Rx data available
747
748 HIGH BYTE FLAGS
749 STATMODE: status mode enable bit
750 RXFOVERFL: receive FIFO overflow
751 RX2MATCH: receive compare byte 2 match
752 RX1MATCH: receive compare byte 1 match
753 RXBREAK: received BREAK
754 RXFRAME: received framing error
755 RXPARITY: received parity error
756 Warnings: This function will clear the high byte flags in the Channel
757 Status Register.
758 */
759 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
760
761 /***************************************************************************
762 Function: sGetChanStatusLo
763 Purpose: Get the low byte only of the channel status
764 Call: sGetChanStatusLo(ChP)
765 CHANNEL_T *ChP; Ptr to channel structure
766 Return: Byte_t: The channel status low byte. Can be any combination
767 of the following flags:
768 CTS_ACT: CTS input asserted
769 DSR_ACT: DSR input asserted
770 CD_ACT: CD input asserted
771 TXFIFOMT: Tx FIFO is empty
772 TXSHRMT: Tx shift register is empty
773 RDA: Rx data available
774 */
775 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
776
777 /***************************************************************************
778 Function: sGetControllerIntStatus
779 Purpose: Get the controller interrupt status
780 Call: sGetControllerIntStatus(CtlP)
781 CONTROLLER_T *CtlP; Ptr to controller structure
782 Return: Byte_t: The controller interrupt status in the lower 4
783 bits. Bits 0 through 3 represent AIOP's 0
784 through 3 respectively. If a bit is set that
785 AIOP is interrupting. Bits 4 through 7 will
786 always be cleared.
787 */
788 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
789
790 /***************************************************************************
791 Function: sPCIGetControllerIntStatus
792 Purpose: Get the controller interrupt status
793 Call: sPCIGetControllerIntStatus(CtlP)
794 CONTROLLER_T *CtlP; Ptr to controller structure
795 Return: unsigned char: The controller interrupt status in the lower 4
796 bits and bit 4. Bits 0 through 3 represent AIOP's 0
797 through 3 respectively. Bit 4 is set if the int
798 was generated from periodic. If a bit is set the
799 AIOP is interrupting.
800 */
801 #define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f)
802
803 /***************************************************************************
804
805 Function: sGetRxCnt
806 Purpose: Get the number of data bytes in the Rx FIFO
807 Call: sGetRxCnt(ChP)
808 CHANNEL_T *ChP; Ptr to channel structure
809 Return: int: The number of data bytes in the Rx FIFO.
810 Comments: Byte read of count register is required to obtain Rx count.
811
812 */
813 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
814
815 /***************************************************************************
816 Function: sGetTxCnt
817 Purpose: Get the number of data bytes in the Tx FIFO
818 Call: sGetTxCnt(ChP)
819 CHANNEL_T *ChP; Ptr to channel structure
820 Return: Byte_t: The number of data bytes in the Tx FIFO.
821 Comments: Byte read of count register is required to obtain Tx count.
822
823 */
824 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
825
826 /*****************************************************************************
827 Function: sGetTxRxDataIO
828 Purpose: Get the I/O address of a channel's TxRx Data register
829 Call: sGetTxRxDataIO(ChP)
830 CHANNEL_T *ChP; Ptr to channel structure
831 Return: WordIO_t: I/O address of a channel's TxRx Data register
832 */
833 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
834
835 /***************************************************************************
836 Function: sInitChanDefaults
837 Purpose: Initialize a channel structure to it's default state.
838 Call: sInitChanDefaults(ChP)
839 CHANNEL_T *ChP; Ptr to the channel structure
840 Comments: This function must be called once for every channel structure
841 that exists before any other SSCI calls can be made.
842
843 */
844 #define sInitChanDefaults(ChP) \
845 { \
846 (ChP)->CtlP = NULLCTLPTR; \
847 (ChP)->AiopNum = NULLAIOP; \
848 (ChP)->ChanID = AIOPID_NULL; \
849 (ChP)->ChanNum = NULLCHAN; \
850 }
851
852 /***************************************************************************
853 Function: sResetAiopByNum
854 Purpose: Reset the AIOP by number
855 Call: sResetAiopByNum(CTLP,AIOPNUM)
856 CONTROLLER_T CTLP; Ptr to controller structure
857 AIOPNUM; AIOP index
858 */
859 #define sResetAiopByNum(CTLP,AIOPNUM) \
860 { \
861 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
862 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
863 }
864
865 /***************************************************************************
866 Function: sSendBreak
867 Purpose: Send a transmit BREAK signal
868 Call: sSendBreak(ChP)
869 CHANNEL_T *ChP; Ptr to channel structure
870 */
871 #define sSendBreak(ChP) \
872 { \
873 (ChP)->TxControl[3] |= SETBREAK; \
874 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
875 }
876
877 /***************************************************************************
878 Function: sSetBaud
879 Purpose: Set baud rate
880 Call: sSetBaud(ChP,Divisor)
881 CHANNEL_T *ChP; Ptr to channel structure
882 Word_t Divisor; 16 bit baud rate divisor for channel
883 */
884 #define sSetBaud(ChP,DIVISOR) \
885 { \
886 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
887 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
888 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
889 }
890
891 /***************************************************************************
892 Function: sSetData7
893 Purpose: Set data bits to 7
894 Call: sSetData7(ChP)
895 CHANNEL_T *ChP; Ptr to channel structure
896 */
897 #define sSetData7(ChP) \
898 { \
899 (ChP)->TxControl[2] &= ~DATA8BIT; \
900 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
901 }
902
903 /***************************************************************************
904 Function: sSetData8
905 Purpose: Set data bits to 8
906 Call: sSetData8(ChP)
907 CHANNEL_T *ChP; Ptr to channel structure
908 */
909 #define sSetData8(ChP) \
910 { \
911 (ChP)->TxControl[2] |= DATA8BIT; \
912 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
913 }
914
915 /***************************************************************************
916 Function: sSetDTR
917 Purpose: Set the DTR output
918 Call: sSetDTR(ChP)
919 CHANNEL_T *ChP; Ptr to channel structure
920 */
921 #define sSetDTR(ChP) \
922 { \
923 (ChP)->TxControl[3] |= SET_DTR; \
924 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
925 }
926
927 /***************************************************************************
928 Function: sSetEvenParity
929 Purpose: Set even parity
930 Call: sSetEvenParity(ChP)
931 CHANNEL_T *ChP; Ptr to channel structure
932 Comments: Function sSetParity() can be used in place of functions sEnParity(),
933 sDisParity(), sSetOddParity(), and sSetEvenParity().
934
935 Warnings: This function has no effect unless parity is enabled with function
936 sEnParity().
937 */
938 #define sSetEvenParity(ChP) \
939 { \
940 (ChP)->TxControl[2] |= EVEN_PAR; \
941 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
942 }
943
944 /***************************************************************************
945 Function: sSetOddParity
946 Purpose: Set odd parity
947 Call: sSetOddParity(ChP)
948 CHANNEL_T *ChP; Ptr to channel structure
949 Comments: Function sSetParity() can be used in place of functions sEnParity(),
950 sDisParity(), sSetOddParity(), and sSetEvenParity().
951
952 Warnings: This function has no effect unless parity is enabled with function
953 sEnParity().
954 */
955 #define sSetOddParity(ChP) \
956 { \
957 (ChP)->TxControl[2] &= ~EVEN_PAR; \
958 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
959 }
960
961 /***************************************************************************
962 Function: sSetRTS
963 Purpose: Set the RTS output
964 Call: sSetRTS(ChP)
965 CHANNEL_T *ChP; Ptr to channel structure
966 */
967 #define sSetRTS(ChP) \
968 { \
969 (ChP)->TxControl[3] |= SET_RTS; \
970 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
971 }
972
973 /***************************************************************************
974 Function: sSetRxTrigger
975 Purpose: Set the Rx FIFO trigger level
976 Call: sSetRxProcessor(ChP,Level)
977 CHANNEL_T *ChP; Ptr to channel structure
978 Byte_t Level; Number of characters in Rx FIFO at which the
979 interrupt will be generated. Can be any of the following flags:
980
981 TRIG_NO: no trigger
982 TRIG_1: 1 character in FIFO
983 TRIG_1_2: FIFO 1/2 full
984 TRIG_7_8: FIFO 7/8 full
985 Comments: An interrupt will be generated when the trigger level is reached
986 only if function sEnInterrupt() has been called with flag
987 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
988 register will be set whenever the trigger level is reached
989 regardless of the setting of RXINT_EN.
990
991 */
992 #define sSetRxTrigger(ChP,LEVEL) \
993 { \
994 (ChP)->RxControl[2] &= ~TRIG_MASK; \
995 (ChP)->RxControl[2] |= LEVEL; \
996 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
997 }
998
999 /***************************************************************************
1000 Function: sSetStop1
1001 Purpose: Set stop bits to 1
1002 Call: sSetStop1(ChP)
1003 CHANNEL_T *ChP; Ptr to channel structure
1004 */
1005 #define sSetStop1(ChP) \
1006 { \
1007 (ChP)->TxControl[2] &= ~STOP2; \
1008 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1009 }
1010
1011 /***************************************************************************
1012 Function: sSetStop2
1013 Purpose: Set stop bits to 2
1014 Call: sSetStop2(ChP)
1015 CHANNEL_T *ChP; Ptr to channel structure
1016 */
1017 #define sSetStop2(ChP) \
1018 { \
1019 (ChP)->TxControl[2] |= STOP2; \
1020 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1021 }
1022
1023 /***************************************************************************
1024 Function: sSetTxXOFFChar
1025 Purpose: Set the Tx XOFF flow control character
1026 Call: sSetTxXOFFChar(ChP,Ch)
1027 CHANNEL_T *ChP; Ptr to channel structure
1028 Byte_t Ch; The value to set the Tx XOFF character to
1029 */
1030 #define sSetTxXOFFChar(ChP,CH) \
1031 { \
1032 (ChP)->R[0x07] = (CH); \
1033 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
1034 }
1035
1036 /***************************************************************************
1037 Function: sSetTxXONChar
1038 Purpose: Set the Tx XON flow control character
1039 Call: sSetTxXONChar(ChP,Ch)
1040 CHANNEL_T *ChP; Ptr to channel structure
1041 Byte_t Ch; The value to set the Tx XON character to
1042 */
1043 #define sSetTxXONChar(ChP,CH) \
1044 { \
1045 (ChP)->R[0x0b] = (CH); \
1046 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
1047 }
1048
1049 /***************************************************************************
1050 Function: sStartRxProcessor
1051 Purpose: Start a channel's receive processor
1052 Call: sStartRxProcessor(ChP)
1053 CHANNEL_T *ChP; Ptr to channel structure
1054 Comments: This function is used to start a Rx processor after it was
1055 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
1056 will restart both the Rx processor and software input flow control.
1057
1058 */
1059 #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
1060
1061 /***************************************************************************
1062 Function: sWriteTxByte
1063 Purpose: Write a transmit data byte to a channel.
1064 ByteIO_t io: Channel transmit register I/O address. This can
1065 be obtained with sGetTxRxDataIO().
1066 Byte_t Data; The transmit data byte.
1067 Warnings: This function writes the data byte without checking to see if
1068 sMaxTxSize is exceeded in the Tx FIFO.
1069 */
1070 #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1071
1072 int sInitController( CONTROLLER_T *CtlP,
1073 int CtlNum,
1074 ByteIO_t MudbacIO,
1075 ByteIO_t *AiopIOList,
1076 int AiopIOListSize,
1077 int IRQNum,
1078 Byte_t Frequency,
1079 int PeriodicOnly);
1080
1081 int sPCIInitController( CONTROLLER_T *CtlP,
1082 int CtlNum,
1083 ByteIO_t *AiopIOList,
1084 int AiopIOListSize,
1085 int IRQNum,
1086 Byte_t Frequency,
1087 int PeriodicOnly);
1088
1089 int sReadAiopID(ByteIO_t io);
1090 int sReadAiopNumChan(WordIO_t io);
1091 int sInitChan( CONTROLLER_T *CtlP,
1092 CHANNEL_T *ChP,
1093 int AiopNum,
1094 int ChanNum);
1095 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
1096 void sStopRxProcessor(CHANNEL_T *ChP);
1097 void sStopSWInFlowCtl(CHANNEL_T *ChP);
1098 void sFlushRxFIFO(CHANNEL_T *ChP);
1099 void sFlushTxFIFO(CHANNEL_T *ChP);
1100 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1101 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1102 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1103
1104 extern Byte_t R[RDATASIZE];
1105 extern CONTROLLER_T sController[CTL_SIZE];
1106 extern Byte_t sIRQMap[16];
1107 extern Byte_t sBitMapClrTbl[8];
1108 extern Byte_t sBitMapSetTbl[8];
1109 extern int sClockPrescale;
1110
1111
1112 /*
1113 * Begin Linux specific definitions for the Rocketport driver
1114 *
1115 * This code is Copyright Theodore Ts'o, 1995-1997
1116 */
1117
1118 struct r_port {
1119 int magic;
1120 int line;
1121 int flags;
1122 int count;
1123 int blocked_open;
1124 struct tty_struct *tty;
1125 int board:2;
1126 int aiop:2;
1127 int chan:3;
1128 CONTROLLER_t *ctlp;
1129 CHANNEL_t channel;
1130 int closing_wait;
1131 int close_delay;
1132 int intmask;
1133 int xmit_fifo_room; /* room in xmit fifo */
1134 unsigned char *xmit_buf;
1135 int xmit_head;
1136 int xmit_tail;
1137 int xmit_cnt;
1138 int session;
1139 int pgrp;
1140 int cd_status;
1141 int ignore_status_mask;
1142 int read_status_mask;
1143 int cps;
1144 struct termios normal_termios;
1145 struct termios callout_termios;
1146 struct tq_struct tqueue;
1147 wait_queue_head_t open_wait;
1148 wait_queue_head_t close_wait;
1149 };
1150
1151 #define RPORT_MAGIC 0x525001
1152
1153 #define NUM_BOARDS 8
1154 #define MAX_RP_PORTS (32*NUM_BOARDS)
1155
1156 /*
1157 * The size of the xmit buffer is 1 page, or 4096 bytes
1158 */
1159 #define XMIT_BUF_SIZE 4096
1160
1161 /* number of characters left in xmit buffer before we ask for more */
1162 #define WAKEUP_CHARS 256
1163
1164 /* Internal flags used only by the rocketport driver */
1165 #define ROCKET_INITIALIZED 0x80000000 /* Port is active */
1166 #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */
1167 #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */
1168 #define ROCKET_CALLOUT_ACTIVE 0x10000000 /* Callout port is active */
1169
1170 /*
1171 * tty subtypes
1172 *
1173 */
1174 #define SERIAL_TYPE_NORMAL 1
1175 #define SERIAL_TYPE_CALLOUT 2
1176
1177 /*
1178 * Assigned major numbers for the Comtrol Rocketport
1179 */
1180 #define TTY_ROCKET_MAJOR 46
1181 #define CUA_ROCKET_MAJOR 47
1182
1183 /*
1184 * Utility function.
1185 */
1186 #ifndef MIN
1187 #define MIN(a,b) ((a) < (b) ? (a) : (b))
1188 #endif
1189
1190 #ifdef PCI_VENDOR_ID_RP
1191 #undef PCI_VENDOR_ID_RP
1192 #undef PCI_DEVICE_ID_RP8OCTA
1193 #undef PCI_DEVICE_ID_RP8INTF
1194 #undef PCI_DEVICE_ID_RP16INTF
1195 #undef PCI_DEVICE_ID_RP32INTF
1196 #endif
1197
1198 #define PCI_VENDOR_ID_RP 0x11fe
1199 #define PCI_DEVICE_ID_RP32INTF 0x0001
1200 #define PCI_DEVICE_ID_RP8INTF 0x0002
1201 #define PCI_DEVICE_ID_RP16INTF 0x0003
1202 #define PCI_DEVICE_ID_RP8OCTA 0x0005
1203
1204 #ifndef PCI_DEVICE_ID_RP4QUAD
1205 #define PCI_DEVICE_ID_RP4QUAD 0x0004
1206 #endif
1207 #ifndef PCI_DEVICE_ID_RP8J
1208 #define PCI_DEVICE_ID_RP8J 0x0006
1209 #endif
1210 #ifndef PCI_DEVICE_ID_RPP4
1211 #define PCI_DEVICE_ID_RPP4 0x000A
1212 #endif
1213 #ifndef PCI_DEVICE_ID_RPP8
1214 #define PCI_DEVICE_ID_RPP8 0x000B
1215 #endif
1216 #ifndef PCI_DEVICE_ID_RP8M
1217 #define PCI_DEVICE_ID_RP8M 0x000C
1218 #endif
1219
1220