File: /usr/src/linux/arch/arm/kernel/bios32.c
1 /*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13
14 #include <asm/page.h> /* for BUG() */
15 #include <asm/irq.h>
16 #include <asm/mach-types.h>
17 #include <asm/mach/pci.h>
18
19 static int debug_pci;
20 int have_isa_bridge;
21
22 struct pci_sys_data {
23 /*
24 * The hardware we are attached to
25 */
26 struct hw_pci *hw;
27
28 unsigned long mem_offset;
29
30 /*
31 * These are the resources for the root bus.
32 */
33 struct resource *resource[3];
34 };
35
36 void pcibios_report_status(u_int status_mask, int warn)
37 {
38 struct pci_dev *dev;
39
40 pci_for_each_dev(dev) {
41 u16 status;
42
43 /*
44 * ignore host bridge - we handle
45 * that separately
46 */
47 if (dev->bus->number == 0 && dev->devfn == 0)
48 continue;
49
50 pci_read_config_word(dev, PCI_STATUS, &status);
51
52 status &= status_mask;
53 if (status == 0)
54 continue;
55
56 /* clear the status errors */
57 pci_write_config_word(dev, PCI_STATUS, status);
58
59 if (warn)
60 printk("(%02x:%02x.%d: %04X) ", dev->bus->number,
61 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
62 status);
63 }
64 }
65
66 /*
67 * We don't use this to fix the device, but initialisation of it.
68 * It's not the correct use for this, but it works.
69 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
70 * the following area:
71 * 1. park on CPU
72 * 2. ISA bridge ping-pong
73 * 3. ISA bridge master handling of target RETRY
74 *
75 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
76 * live with bug 2.
77 */
78 static void __init pci_fixup_83c553(struct pci_dev *dev)
79 {
80 /*
81 * Set memory region to start at address 0, and enable IO
82 */
83 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
84 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
85
86 dev->resource[0].end -= dev->resource[0].start;
87 dev->resource[0].start = 0;
88
89 /*
90 * All memory requests from ISA to be channelled to PCI
91 */
92 pci_write_config_byte(dev, 0x48, 0xff);
93
94 /*
95 * Enable ping-pong on bus master to ISA bridge transactions.
96 * This improves the sound DMA substantially. The fixed
97 * priority arbiter also helps (see below).
98 */
99 pci_write_config_byte(dev, 0x42, 0x01);
100
101 /*
102 * Enable PCI retry
103 */
104 pci_write_config_byte(dev, 0x40, 0x22);
105
106 /*
107 * We used to set the arbiter to "park on last master" (bit
108 * 1 set), but unfortunately the CyberPro does not park the
109 * bus. We must therefore park on CPU. Unfortunately, this
110 * may trigger yet another bug in the 553.
111 */
112 pci_write_config_byte(dev, 0x83, 0x02);
113
114 /*
115 * Make the ISA DMA request lowest priority, and disable
116 * rotating priorities completely.
117 */
118 pci_write_config_byte(dev, 0x80, 0x11);
119 pci_write_config_byte(dev, 0x81, 0x00);
120
121 /*
122 * Route INTA input to IRQ 11, and set IRQ11 to be level
123 * sensitive.
124 */
125 pci_write_config_word(dev, 0x44, 0xb000);
126 outb(0x08, 0x4d1);
127 }
128
129 static void __init pci_fixup_unassign(struct pci_dev *dev)
130 {
131 dev->resource[0].end -= dev->resource[0].start;
132 dev->resource[0].start = 0;
133 }
134
135 /*
136 * Prevent the PCI layer from seeing the resources allocated to this device
137 * if it is the host bridge by marking it as such. These resources are of
138 * no consequence to the PCI layer (they are handled elsewhere).
139 */
140 static void __init pci_fixup_dec21285(struct pci_dev *dev)
141 {
142 int i;
143
144 if (dev->devfn == 0) {
145 dev->class &= 0xff;
146 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
147 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
148 dev->resource[i].start = 0;
149 dev->resource[i].end = 0;
150 dev->resource[i].flags = 0;
151 }
152 }
153 }
154
155 /*
156 * PCI IDE controllers use non-standard I/O port
157 * decoding, respect it.
158 */
159 static void __init pci_fixup_ide_bases(struct pci_dev *dev)
160 {
161 struct resource *r;
162 int i;
163
164 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
165 return;
166
167 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
168 r = dev->resource + i;
169 if ((r->start & ~0x80) == 0x374) {
170 r->start |= 2;
171 r->end = r->start;
172 }
173 }
174 }
175
176 /*
177 * Put the DEC21142 to sleep
178 */
179 static void __init pci_fixup_dec21142(struct pci_dev *dev)
180 {
181 pci_write_config_dword(dev, 0x40, 0x80000000);
182 }
183
184 struct pci_fixup pcibios_fixups[] = {
185 {
186 PCI_FIXUP_HEADER,
187 PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285,
188 pci_fixup_dec21285
189 }, {
190 PCI_FIXUP_HEADER,
191 PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553,
192 pci_fixup_83c553
193 }, {
194 PCI_FIXUP_HEADER,
195 PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F,
196 pci_fixup_unassign
197 }, {
198 PCI_FIXUP_HEADER,
199 PCI_ANY_ID, PCI_ANY_ID,
200 pci_fixup_ide_bases
201 }, {
202 PCI_FIXUP_HEADER,
203 PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
204 pci_fixup_dec21142
205 }, { 0 }
206 };
207
208 void __init
209 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
210 struct resource *res, int resource)
211 {
212 struct pci_sys_data *sys = dev->sysdata;
213 u32 val, check;
214 int reg;
215
216 if (debug_pci)
217 printk("PCI: Assigning %3s %08lx to %s\n",
218 res->flags & IORESOURCE_IO ? "IO" : "MEM",
219 res->start, dev->name);
220
221 if (resource < 6) {
222 reg = PCI_BASE_ADDRESS_0 + 4*resource;
223 } else if (resource == PCI_ROM_RESOURCE) {
224 reg = dev->rom_base_reg;
225 } else {
226 /* Somebody might have asked allocation of a
227 * non-standard resource.
228 */
229 return;
230 }
231
232 val = res->start;
233 if (res->flags & IORESOURCE_MEM)
234 val -= sys->mem_offset;
235 val |= res->flags & PCI_REGION_FLAG_MASK;
236
237 pci_write_config_dword(dev, reg, val);
238 pci_read_config_dword(dev, reg, &check);
239 if ((val ^ check) & ((val & PCI_BASE_ADDRESS_SPACE_IO) ?
240 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
241 printk(KERN_ERR "PCI: Error while updating region "
242 "%s/%d (%08x != %08x)\n", dev->slot_name,
243 resource, val, check);
244 }
245 }
246
247 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
248 {
249 if (debug_pci)
250 printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
251 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
252 }
253
254 /*
255 * If the bus contains any of these devices, then we must not turn on
256 * parity checking of any kind. Currently this is CyberPro 20x0 only.
257 */
258 static inline int pdev_bad_for_parity(struct pci_dev *dev)
259 {
260 return (dev->vendor == PCI_VENDOR_ID_INTERG &&
261 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
262 dev->device == PCI_DEVICE_ID_INTERG_2010));
263 }
264
265 /*
266 * Adjust the device resources from bus-centric to Linux-centric.
267 */
268 static void __init
269 pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
270 {
271 int i;
272
273 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
274 if (dev->resource[i].start == 0)
275 continue;
276 if (dev->resource[i].flags & IORESOURCE_MEM) {
277 dev->resource[i].start += root->mem_offset;
278 dev->resource[i].end += root->mem_offset;
279 }
280 }
281 }
282
283 static void __init
284 pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
285 {
286 struct pci_dev *dev = bus->self;
287 int i;
288
289 if (dev) {
290 for (i = 0; i < 3; i++) {
291 bus->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
292 bus->resource[i]->name = bus->name;
293 }
294 bus->resource[0]->flags |= pci_bridge_check_io(dev);
295 bus->resource[1]->flags |= IORESOURCE_MEM;
296
297 if (root->resource[2])
298 bus->resource[2]->flags = root->resource[2]->flags;
299 else {
300 /* no prefetchable memory region - disable it */
301 bus->resource[2]->start = 1024*1024;
302 bus->resource[2]->end = bus->resource[2]->start - 1;
303 }
304 } else {
305 /*
306 * Assign root bus resources.
307 */
308 for (i = 0; i < 3; i++)
309 bus->resource[i] = root->resource[i];
310 }
311 }
312
313 /*
314 * pcibios_fixup_bus - Called after each bus is probed,
315 * but before its children are examined.
316 */
317 void __init pcibios_fixup_bus(struct pci_bus *bus)
318 {
319 struct pci_sys_data *root = bus->sysdata;
320 struct list_head *walk;
321 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
322 u16 all_status = -1;
323
324 pbus_assign_bus_resources(bus, root);
325
326 /*
327 * Walk the devices on this bus, working out what we can
328 * and can't support.
329 */
330 for (walk = bus->devices.next; walk != &bus->devices; walk = walk->next) {
331 struct pci_dev *dev = pci_dev_b(walk);
332 u16 status;
333
334 pdev_fixup_device_resources(root, dev);
335
336 pci_read_config_word(dev, PCI_STATUS, &status);
337 all_status &= status;
338
339 if (pdev_bad_for_parity(dev))
340 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
341
342 /*
343 * If this device is an ISA bridge, set the have_isa_bridge
344 * flag. We will then go looking for things like keyboard,
345 * etc
346 */
347 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA ||
348 dev->class >> 8 == PCI_CLASS_BRIDGE_EISA)
349 have_isa_bridge = !0;
350 }
351
352 /*
353 * If any device on this bus does not support fast back to back
354 * transfers, then the bus as a whole is not able to support them.
355 * Having fast back to back transfers on saves us one PCI cycle
356 * per transaction.
357 */
358 if (all_status & PCI_STATUS_FAST_BACK)
359 features |= PCI_COMMAND_FAST_BACK;
360
361 /*
362 * Now walk the devices again, this time setting them up.
363 */
364 for (walk = bus->devices.next; walk != &bus->devices; walk = walk->next) {
365 struct pci_dev *dev = pci_dev_b(walk);
366 u16 cmd;
367
368 pci_read_config_word(dev, PCI_COMMAND, &cmd);
369 cmd |= features;
370 pci_write_config_word(dev, PCI_COMMAND, cmd);
371 }
372
373 /*
374 * Report what we did for this bus
375 */
376 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
377 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
378 }
379
380 /*
381 * Convert from Linux-centric to bus-centric addresses for bridge devices.
382 */
383 void __init
384 pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
385 {
386 struct pci_sys_data *root = bus->sysdata;
387
388 ranges->mem_start -= root->mem_offset;
389 ranges->mem_end -= root->mem_offset;
390 ranges->prefetch_start -= root->mem_offset;
391 ranges->prefetch_end -= root->mem_offset;
392 }
393
394 u8 __init no_swizzle(struct pci_dev *dev, u8 *pin)
395 {
396 return 0;
397 }
398
399 extern struct hw_pci ebsa285_pci;
400 extern struct hw_pci cats_pci;
401 extern struct hw_pci netwinder_pci;
402 extern struct hw_pci personal_server_pci;
403 extern struct hw_pci ftv_pci;
404 extern struct hw_pci shark_pci;
405 extern struct hw_pci integrator_pci;
406
407 void __init pcibios_init(void)
408 {
409 struct pci_sys_data *root;
410 struct hw_pci *hw = NULL;
411
412 do {
413 #ifdef CONFIG_ARCH_EBSA285
414 if (machine_is_ebsa285()) {
415 hw = &ebsa285_pci;
416 break;
417 }
418 #endif
419 #ifdef CONFIG_ARCH_SHARK
420 if (machine_is_shark()) {
421 hw = &shark_pci;
422 break;
423 }
424 #endif
425 #ifdef CONFIG_ARCH_CATS
426 if (machine_is_cats()) {
427 hw = &cats_pci;
428 break;
429 }
430 #endif
431 #ifdef CONFIG_ARCH_NETWINDER
432 if (machine_is_netwinder()) {
433 hw = &netwinder_pci;
434 break;
435 }
436 #endif
437 #ifdef CONFIG_ARCH_PERSONAL_SERVER
438 if (machine_is_personal_server()) {
439 hw = &personal_server_pci;
440 break;
441 }
442 #endif
443 #ifdef CONFIG_ARCH_FTVPCI
444 if (machine_is_ftvpci()) {
445 hw = &ftv_pci;
446 break;
447 }
448 #endif
449 #ifdef CONFIG_ARCH_INTEGRATOR
450 if (machine_is_integrator()) {
451 hw = &integrator_pci;
452 break;
453 }
454 #endif
455 } while (0);
456
457 if (hw == NULL)
458 return;
459
460 root = kmalloc(sizeof(*root), GFP_KERNEL);
461 if (!root)
462 panic("PCI: unable to allocate root data!");
463
464 root->hw = hw;
465 root->mem_offset = hw->mem_offset;
466
467 memset(root->resource, 0, sizeof(root->resource));
468
469 /*
470 * Setup the resources for this bus.
471 * resource[0] - IO ports
472 * resource[1] - non-prefetchable memory
473 * resource[2] - prefetchable memory
474 */
475 if (root->hw->setup_resources)
476 root->hw->setup_resources(root->resource);
477 else {
478 root->resource[0] = &ioport_resource;
479 root->resource[1] = &iomem_resource;
480 root->resource[2] = NULL;
481 }
482
483 /*
484 * Set up the host bridge, and scan the bus.
485 */
486 root->hw->init(root);
487
488 /*
489 * Assign any unassigned resources.
490 */
491 pci_assign_unassigned_resources();
492 pci_fixup_irqs(root->hw->swizzle, root->hw->map_irq);
493 }
494
495 char * __init pcibios_setup(char *str)
496 {
497 if (!strcmp(str, "debug")) {
498 debug_pci = 1;
499 return NULL;
500 }
501 return str;
502 }
503
504 /*
505 * From arch/i386/kernel/pci-i386.c:
506 *
507 * We need to avoid collisions with `mirrored' VGA ports
508 * and other strange ISA hardware, so we always want the
509 * addresses to be allocated in the 0x000-0x0ff region
510 * modulo 0x400.
511 *
512 * Why? Because some silly external IO cards only decode
513 * the low 10 bits of the IO address. The 0x00-0xff region
514 * is reserved for motherboard devices that decode all 16
515 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
516 * but we want to try to avoid allocating at 0x2900-0x2bff
517 * which might be mirrored at 0x0100-0x03ff..
518 */
519 void pcibios_align_resource(void *data, struct resource *res, unsigned long size)
520 {
521 if (res->flags & IORESOURCE_IO) {
522 unsigned long start = res->start;
523
524 if (start & 0x300)
525 res->start = (start + 0x3ff) & ~0x3ff;
526 }
527 }
528
529 /**
530 * pcibios_enable_device - Enable I/O and memory.
531 * @dev: PCI device to be enabled
532 */
533 int pcibios_enable_device(struct pci_dev *dev)
534 {
535 u16 cmd, old_cmd;
536 int idx;
537 struct resource *r;
538
539 pci_read_config_word(dev, PCI_COMMAND, &cmd);
540 old_cmd = cmd;
541 for (idx = 0; idx < 6; idx++) {
542 r = dev->resource + idx;
543 if (!r->start && r->end) {
544 printk(KERN_ERR "PCI: Device %s not available because"
545 " of resource collisions\n", dev->slot_name);
546 return -EINVAL;
547 }
548 if (r->flags & IORESOURCE_IO)
549 cmd |= PCI_COMMAND_IO;
550 if (r->flags & IORESOURCE_MEM)
551 cmd |= PCI_COMMAND_MEMORY;
552 }
553 if (cmd != old_cmd) {
554 printk("PCI: enabling device %s (%04x -> %04x)\n",
555 dev->slot_name, old_cmd, cmd);
556 pci_write_config_word(dev, PCI_COMMAND, cmd);
557 }
558 return 0;
559 }
560