File: /usr/src/linux/arch/arm/kernel/dma-rpc.c
1 /*
2 * linux/arch/arm/kernel/dma-rpc.c
3 *
4 * Copyright (C) 1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * DMA functions specific to RiscPC architecture
11 */
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/mman.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17
18 #include <asm/page.h>
19 #include <asm/dma.h>
20 #include <asm/fiq.h>
21 #include <asm/io.h>
22 #include <asm/irq.h>
23 #include <asm/hardware.h>
24 #include <asm/uaccess.h>
25
26 #include <asm/mach/dma.h>
27 #include <asm/hardware/iomd.h>
28
29 #if 0
30 typedef enum {
31 dma_size_8 = 1,
32 dma_size_16 = 2,
33 dma_size_32 = 4,
34 dma_size_128 = 16
35 } dma_size_t;
36
37 typedef struct {
38 dma_size_t transfersize;
39 } dma_t;
40 #endif
41
42 #define TRANSFER_SIZE 2
43
44 #define CURA (0)
45 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
46 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
47 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
48 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
49 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
50
51 #define state_prog_a 0
52 #define state_wait_a 1
53 #define state_wait_b 2
54
55 static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
56 {
57 unsigned long end, offset, flags = 0;
58
59 if (dma->sg) {
60 sg->dma_address = dma->sg->dma_address;
61 offset = sg->dma_address & ~PAGE_MASK;
62
63 end = offset + dma->sg->length;
64
65 if (end > PAGE_SIZE)
66 end = PAGE_SIZE;
67
68 if (offset + (int) TRANSFER_SIZE > end)
69 flags |= DMA_END_L;
70
71 sg->length = end - TRANSFER_SIZE;
72
73 dma->sg->length -= end - offset;
74 dma->sg->dma_address += end - offset;
75
76 if (dma->sg->length == 0) {
77 if (dma->sgcount > 1) {
78 dma->sg++;
79 dma->sgcount--;
80 } else {
81 dma->sg = NULL;
82 flags |= DMA_END_S;
83 }
84 }
85 } else {
86 flags = DMA_END_S | DMA_END_L;
87 sg->dma_address = 0;
88 sg->length = 0;
89 }
90
91 sg->length |= flags;
92 }
93
94 static inline void iomd_setup_dma_a(struct scatterlist *sg, dma_t *dma)
95 {
96 iomd_writel(sg->dma_address, dma->dma_base + CURA);
97 iomd_writel(sg->length, dma->dma_base + ENDA);
98 }
99
100 static inline void iomd_setup_dma_b(struct scatterlist *sg, dma_t *dma)
101 {
102 iomd_writel(sg->dma_address, dma->dma_base + CURB);
103 iomd_writel(sg->length, dma->dma_base + ENDB);
104 }
105
106 static void iomd_dma_handle(int irq, void *dev_id, struct pt_regs *regs)
107 {
108 dma_t *dma = (dma_t *)dev_id;
109 unsigned int status = 0, no_buffer = dma->sg == NULL;
110
111 do {
112 switch (dma->state) {
113 case state_prog_a:
114 iomd_get_next_sg(&dma->cur_sg, dma);
115 iomd_setup_dma_a(&dma->cur_sg, dma);
116 dma->state = state_wait_a;
117
118 case state_wait_a:
119 status = iomd_readb(dma->dma_base + ST);
120 switch (status & (DMA_ST_OFL|DMA_ST_INT|DMA_ST_AB)) {
121 case DMA_ST_OFL|DMA_ST_INT:
122 iomd_get_next_sg(&dma->cur_sg, dma);
123 iomd_setup_dma_a(&dma->cur_sg, dma);
124 break;
125
126 case DMA_ST_INT:
127 iomd_get_next_sg(&dma->cur_sg, dma);
128 iomd_setup_dma_b(&dma->cur_sg, dma);
129 dma->state = state_wait_b;
130 break;
131
132 case DMA_ST_OFL|DMA_ST_INT|DMA_ST_AB:
133 iomd_setup_dma_b(&dma->cur_sg, dma);
134 dma->state = state_wait_b;
135 break;
136 }
137 break;
138
139 case state_wait_b:
140 status = iomd_readb(dma->dma_base + ST);
141 switch (status & (DMA_ST_OFL|DMA_ST_INT|DMA_ST_AB)) {
142 case DMA_ST_OFL|DMA_ST_INT|DMA_ST_AB:
143 iomd_get_next_sg(&dma->cur_sg, dma);
144 iomd_setup_dma_b(&dma->cur_sg, dma);
145 break;
146
147 case DMA_ST_INT|DMA_ST_AB:
148 iomd_get_next_sg(&dma->cur_sg, dma);
149 iomd_setup_dma_a(&dma->cur_sg, dma);
150 dma->state = state_wait_a;
151 break;
152
153 case DMA_ST_OFL|DMA_ST_INT:
154 iomd_setup_dma_a(&dma->cur_sg, dma);
155 dma->state = state_wait_a;
156 break;
157 }
158 break;
159 }
160 } while (dma->sg && (status & DMA_ST_INT));
161
162 if (no_buffer)
163 disable_irq(irq);
164 }
165
166 static int iomd_request_dma(dmach_t channel, dma_t *dma)
167 {
168 return request_irq(dma->dma_irq, iomd_dma_handle,
169 SA_INTERRUPT, dma->device_id, dma);
170 }
171
172 static void iomd_free_dma(dmach_t channel, dma_t *dma)
173 {
174 free_irq(dma->dma_irq, dma);
175 }
176
177 static void iomd_enable_dma(dmach_t channel, dma_t *dma)
178 {
179 unsigned long dma_base = dma->dma_base;
180 unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
181
182 if (dma->invalid) {
183 dma->invalid = 0;
184
185 /*
186 * Cope with ISA-style drivers which expect cache
187 * coherence.
188 */
189 if (!dma->using_sg) {
190 dma->buf.dma_address = pci_map_single(NULL,
191 dma->buf.address, dma->buf.length,
192 dma->dma_mode == DMA_MODE_READ ?
193 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
194 }
195
196 iomd_writeb(DMA_CR_C, dma_base + CR);
197 dma->state = state_prog_a;
198 }
199
200 if (dma->dma_mode == DMA_MODE_READ)
201 ctrl |= DMA_CR_D;
202
203 iomd_writeb(ctrl, dma_base + CR);
204 enable_irq(dma->dma_irq);
205 }
206
207 static void iomd_disable_dma(dmach_t channel, dma_t *dma)
208 {
209 unsigned long dma_base = dma->dma_base;
210 unsigned int ctrl;
211
212 disable_irq(dma->dma_irq);
213 ctrl = iomd_readb(dma_base + CR);
214 iomd_writeb(ctrl & ~DMA_CR_E, dma_base + CR);
215 }
216
217 static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle)
218 {
219 int tcr, speed;
220
221 if (cycle < 188)
222 speed = 3;
223 else if (cycle <= 250)
224 speed = 2;
225 else if (cycle < 438)
226 speed = 1;
227 else
228 speed = 0;
229
230 tcr = iomd_readb(IOMD_DMATCR);
231 speed &= 3;
232
233 switch (channel) {
234 case DMA_0:
235 tcr = (tcr & ~0x03) | speed;
236 break;
237
238 case DMA_1:
239 tcr = (tcr & ~0x0c) | (speed << 2);
240 break;
241
242 case DMA_2:
243 tcr = (tcr & ~0x30) | (speed << 4);
244 break;
245
246 case DMA_3:
247 tcr = (tcr & ~0xc0) | (speed << 6);
248 break;
249
250 default:
251 break;
252 }
253
254 iomd_writeb(tcr, IOMD_DMATCR);
255
256 return speed;
257 }
258
259 static struct dma_ops iomd_dma_ops = {
260 type: "IOMD",
261 request: iomd_request_dma,
262 free: iomd_free_dma,
263 enable: iomd_enable_dma,
264 disable: iomd_disable_dma,
265 setspeed: iomd_set_dma_speed,
266 };
267
268 static struct fiq_handler fh = {
269 name: "floppydma"
270 };
271
272 static void floppy_enable_dma(dmach_t channel, dma_t *dma)
273 {
274 void *fiqhandler_start;
275 unsigned int fiqhandler_length;
276 struct pt_regs regs;
277
278 if (dma->dma_mode == DMA_MODE_READ) {
279 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
280 fiqhandler_start = &floppy_fiqin_start;
281 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
282 } else {
283 extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
284 fiqhandler_start = &floppy_fiqout_start;
285 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
286 }
287
288 regs.ARM_r9 = dma->buf.length;
289 regs.ARM_r10 = (unsigned long)dma->buf.address;
290 regs.ARM_fp = FLOPPYDMA_BASE;
291
292 if (claim_fiq(&fh)) {
293 printk("floppydma: couldn't claim FIQ.\n");
294 return;
295 }
296
297 set_fiq_handler(fiqhandler_start, fiqhandler_length);
298 set_fiq_regs(®s);
299 enable_fiq(dma->dma_irq);
300 }
301
302 static void floppy_disable_dma(dmach_t channel, dma_t *dma)
303 {
304 disable_fiq(dma->dma_irq);
305 release_fiq(&fh);
306 }
307
308 static int floppy_get_residue(dmach_t channel, dma_t *dma)
309 {
310 struct pt_regs regs;
311 get_fiq_regs(®s);
312 return regs.ARM_r9;
313 }
314
315 static struct dma_ops floppy_dma_ops = {
316 type: "FIQDMA",
317 enable: floppy_enable_dma,
318 disable: floppy_disable_dma,
319 residue: floppy_get_residue,
320 };
321
322 /*
323 * This is virtual DMA - we don't need anything here.
324 */
325 static void sound_enable_disable_dma(dmach_t channel, dma_t *dma)
326 {
327 }
328
329 static struct dma_ops sound_dma_ops = {
330 type: "VIRTUAL",
331 enable: sound_enable_disable_dma,
332 disable: sound_enable_disable_dma,
333 };
334
335 void __init arch_dma_init(dma_t *dma)
336 {
337 iomd_writeb(0, IOMD_IO0CR);
338 iomd_writeb(0, IOMD_IO1CR);
339 iomd_writeb(0, IOMD_IO2CR);
340 iomd_writeb(0, IOMD_IO3CR);
341
342 iomd_writeb(0xa0, IOMD_DMATCR);
343
344 dma[DMA_0].dma_base = IOMD_IO0CURA;
345 dma[DMA_0].dma_irq = IRQ_DMA0;
346 dma[DMA_0].d_ops = &iomd_dma_ops;
347 dma[DMA_1].dma_base = IOMD_IO1CURA;
348 dma[DMA_1].dma_irq = IRQ_DMA1;
349 dma[DMA_1].d_ops = &iomd_dma_ops;
350 dma[DMA_2].dma_base = IOMD_IO2CURA;
351 dma[DMA_2].dma_irq = IRQ_DMA2;
352 dma[DMA_2].d_ops = &iomd_dma_ops;
353 dma[DMA_3].dma_base = IOMD_IO3CURA;
354 dma[DMA_3].dma_irq = IRQ_DMA3;
355 dma[DMA_3].d_ops = &iomd_dma_ops;
356 dma[DMA_S0].dma_base = IOMD_SD0CURA;
357 dma[DMA_S0].dma_irq = IRQ_DMAS0;
358 dma[DMA_S0].d_ops = &iomd_dma_ops;
359 dma[DMA_S1].dma_base = IOMD_SD1CURA;
360 dma[DMA_S1].dma_irq = IRQ_DMAS1;
361 dma[DMA_S1].d_ops = &iomd_dma_ops;
362 dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA;
363 dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops;
364 dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops;
365
366 /*
367 * Setup DMA channels 2,3 to be for podules
368 * and channels 0,1 for internal devices
369 */
370 iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
371 }
372