File: /usr/src/linux/drivers/ide/aec62xx.c
1 /*
2 * linux/drivers/ide/aec62xx.c Version 0.09 June. 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick (andre@linux-ide.org)
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 */
8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/timer.h>
14 #include <linux/mm.h>
15 #include <linux/ioport.h>
16 #include <linux/blkdev.h>
17 #include <linux/hdreg.h>
18
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/ide.h>
23
24 #include <asm/io.h>
25 #include <asm/irq.h>
26
27 #include "ide_modes.h"
28
29 #define DISPLAY_AEC62XX_TIMINGS
30
31 #ifndef HIGH_4
32 #define HIGH_4(H) ((H)=(H>>4))
33 #endif
34 #ifndef LOW_4
35 #define LOW_4(L) ((L)=(L-((L>>4)<<4)))
36 #endif
37 #ifndef SPLIT_BYTE
38 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
39 #endif
40 #ifndef MAKE_WORD
41 #define MAKE_WORD(W,HB,LB) ((W)=((HB<<8)+LB))
42 #endif
43
44
45 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
46 #include <linux/stat.h>
47 #include <linux/proc_fs.h>
48
49 static int aec62xx_get_info(char *, char **, off_t, int);
50 extern int (*aec62xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
51 extern char *ide_media_verbose(ide_drive_t *);
52 static struct pci_dev *bmide_dev;
53
54 static int aec62xx_get_info (char *buffer, char **addr, off_t offset, int count)
55 {
56 char *p = buffer;
57
58 u32 bibma = pci_resource_start(bmide_dev, 4);
59 u8 c0 = 0, c1 = 0;
60 u8 art = 0, uart = 0;
61
62 switch(bmide_dev->device) {
63 case PCI_DEVICE_ID_ARTOP_ATP850UF:
64 p += sprintf(p, "\n AEC6210 Chipset.\n");
65 break;
66 case PCI_DEVICE_ID_ARTOP_ATP860:
67 p += sprintf(p, "\n AEC6260 No Bios Chipset.\n");
68 break;
69 case PCI_DEVICE_ID_ARTOP_ATP860R:
70 p += sprintf(p, "\n AEC6260 Chipset.\n");
71 break;
72 default:
73 p += sprintf(p, "\n AEC62?? Chipset.\n");
74 break;
75 }
76
77 /*
78 * at that point bibma+0x2 et bibma+0xa are byte registers
79 * to investigate:
80 */
81 c0 = inb_p((unsigned short)bibma + 0x02);
82 c1 = inb_p((unsigned short)bibma + 0x0a);
83
84 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
85 (void) pci_read_config_byte(bmide_dev, 0x4a, &art);
86 p += sprintf(p, " %sabled %sabled\n",
87 (art&0x02)?" en":"dis",(art&0x04)?" en":"dis");
88 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
89 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
90 (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ",(c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
91
92 switch(bmide_dev->device) {
93 case PCI_DEVICE_ID_ARTOP_ATP850UF:
94 (void) pci_read_config_byte(bmide_dev, 0x54, &art);
95 p += sprintf(p, "DMA Mode: %s(%s) %s(%s) %s(%s) %s(%s)\n",
96 (c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
97 (art&0x02)?"2":(art&0x01)?"1":"0",
98 (c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
99 (art&0x08)?"2":(art&0x04)?"1":"0",
100 (c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
101 (art&0x20)?"2":(art&0x10)?"1":"0",
102 (c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
103 (art&0x80)?"2":(art&0x40)?"1":"0");
104 (void) pci_read_config_byte(bmide_dev, 0x40, &art);
105 p += sprintf(p, "Active: 0x%02x", art);
106 (void) pci_read_config_byte(bmide_dev, 0x42, &art);
107 p += sprintf(p, " 0x%02x", art);
108 (void) pci_read_config_byte(bmide_dev, 0x44, &art);
109 p += sprintf(p, " 0x%02x", art);
110 (void) pci_read_config_byte(bmide_dev, 0x46, &art);
111 p += sprintf(p, " 0x%02x\n", art);
112 (void) pci_read_config_byte(bmide_dev, 0x41, &art);
113 p += sprintf(p, "Recovery: 0x%02x", art);
114 (void) pci_read_config_byte(bmide_dev, 0x43, &art);
115 p += sprintf(p, " 0x%02x", art);
116 (void) pci_read_config_byte(bmide_dev, 0x45, &art);
117 p += sprintf(p, " 0x%02x", art);
118 (void) pci_read_config_byte(bmide_dev, 0x47, &art);
119 p += sprintf(p, " 0x%02x\n", art);
120 break;
121 case PCI_DEVICE_ID_ARTOP_ATP860:
122 case PCI_DEVICE_ID_ARTOP_ATP860R:
123 (void) pci_read_config_byte(bmide_dev, 0x44, &art);
124 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
125 (c0&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
126 ((art&0x06)==0x06)?"4":((art&0x05)==0x05)?"4":((art&0x04)==0x04)?"3":((art&0x03)==0x03)?"2":((art&0x02)==0x02)?"1":((art&0x01)==0x01)?"0":"?",
127 (c0&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
128 ((art&0x60)==0x60)?"4":((art&0x50)==0x50)?"4":((art&0x40)==0x40)?"3":((art&0x30)==0x30)?"2":((art&0x20)==0x20)?"1":((art&0x10)==0x10)?"0":"?");
129 (void) pci_read_config_byte(bmide_dev, 0x45, &art);
130 p += sprintf(p, " %s(%s) %s(%s)\n",
131 (c1&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
132 ((art&0x06)==0x06)?"4":((art&0x05)==0x05)?"4":((art&0x04)==0x04)?"3":((art&0x03)==0x03)?"2":((art&0x02)==0x02)?"1":((art&0x01)==0x01)?"0":"?",
133 (c1&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
134 ((art&0x60)==0x60)?"4":((art&0x50)==0x50)?"4":((art&0x40)==0x40)?"3":((art&0x30)==0x30)?"2":((art&0x20)==0x20)?"1":((art&0x10)==0x10)?"0":"?");
135 (void) pci_read_config_byte(bmide_dev, 0x40, &art);
136 p += sprintf(p, "Active: 0x%02x", HIGH_4(art));
137 (void) pci_read_config_byte(bmide_dev, 0x41, &art);
138 p += sprintf(p, " 0x%02x", HIGH_4(art));
139 (void) pci_read_config_byte(bmide_dev, 0x42, &art);
140 p += sprintf(p, " 0x%02x", HIGH_4(art));
141 (void) pci_read_config_byte(bmide_dev, 0x43, &art);
142 p += sprintf(p, " 0x%02x\n", HIGH_4(art));
143 (void) pci_read_config_byte(bmide_dev, 0x40, &art);
144 p += sprintf(p, "Recovery: 0x%02x", LOW_4(art));
145 (void) pci_read_config_byte(bmide_dev, 0x41, &art);
146 p += sprintf(p, " 0x%02x", LOW_4(art));
147 (void) pci_read_config_byte(bmide_dev, 0x42, &art);
148 p += sprintf(p, " 0x%02x", LOW_4(art));
149 (void) pci_read_config_byte(bmide_dev, 0x43, &art);
150 p += sprintf(p, " 0x%02x\n", LOW_4(art));
151 (void) pci_read_config_byte(bmide_dev, 0x49, &uart);
152 p += sprintf(p, "reg49h = 0x%02x ", uart);
153 (void) pci_read_config_byte(bmide_dev, 0x4a, &uart);
154 p += sprintf(p, "reg4ah = 0x%02x\n", uart);
155 break;
156 default:
157 break;
158 }
159
160 return p-buffer;/* => must be less than 4k! */
161 }
162 #endif /* defined(DISPLAY_AEC62xx_TIMINGS) && defined(CONFIG_PROC_FS) */
163
164 byte aec62xx_proc = 0;
165
166 #ifdef CONFIG_AEC62XX_TUNING
167
168 struct chipset_bus_clock_list_entry {
169 byte xfer_speed;
170
171 byte chipset_settings_34;
172 byte ultra_settings_34;
173
174 byte chipset_settings_33;
175 byte ultra_settings_33;
176 };
177
178 struct chipset_bus_clock_list_entry aec62xx_base [] = {
179 #ifdef CONFIG_BLK_DEV_IDEDMA
180 { XFER_UDMA_4, 0x41, 0x04, 0x31, 0x05 },
181 { XFER_UDMA_3, 0x41, 0x03, 0x31, 0x04 },
182 { XFER_UDMA_2, 0x41, 0x02, 0x31, 0x03 },
183 { XFER_UDMA_1, 0x41, 0x01, 0x31, 0x02 },
184 { XFER_UDMA_0, 0x41, 0x01, 0x31, 0x01 },
185
186 { XFER_MW_DMA_2, 0x41, 0x00, 0x31, 0x00 },
187 { XFER_MW_DMA_1, 0x42, 0x00, 0x31, 0x00 },
188 { XFER_MW_DMA_0, 0x7a, 0x00, 0x0a, 0x00 },
189 #endif /* CONFIG_BLK_DEV_IDEDMA */
190 { XFER_PIO_4, 0x41, 0x00, 0x31, 0x00 },
191 { XFER_PIO_3, 0x43, 0x00, 0x33, 0x00 },
192 { XFER_PIO_2, 0x78, 0x00, 0x08, 0x00 },
193 { XFER_PIO_1, 0x7a, 0x00, 0x0a, 0x00 },
194 { XFER_PIO_0, 0x70, 0x00, 0x00, 0x00 },
195 { 0, 0x00, 0x00, 0x00, 0x00 }
196 };
197
198 extern char *ide_xfer_verbose (byte xfer_rate);
199
200 /*
201 * TO DO: active tuning and correction of cards without a bios.
202 */
203
204 static byte pci_bus_clock_list (byte speed, struct chipset_bus_clock_list_entry * chipset_table)
205 {
206 int bus_speed = system_bus_clock();
207
208 for ( ; chipset_table->xfer_speed ; chipset_table++)
209 if (chipset_table->xfer_speed == speed) {
210 return ((byte) ((bus_speed <= 33) ? chipset_table->chipset_settings_33 : chipset_table->chipset_settings_34));
211 }
212 return 0x00;
213 }
214
215 static byte pci_bus_clock_list_ultra (byte speed, struct chipset_bus_clock_list_entry * chipset_table)
216 {
217 int bus_speed = system_bus_clock();
218
219 for ( ; chipset_table->xfer_speed ; chipset_table++)
220 if (chipset_table->xfer_speed == speed) {
221 return ((byte) ((bus_speed <= 33) ? chipset_table->ultra_settings_33 : chipset_table->ultra_settings_34));
222 }
223 return 0x00;
224 }
225
226 static int aec6210_tune_chipset (ide_drive_t *drive, byte speed)
227 {
228 ide_hwif_t *hwif = HWIF(drive);
229 struct pci_dev *dev = hwif->pci_dev;
230 int err = 0;
231 unsigned short d_conf = 0x0000;
232 byte ultra = 0x00;
233 byte ultra_conf = 0x00;
234 byte tmp0 = 0x00;
235 byte tmp1 = 0x00;
236 byte tmp2 = 0x00;
237 unsigned long flags;
238
239 __save_flags(flags); /* local CPU only */
240 __cli(); /* local CPU only */
241
242 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
243 tmp0 = pci_bus_clock_list(speed, aec62xx_base);
244 SPLIT_BYTE(tmp0,tmp1,tmp2);
245 MAKE_WORD(d_conf,tmp1,tmp2);
246 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
247
248 tmp1 = 0x00;
249 tmp2 = 0x00;
250 pci_read_config_byte(dev, 0x54, &ultra);
251 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
252 ultra_conf = pci_bus_clock_list_ultra(speed, aec62xx_base);
253 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
254 pci_write_config_byte(dev, 0x54, tmp2);
255
256 __restore_flags(flags); /* local CPU only */
257
258 err = ide_config_drive_speed(drive, speed);
259 return(err);
260 }
261
262 static int aec6260_tune_chipset (ide_drive_t *drive, byte speed)
263 {
264 ide_hwif_t *hwif = HWIF(drive);
265 struct pci_dev *dev = hwif->pci_dev;
266 byte unit = (drive->select.b.unit & 0x01);
267 byte ultra_pci = hwif->channel ? 0x45 : 0x44;
268 int err = 0;
269 byte drive_conf = 0x00;
270 byte ultra_conf = 0x00;
271 byte ultra = 0x00;
272 byte tmp1 = 0x00;
273 byte tmp2 = 0x00;
274 unsigned long flags;
275
276 __save_flags(flags); /* local CPU only */
277 __cli(); /* local CPU only */
278
279 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
280 drive_conf = pci_bus_clock_list(speed, aec62xx_base);
281 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
282
283 pci_read_config_byte(dev, ultra_pci, &ultra);
284 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
285 ultra_conf = pci_bus_clock_list_ultra(speed, aec62xx_base);
286 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
287 pci_write_config_byte(dev, ultra_pci, tmp2);
288 __restore_flags(flags); /* local CPU only */
289
290 if (!drive->init_speed)
291 drive->init_speed = speed;
292
293 err = ide_config_drive_speed(drive, speed);
294 drive->current_speed = speed;
295 return(err);
296 }
297
298
299 static int aec62xx_tune_chipset (ide_drive_t *drive, byte speed)
300 {
301 if (HWIF(drive)->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
302 return ((int) aec6210_tune_chipset(drive, speed));
303 } else {
304 return ((int) aec6260_tune_chipset(drive, speed));
305 }
306 }
307
308 #ifdef CONFIG_BLK_DEV_IDEDMA
309 static int config_aec6210_chipset_for_dma (ide_drive_t *drive, byte ultra)
310 {
311 struct hd_driveid *id = drive->id;
312 ide_hwif_t *hwif = HWIF(drive);
313 byte unit = (drive->select.b.unit & 0x01);
314 unsigned long dma_base = hwif->dma_base;
315 byte speed = -1;
316
317 if (drive->media != ide_disk)
318 return ((int) ide_dma_off_quietly);
319
320 if (((id->dma_ultra & 0x0010) ||
321 (id->dma_ultra & 0x0008) ||
322 (id->dma_ultra & 0x0004)) && (ultra)) {
323 speed = XFER_UDMA_2;
324 } else if ((id->dma_ultra & 0x0002) && (ultra)) {
325 speed = XFER_UDMA_1;
326 } else if ((id->dma_ultra & 0x0001) && (ultra)) {
327 speed = XFER_UDMA_0;
328 } else if (id->dma_mword & 0x0004) {
329 speed = XFER_MW_DMA_2;
330 } else if (id->dma_mword & 0x0002) {
331 speed = XFER_MW_DMA_1;
332 } else if (id->dma_mword & 0x0001) {
333 speed = XFER_MW_DMA_0;
334 } else if (id->dma_1word & 0x0004) {
335 speed = XFER_SW_DMA_2;
336 } else if (id->dma_1word & 0x0002) {
337 speed = XFER_SW_DMA_1;
338 } else if (id->dma_1word & 0x0001) {
339 speed = XFER_SW_DMA_0;
340 } else {
341 return ((int) ide_dma_off_quietly);
342 }
343
344 outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
345 (void) aec6210_tune_chipset(drive, speed);
346
347 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_off :
348 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
349 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
350 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
351 ide_dma_off_quietly);
352 }
353
354 static int config_aec6260_chipset_for_dma (ide_drive_t *drive, byte ultra)
355 {
356 struct hd_driveid *id = drive->id;
357 ide_hwif_t *hwif = HWIF(drive);
358 byte unit = (drive->select.b.unit & 0x01);
359 unsigned long dma_base = hwif->dma_base;
360 byte speed = -1;
361 byte ultra66 = eighty_ninty_three(drive);
362
363 if (drive->media != ide_disk)
364 return ((int) ide_dma_off_quietly);
365
366 if ((id->dma_ultra & 0x0010) && (ultra) && (ultra66)) {
367 speed = XFER_UDMA_4;
368 } else if ((id->dma_ultra & 0x0008) && (ultra) && (ultra66)) {
369 speed = XFER_UDMA_3;
370 } else if ((id->dma_ultra & 0x0004) && (ultra)) {
371 speed = XFER_UDMA_2;
372 } else if ((id->dma_ultra & 0x0002) && (ultra)) {
373 speed = XFER_UDMA_1;
374 } else if ((id->dma_ultra & 0x0001) && (ultra)) {
375 speed = XFER_UDMA_0;
376 } else if (id->dma_mword & 0x0004) {
377 speed = XFER_MW_DMA_2;
378 } else if (id->dma_mword & 0x0002) {
379 speed = XFER_MW_DMA_1;
380 } else if (id->dma_mword & 0x0001) {
381 speed = XFER_MW_DMA_0;
382 } else if (id->dma_1word & 0x0004) {
383 speed = XFER_SW_DMA_2;
384 } else if (id->dma_1word & 0x0002) {
385 speed = XFER_SW_DMA_1;
386 } else if (id->dma_1word & 0x0001) {
387 speed = XFER_SW_DMA_0;
388 } else {
389 return ((int) ide_dma_off_quietly);
390 }
391
392 outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
393 (void) aec6260_tune_chipset(drive, speed);
394
395 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
396 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
397 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
398 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
399 ide_dma_off_quietly);
400 }
401
402 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
403 {
404 switch(HWIF(drive)->pci_dev->device) {
405 case PCI_DEVICE_ID_ARTOP_ATP850UF:
406 return config_aec6210_chipset_for_dma(drive, ultra);
407 case PCI_DEVICE_ID_ARTOP_ATP860:
408 case PCI_DEVICE_ID_ARTOP_ATP860R:
409 return config_aec6260_chipset_for_dma(drive, ultra);
410 default:
411 return ((int) ide_dma_off_quietly);
412 }
413 }
414
415 #endif /* CONFIG_BLK_DEV_IDEDMA */
416
417 static void aec62xx_tune_drive (ide_drive_t *drive, byte pio)
418 {
419 byte speed;
420 byte new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
421
422 switch(pio) {
423 case 5: speed = new_pio; break;
424 case 4: speed = XFER_PIO_4; break;
425 case 3: speed = XFER_PIO_3; break;
426 case 2: speed = XFER_PIO_2; break;
427 case 1: speed = XFER_PIO_1; break;
428 default: speed = XFER_PIO_0; break;
429 }
430
431 switch(HWIF(drive)->pci_dev->device) {
432 case PCI_DEVICE_ID_ARTOP_ATP850UF:
433 (void) aec6210_tune_chipset(drive, speed);
434 case PCI_DEVICE_ID_ARTOP_ATP860:
435 case PCI_DEVICE_ID_ARTOP_ATP860R:
436 (void) aec6260_tune_chipset(drive, speed);
437 default:
438 break;
439 }
440 }
441
442 #ifdef CONFIG_BLK_DEV_IDEDMA
443 static int config_drive_xfer_rate (ide_drive_t *drive)
444 {
445 struct hd_driveid *id = drive->id;
446 ide_dma_action_t dma_func = ide_dma_on;
447
448 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
449 /* Consult the list of known "bad" drives */
450 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
451 dma_func = ide_dma_off;
452 goto fast_ata_pio;
453 }
454 dma_func = ide_dma_off_quietly;
455 if (id->field_valid & 4) {
456 if (id->dma_ultra & 0x001F) {
457 /* Force if Capable UltraDMA */
458 dma_func = config_chipset_for_dma(drive, 1);
459 if ((id->field_valid & 2) &&
460 (dma_func != ide_dma_on))
461 goto try_dma_modes;
462 }
463 } else if (id->field_valid & 2) {
464 try_dma_modes:
465 if ((id->dma_mword & 0x0007) ||
466 (id->dma_1word & 0x0007)) {
467 /* Force if Capable regular DMA modes */
468 dma_func = config_chipset_for_dma(drive, 0);
469 if (dma_func != ide_dma_on)
470 goto no_dma_set;
471 }
472 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
473 if (id->eide_dma_time > 150) {
474 goto no_dma_set;
475 }
476 /* Consult the list of known "good" drives */
477 dma_func = config_chipset_for_dma(drive, 0);
478 if (dma_func != ide_dma_on)
479 goto no_dma_set;
480 } else {
481 goto fast_ata_pio;
482 }
483 } else if ((id->capability & 8) || (id->field_valid & 2)) {
484 fast_ata_pio:
485 dma_func = ide_dma_off_quietly;
486 no_dma_set:
487 aec62xx_tune_drive(drive, 5);
488 }
489 return HWIF(drive)->dmaproc(dma_func, drive);
490 }
491
492 /*
493 * aec62xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
494 */
495 int aec62xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
496 {
497 switch (func) {
498 case ide_dma_check:
499 return config_drive_xfer_rate(drive);
500 case ide_dma_lostirq:
501 case ide_dma_timeout:
502 switch(HWIF(drive)->pci_dev->device) {
503 case PCI_DEVICE_ID_ARTOP_ATP860:
504 case PCI_DEVICE_ID_ARTOP_ATP860R:
505 // {
506 // int i = 0;
507 // byte reg49h = 0;
508 // pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, ®49h);
509 // for (i=0;i<256;i++)
510 // pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
511 // pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
512 // }
513 // return 0;
514 default:
515 break;
516 }
517 default:
518 break;
519 }
520 return ide_dmaproc(func, drive); /* use standard DMA stuff */
521 }
522 #endif /* CONFIG_BLK_DEV_IDEDMA */
523 #endif /* CONFIG_AEC62XX_TUNING */
524
525 unsigned int __init pci_init_aec62xx (struct pci_dev *dev, const char *name)
526 {
527 if (dev->resource[PCI_ROM_RESOURCE].start) {
528 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
529 printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
530 }
531
532 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
533 if (!aec62xx_proc) {
534 aec62xx_proc = 1;
535 bmide_dev = dev;
536 aec62xx_display_info = &aec62xx_get_info;
537 }
538 #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */
539
540 return dev->irq;
541 }
542
543 unsigned int __init ata66_aec62xx (ide_hwif_t *hwif)
544 {
545 byte mask = hwif->channel ? 0x02 : 0x01;
546 byte ata66 = 0;
547
548 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
549 return ((ata66 & mask) ? 0 : 1);
550 }
551
552 void __init ide_init_aec62xx (ide_hwif_t *hwif)
553 {
554 #ifdef CONFIG_AEC62XX_TUNING
555 hwif->tuneproc = &aec62xx_tune_drive;
556 hwif->speedproc = &aec62xx_tune_chipset;
557 #ifdef CONFIG_BLK_DEV_IDEDMA
558 if (hwif->dma_base)
559 hwif->dmaproc = &aec62xx_dmaproc;
560 #else /* !CONFIG_BLK_DEV_IDEDMA */
561 hwif->drives[0].autotune = 1;
562 hwif->drives[1].autotune = 1;
563 #endif /* CONFIG_BLK_DEV_IDEDMA */
564 #endif /* CONFIG_AEC62XX_TUNING */
565 }
566
567 void __init ide_dmacapable_aec62xx (ide_hwif_t *hwif, unsigned long dmabase)
568 {
569 #ifdef CONFIG_AEC62XX_TUNING
570 unsigned long flags;
571 byte reg54h = 0;
572
573 __save_flags(flags); /* local CPU only */
574 __cli(); /* local CPU only */
575
576 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
577 pci_write_config_byte(hwif->pci_dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
578
579 __restore_flags(flags); /* local CPU only */
580 #endif /* CONFIG_AEC62XX_TUNING */
581 ide_setup_dma(hwif, dmabase, 8);
582 }
583