File: /usr/src/linux/drivers/ide/alim15x3.c
1 /*
2 * linux/drivers/ide/alim15x3.c Version 0.10 Jun. 9, 2000
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 *
11 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
12 *
13 **********************************************************************
14 * 9/7/99 --Parts from the above author are included and need to be
15 * converted into standard interface, once I finish the thought.
16 */
17
18 #include <linux/config.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/hdreg.h>
24 #include <linux/ide.h>
25 #include <linux/init.h>
26
27 #include <asm/io.h>
28
29 #include "ide_modes.h"
30
31 #define DISPLAY_ALI_TIMINGS
32
33 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
34 #include <linux/stat.h>
35 #include <linux/proc_fs.h>
36
37 static int ali_get_info(char *buffer, char **addr, off_t offset, int count);
38 extern int (*ali_display_info)(char *, char **, off_t, int); /* ide-proc.c */
39 static struct pci_dev *bmide_dev;
40
41 char *fifo[4] = {
42 "FIFO Off",
43 "FIFO On ",
44 "DMA mode",
45 "PIO mode" };
46
47 char *udmaT[8] = {
48 "1.5T",
49 " 2T",
50 "2.5T",
51 " 3T",
52 "3.5T",
53 " 4T",
54 " 6T",
55 " 8T"
56 };
57
58 char *channel_status[8] = {
59 "OK ",
60 "busy ",
61 "DRQ ",
62 "DRQ busy ",
63 "error ",
64 "error busy ",
65 "error DRQ ",
66 "error DRQ busy"
67 };
68
69 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
70 {
71 byte reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1;
72 unsigned int bibma;
73 byte c0, c1;
74 byte rev, tmp;
75 char *p = buffer;
76 char *q;
77
78 /* fetch rev. */
79 pci_read_config_byte(bmide_dev, 0x08, &rev);
80 if (rev >= 0xc1) /* M1543C or newer */
81 udmaT[7] = " ???";
82 else
83 fifo[3] = " ??? ";
84
85 /* first fetch bibma: */
86 pci_read_config_dword(bmide_dev, 0x20, &bibma);
87 bibma = (bibma & 0xfff0) ;
88 /*
89 * at that point bibma+0x2 et bibma+0xa are byte
90 * registers to investigate:
91 */
92 c0 = inb((unsigned short)bibma + 0x02);
93 c1 = inb((unsigned short)bibma + 0x0a);
94
95 p += sprintf(p,
96 "\n Ali M15x3 Chipset.\n");
97 p += sprintf(p,
98 " ------------------\n");
99 pci_read_config_byte(bmide_dev, 0x78, ®53h);
100 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
101
102 pci_read_config_byte(bmide_dev, 0x53, ®53h);
103 p += sprintf(p,
104 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
105 (reg53h & 0x02) ? "Yes" : "No ",
106 (reg53h & 0x01) ? "Yes" : "No " );
107 pci_read_config_byte(bmide_dev, 0x74, ®53h);
108 p += sprintf(p,
109 "FIFO Status: contains %d Words, runs%s%s\n\n",
110 (reg53h & 0x3f),
111 (reg53h & 0x40) ? " OVERWR" : "",
112 (reg53h & 0x80) ? " OVERRD." : "." );
113
114 p += sprintf(p,
115 "-------------------primary channel-------------------secondary channel---------\n\n");
116
117 pci_read_config_byte(bmide_dev, 0x09, ®53h);
118 p += sprintf(p,
119 "channel status: %s %s\n",
120 (reg53h & 0x20) ? "On " : "Off",
121 (reg53h & 0x10) ? "On " : "Off" );
122
123 p += sprintf(p,
124 "both channels togth: %s %s\n",
125 (c0&0x80) ? "No " : "Yes",
126 (c1&0x80) ? "No " : "Yes" );
127
128 pci_read_config_byte(bmide_dev, 0x76, ®53h);
129 p += sprintf(p,
130 "Channel state: %s %s\n",
131 channel_status[reg53h & 0x07],
132 channel_status[(reg53h & 0x70) >> 4] );
133
134 pci_read_config_byte(bmide_dev, 0x58, ®5xh);
135 pci_read_config_byte(bmide_dev, 0x5c, ®5yh);
136 p += sprintf(p,
137 "Add. Setup Timing: %dT %dT\n",
138 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
139 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
140
141 pci_read_config_byte(bmide_dev, 0x59, ®5xh);
142 pci_read_config_byte(bmide_dev, 0x5d, ®5yh);
143 p += sprintf(p,
144 "Command Act. Count: %dT %dT\n"
145 "Command Rec. Count: %dT %dT\n\n",
146 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
147 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
148 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
149 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
150
151 p += sprintf(p,
152 "----------------drive0-----------drive1------------drive0-----------drive1------\n\n");
153 p += sprintf(p,
154 "DMA enabled: %s %s %s %s\n",
155 (c0&0x20) ? "Yes" : "No ",
156 (c0&0x40) ? "Yes" : "No ",
157 (c1&0x20) ? "Yes" : "No ",
158 (c1&0x40) ? "Yes" : "No " );
159
160 pci_read_config_byte(bmide_dev, 0x54, ®5xh);
161 pci_read_config_byte(bmide_dev, 0x55, ®5yh);
162 q = "FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n";
163 if (rev < 0xc1) {
164 if ((rev == 0x20) && (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
165 p += sprintf(p, q, 8, 8, 8, 8);
166 } else {
167 p += sprintf(p, q,
168 (reg5xh & 0x03) + 12,
169 ((reg5xh & 0x30)>>4) + 12,
170 (reg5yh & 0x03) + 12,
171 ((reg5yh & 0x30)>>4) + 12 );
172 }
173 } else {
174 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
175 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
176 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
177 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
178 p += sprintf(p, q, t1, t2, t3, t4);
179 }
180
181 #if 0
182 p += sprintf(p,
183 "FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n",
184 (reg5xh & 0x03) + 12,
185 ((reg5xh & 0x30)>>4) + 12,
186 (reg5yh & 0x03) + 12,
187 ((reg5yh & 0x30)>>4) + 12 );
188 #endif
189
190 p += sprintf(p,
191 "FIFO mode: %s %s %s %s\n",
192 fifo[((reg5xh & 0x0c) >> 2)],
193 fifo[((reg5xh & 0xc0) >> 6)],
194 fifo[((reg5yh & 0x0c) >> 2)],
195 fifo[((reg5yh & 0xc0) >> 6)] );
196
197 pci_read_config_byte(bmide_dev, 0x5a, ®5xh);
198 pci_read_config_byte(bmide_dev, 0x5b, ®5xh1);
199 pci_read_config_byte(bmide_dev, 0x5e, ®5yh);
200 pci_read_config_byte(bmide_dev, 0x5f, ®5yh1);
201
202 p += sprintf(p,/*
203 "------------------drive0-----------drive1------------drive0-----------drive1------\n")*/
204 "Dt RW act. Cnt %2dT %2dT %2dT %2dT\n"
205 "Dt RW rec. Cnt %2dT %2dT %2dT %2dT\n\n",
206 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
207 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
208 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
209 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
210 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
211 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
212 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
213 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
214
215 p += sprintf(p,
216 "-----------------------------------UDMA Timings--------------------------------\n\n");
217
218 pci_read_config_byte(bmide_dev, 0x56, ®5xh);
219 pci_read_config_byte(bmide_dev, 0x57, ®5yh);
220 p += sprintf(p,
221 "UDMA: %s %s %s %s\n"
222 "UDMA timings: %s %s %s %s\n\n",
223 (reg5xh & 0x08) ? "OK" : "No",
224 (reg5xh & 0x80) ? "OK" : "No",
225 (reg5yh & 0x08) ? "OK" : "No",
226 (reg5yh & 0x80) ? "OK" : "No",
227 udmaT[(reg5xh & 0x07)],
228 udmaT[(reg5xh & 0x70) >> 4],
229 udmaT[reg5yh & 0x07],
230 udmaT[(reg5yh & 0x70) >> 4] );
231
232 return p-buffer; /* => must be less than 4k! */
233 }
234 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
235
236 static byte m5229_revision;
237 static byte chip_is_1543c_e;
238
239 byte ali_proc = 0;
240 static struct pci_dev *isa_dev;
241
242 static void ali15x3_tune_drive (ide_drive_t *drive, byte pio)
243 {
244 ide_pio_data_t d;
245 ide_hwif_t *hwif = HWIF(drive);
246 struct pci_dev *dev = hwif->pci_dev;
247 int s_time, a_time, c_time;
248 byte s_clc, a_clc, r_clc;
249 unsigned long flags;
250 int bus_speed = system_bus_clock();
251 int port = hwif->index ? 0x5c : 0x58;
252 int portFIFO = hwif->channel ? 0x55 : 0x54;
253 byte cd_dma_fifo = 0;
254
255 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
256 s_time = ide_pio_timings[pio].setup_time;
257 a_time = ide_pio_timings[pio].active_time;
258 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
259 s_clc = 0;
260 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
261 a_clc = 0;
262 c_time = ide_pio_timings[pio].cycle_time;
263
264 #if 0
265 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
266 r_clc = 0;
267 #endif
268
269 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
270 r_clc = 1;
271 } else {
272 if (r_clc >= 16)
273 r_clc = 0;
274 }
275 __save_flags(flags);
276 __cli();
277
278 /*
279 * PIO mode => ATA FIFO on, ATAPI FIFO off
280 */
281 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
282 if (drive->media==ide_disk) {
283 if (hwif->index) {
284 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
285 } else {
286 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
287 }
288 } else {
289 if (hwif->index) {
290 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
291 } else {
292 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
293 }
294 }
295
296 pci_write_config_byte(dev, port, s_clc);
297 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
298 __restore_flags(flags);
299
300 /*
301 * setup active rec
302 * { 70, 165, 365 }, PIO Mode 0
303 * { 50, 125, 208 }, PIO Mode 1
304 * { 30, 100, 110 }, PIO Mode 2
305 * { 30, 80, 70 }, PIO Mode 3 with IORDY
306 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
307 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
308 */
309
310 }
311
312 static int ali15x3_tune_chipset (ide_drive_t *drive, byte speed)
313 {
314 ide_hwif_t *hwif = HWIF(drive);
315 struct pci_dev *dev = hwif->pci_dev;
316 byte unit = (drive->select.b.unit & 0x01);
317 byte tmpbyte = 0x00;
318 int m5229_udma = hwif->channel? 0x57 : 0x56;
319 int err = 0;
320
321 if (speed < XFER_UDMA_0) {
322 byte ultra_enable = (unit) ? 0x7f : 0xf7;
323 /*
324 * clear "ultra enable" bit
325 */
326 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
327 tmpbyte &= ultra_enable;
328 pci_write_config_byte(dev, m5229_udma, tmpbyte);
329 }
330
331 err = ide_config_drive_speed(drive, speed);
332
333 #ifdef CONFIG_BLK_DEV_IDEDMA
334 if (speed >= XFER_SW_DMA_0) {
335 unsigned long dma_base = hwif->dma_base;
336
337 outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
338 }
339
340 if (speed >= XFER_UDMA_0) {
341 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
342 tmpbyte &= (0x0f << ((1-unit) << 2));
343 /*
344 * enable ultra dma and set timing
345 */
346 tmpbyte |= ((0x08 | ((4-speed)&0x07)) << (unit << 2));
347 pci_write_config_byte(dev, m5229_udma, tmpbyte);
348 if (speed >= XFER_UDMA_3) {
349 pci_read_config_byte(dev, 0x4b, &tmpbyte);
350 tmpbyte |= 1;
351 pci_write_config_byte(dev, 0x4b, tmpbyte);
352 }
353 }
354 #endif /* CONFIG_BLK_DEV_IDEDMA */
355
356 drive->current_speed = speed;
357
358 return (err);
359 }
360
361 static void config_chipset_for_pio (ide_drive_t *drive)
362 {
363 ali15x3_tune_drive(drive, 5);
364 }
365
366 #ifdef CONFIG_BLK_DEV_IDEDMA
367 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra33)
368 {
369 struct hd_driveid *id = drive->id;
370 byte speed = 0x00;
371 byte ultra66 = eighty_ninty_three(drive);
372 byte ultra100 = (m5229_revision>=0xc4) ? 1 : 0;
373 int rval;
374
375 if ((id->dma_ultra & 0x0020) && (ultra100) && (ultra66) && (ultra33)) {
376 speed = XFER_UDMA_5;
377 } else if ((id->dma_ultra & 0x0010) && (ultra66) && (ultra33)) {
378 speed = XFER_UDMA_4;
379 } else if ((id->dma_ultra & 0x0008) && (ultra66) && (ultra33)) {
380 speed = XFER_UDMA_3;
381 } else if ((id->dma_ultra & 0x0004) && (ultra33)) {
382 speed = XFER_UDMA_2;
383 } else if ((id->dma_ultra & 0x0002) && (ultra33)) {
384 speed = XFER_UDMA_1;
385 } else if ((id->dma_ultra & 0x0001) && (ultra33)) {
386 speed = XFER_UDMA_0;
387 } else if (id->dma_mword & 0x0004) {
388 speed = XFER_MW_DMA_2;
389 } else if (id->dma_mword & 0x0002) {
390 speed = XFER_MW_DMA_1;
391 } else if (id->dma_mword & 0x0001) {
392 speed = XFER_MW_DMA_0;
393 } else if (id->dma_1word & 0x0004) {
394 speed = XFER_SW_DMA_2;
395 } else if (id->dma_1word & 0x0002) {
396 speed = XFER_SW_DMA_1;
397 } else if (id->dma_1word & 0x0001) {
398 speed = XFER_SW_DMA_0;
399 } else {
400 return ((int) ide_dma_off_quietly);
401 }
402
403 (void) ali15x3_tune_chipset(drive, speed);
404
405 if (!drive->init_speed)
406 drive->init_speed = speed;
407
408 rval = (int)( ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
409 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
410 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
411 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
412 ide_dma_off_quietly);
413
414 return rval;
415 }
416
417 static byte ali15x3_can_ultra (ide_drive_t *drive)
418 {
419 #ifndef CONFIG_WDC_ALI15X3
420 struct hd_driveid *id = drive->id;
421 #endif /* CONFIG_WDC_ALI15X3 */
422
423 if (m5229_revision <= 0x20) {
424 return 0;
425 } else if ((m5229_revision < 0xC2) &&
426 #ifndef CONFIG_WDC_ALI15X3
427 ((chip_is_1543c_e && strstr(id->model, "WDC ")) ||
428 (drive->media!=ide_disk))) {
429 #else /* CONFIG_WDC_ALI15X3 */
430 (drive->media!=ide_disk)) {
431 #endif /* CONFIG_WDC_ALI15X3 */
432 return 0;
433 } else {
434 return 1;
435 }
436 }
437
438 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
439 {
440 struct hd_driveid *id = drive->id;
441 ide_hwif_t *hwif = HWIF(drive);
442 ide_dma_action_t dma_func = ide_dma_on;
443 byte can_ultra_dma = ali15x3_can_ultra(drive);
444
445 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
446 return hwif->dmaproc(ide_dma_off_quietly, drive);
447
448 if ((id != NULL) && ((id->capability & 1) != 0) && hwif->autodma) {
449 /* Consult the list of known "bad" drives */
450 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
451 dma_func = ide_dma_off;
452 goto fast_ata_pio;
453 }
454 dma_func = ide_dma_off_quietly;
455 if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
456 if (id->dma_ultra & 0x002F) {
457 /* Force if Capable UltraDMA */
458 dma_func = config_chipset_for_dma(drive, can_ultra_dma);
459 if ((id->field_valid & 2) &&
460 (dma_func != ide_dma_on))
461 goto try_dma_modes;
462 }
463 } else if (id->field_valid & 2) {
464 try_dma_modes:
465 if ((id->dma_mword & 0x0007) ||
466 (id->dma_1word & 0x0007)) {
467 /* Force if Capable regular DMA modes */
468 dma_func = config_chipset_for_dma(drive, can_ultra_dma);
469 if (dma_func != ide_dma_on)
470 goto no_dma_set;
471 }
472 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
473 if (id->eide_dma_time > 150) {
474 goto no_dma_set;
475 }
476 /* Consult the list of known "good" drives */
477 dma_func = config_chipset_for_dma(drive, can_ultra_dma);
478 if (dma_func != ide_dma_on)
479 goto no_dma_set;
480 } else {
481 goto fast_ata_pio;
482 }
483 } else if ((id->capability & 8) || (id->field_valid & 2)) {
484 fast_ata_pio:
485 dma_func = ide_dma_off_quietly;
486 no_dma_set:
487 config_chipset_for_pio(drive);
488 }
489 return hwif->dmaproc(dma_func, drive);
490 }
491
492 static int ali15x3_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
493 {
494 switch(func) {
495 case ide_dma_check:
496 return ali15x3_config_drive_for_dma(drive);
497 case ide_dma_write:
498 if ((m5229_revision < 0xC2) && (drive->media != ide_disk))
499 return 1; /* try PIO instead of DMA */
500 break;
501 default:
502 break;
503 }
504 return ide_dmaproc(func, drive); /* use standard DMA stuff */
505 }
506 #endif /* CONFIG_BLK_DEV_IDEDMA */
507
508 unsigned int __init pci_init_ali15x3 (struct pci_dev *dev, const char *name)
509 {
510 unsigned long fixdma_base = pci_resource_start(dev, 4);
511
512 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
513
514 isa_dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
515
516 if (!fixdma_base) {
517 /*
518 *
519 */
520 } else {
521 /*
522 * enable DMA capable bit, and "not" simplex only
523 */
524 outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
525
526 if (inb(fixdma_base+2) & 0x80)
527 printk("%s: simplex device: DMA will fail!!\n", name);
528 }
529
530 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
531 if (!ali_proc) {
532 ali_proc = 1;
533 bmide_dev = dev;
534 ali_display_info = &ali_get_info;
535 }
536 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
537
538 return 0;
539 }
540
541 /*
542 * This checks if the controller and the cable are capable
543 * of UDMA66 transfers. It doesn't check the drives.
544 * But see note 2 below!
545 */
546 unsigned int __init ata66_ali15x3 (ide_hwif_t *hwif)
547 {
548 struct pci_dev *dev = hwif->pci_dev;
549 unsigned int ata66 = 0;
550 byte cable_80_pin[2] = { 0, 0 };
551
552 unsigned long flags;
553 byte tmpbyte;
554
555 __save_flags(flags);
556 __cli();
557
558 if (m5229_revision >= 0xC2) {
559 /*
560 * 1543C-B?, 1535, 1535D, 1553
561 * Note 1: not all "motherboard" support this detection
562 * Note 2: if no udma 66 device, the detection may "error".
563 * but in this case, we will not set the device to
564 * ultra 66, the detection result is not important
565 */
566
567 /*
568 * enable "Cable Detection", m5229, 0x4b, bit3
569 */
570 pci_read_config_byte(dev, 0x4b, &tmpbyte);
571 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
572
573 /*
574 * set south-bridge's enable bit, m1533, 0x79
575 */
576 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
577 if (m5229_revision == 0xC2) {
578 /*
579 * 1543C-B0 (m1533, 0x79, bit 2)
580 */
581 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
582 } else if (m5229_revision >= 0xC3) {
583 /*
584 * 1553/1535 (m1533, 0x79, bit 1)
585 */
586 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
587 }
588 /*
589 * Ultra66 cable detection (from Host View)
590 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
591 */
592 pci_read_config_byte(dev, 0x4a, &tmpbyte);
593 /*
594 * 0x4a, bit0 is 0 => primary channel
595 * has 80-pin (from host view)
596 */
597 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1;
598 /*
599 * 0x4a, bit1 is 0 => secondary channel
600 * has 80-pin (from host view)
601 */
602 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1;
603 /*
604 * Allow ata66 if cable of current channel has 80 pins
605 */
606 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0];
607 } else {
608 /*
609 * revision 0x20 (1543-E, 1543-F)
610 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
611 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
612 */
613 pci_read_config_byte(dev, 0x4b, &tmpbyte);
614 /*
615 * clear bit 7
616 */
617 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
618 /*
619 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
620 */
621 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
622 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
623 }
624
625 /*
626 * CD_ROM DMA on (m5229, 0x53, bit0)
627 * Enable this bit even if we want to use PIO
628 * PIO FIFO off (m5229, 0x53, bit1)
629 * The hardware will use 0x54h and 0x55h to control PIO FIFO
630 */
631 pci_read_config_byte(dev, 0x53, &tmpbyte);
632 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
633
634 pci_write_config_byte(dev, 0x53, tmpbyte);
635
636 __restore_flags(flags);
637
638 return(ata66);
639 }
640
641 void __init ide_init_ali15x3 (ide_hwif_t *hwif)
642 {
643 #ifndef CONFIG_SPARC64
644 byte ideic, inmir;
645 byte irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
646 1, 11, 0, 12, 0, 14, 0, 15 };
647
648 hwif->irq = hwif->channel ? 15 : 14;
649
650 if (isa_dev) {
651 /*
652 * read IDE interface control
653 */
654 pci_read_config_byte(isa_dev, 0x58, &ideic);
655
656 /* bit0, bit1 */
657 ideic = ideic & 0x03;
658
659 /* get IRQ for IDE Controller */
660 if ((hwif->channel && ideic == 0x03) || (!hwif->channel && !ideic)) {
661 /*
662 * get SIRQ1 routing table
663 */
664 pci_read_config_byte(isa_dev, 0x44, &inmir);
665 inmir = inmir & 0x0f;
666 hwif->irq = irq_routing_table[inmir];
667 } else if (hwif->channel && !(ideic & 0x01)) {
668 /*
669 * get SIRQ2 routing table
670 */
671 pci_read_config_byte(isa_dev, 0x75, &inmir);
672 inmir = inmir & 0x0f;
673 hwif->irq = irq_routing_table[inmir];
674 }
675 }
676 #endif /* CONFIG_SPARC64 */
677
678 hwif->tuneproc = &ali15x3_tune_drive;
679 hwif->drives[0].autotune = 1;
680 hwif->drives[1].autotune = 1;
681 hwif->speedproc = &ali15x3_tune_chipset;
682
683 #ifdef CONFIG_BLK_DEV_IDEDMA
684 if ((hwif->dma_base) && (m5229_revision >= 0x20)) {
685 /*
686 * M1543C or newer for DMAing
687 */
688 hwif->dmaproc = &ali15x3_dmaproc;
689 hwif->autodma = 1;
690 }
691
692 if (noautodma)
693 hwif->autodma = 0;
694 #else
695 hwif->autodma = 0;
696 #endif /* CONFIG_BLK_DEV_IDEDMA */
697 }
698
699 void __init ide_dmacapable_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
700 {
701 if ((dmabase) && (m5229_revision < 0x20)) {
702 return;
703 }
704 ide_setup_dma(hwif, dmabase, 8);
705 }
706