File: /usr/src/linux/drivers/ide/cmd64x.c
1 /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2 *
3 * linux/drivers/ide/cmd64x.c Version 1.22 June 9, 2000
4 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
10 *
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
13 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
14 */
15
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/hdreg.h>
21 #include <linux/ide.h>
22 #include <linux/init.h>
23
24 #include <asm/io.h>
25
26 #include "ide_modes.h"
27
28 #ifndef SPLIT_BYTE
29 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
30 #endif
31
32 #define CMD_DEBUG 0
33
34 #if CMD_DEBUG
35 #define cmdprintk(x...) printk(##x)
36 #else
37 #define cmdprintk(x...)
38 #endif
39
40 /*
41 * CMD64x specific registers definition.
42 */
43
44 #define CFR 0x50
45 #define CFR_INTR_CH0 0x02
46 #define CNTRL 0x51
47 #define CNTRL_DIS_RA0 0x40
48 #define CNTRL_DIS_RA1 0x80
49 #define CNTRL_ENA_2ND 0x08
50
51 #define CMDTIM 0x52
52 #define ARTTIM0 0x53
53 #define DRWTIM0 0x54
54 #define ARTTIM1 0x55
55 #define DRWTIM1 0x56
56 #define ARTTIM23 0x57
57 #define ARTTIM23_DIS_RA2 0x04
58 #define ARTTIM23_DIS_RA3 0x08
59 #define ARTTIM23_INTR_CH1 0x10
60 #define ARTTIM2 0x57
61 #define ARTTIM3 0x57
62 #define DRWTIM23 0x58
63 #define DRWTIM2 0x58
64 #define BRST 0x59
65 #define DRWTIM3 0x5b
66
67 #define BMIDECR0 0x70
68 #define MRDMODE 0x71
69 #define MRDMODE_INTR_CH0 0x04
70 #define MRDMODE_INTR_CH1 0x08
71 #define MRDMODE_BLK_CH0 0x10
72 #define MRDMODE_BLK_CH1 0x20
73 #define BMIDESR0 0x72
74 #define UDIDETCR0 0x73
75 #define DTPR0 0x74
76 #define BMIDECR1 0x78
77 #define BMIDECSR 0x79
78 #define BMIDESR1 0x7A
79 #define UDIDETCR1 0x7B
80 #define DTPR1 0x7C
81
82 #define DISPLAY_CMD64X_TIMINGS
83
84 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
85 #include <linux/stat.h>
86 #include <linux/proc_fs.h>
87
88 static int cmd64x_get_info(char *, char **, off_t, int);
89 extern int (*cmd64x_display_info)(char *, char **, off_t, int); /* ide-proc.c */
90 extern char *ide_media_verbose(ide_drive_t *);
91 static struct pci_dev *bmide_dev;
92
93 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
94 {
95 char *p = buffer;
96 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
97 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
98 u8 reg72 = 0, reg73 = 0; /* primary */
99 u8 reg7a = 0, reg7b = 0; /* secondary */
100 u8 reg50 = 0, reg71 = 0; /* extra */
101 u8 hi_byte = 0, lo_byte = 0;
102
103 switch(bmide_dev->device) {
104 case PCI_DEVICE_ID_CMD_649:
105 p += sprintf(p, "\n CMD649 Chipset.\n");
106 break;
107 case PCI_DEVICE_ID_CMD_648:
108 p += sprintf(p, "\n CMD648 Chipset.\n");
109 break;
110 case PCI_DEVICE_ID_CMD_646:
111 p += sprintf(p, "\n CMD646 Chipset.\n");
112 break;
113 case PCI_DEVICE_ID_CMD_643:
114 p += sprintf(p, "\n CMD643 Chipset.\n");
115 break;
116 default:
117 p += sprintf(p, "\n CMD64? Chipse.\n");
118 break;
119 }
120 (void) pci_read_config_byte(bmide_dev, CFR, ®50);
121 (void) pci_read_config_byte(bmide_dev, ARTTIM0, ®53);
122 (void) pci_read_config_byte(bmide_dev, DRWTIM0, ®54);
123 (void) pci_read_config_byte(bmide_dev, ARTTIM1, ®55);
124 (void) pci_read_config_byte(bmide_dev, DRWTIM1, ®56);
125 (void) pci_read_config_byte(bmide_dev, ARTTIM2, ®57);
126 (void) pci_read_config_byte(bmide_dev, DRWTIM2, ®58);
127 (void) pci_read_config_byte(bmide_dev, DRWTIM3, ®5b);
128 (void) pci_read_config_byte(bmide_dev, MRDMODE, ®71);
129 (void) pci_read_config_byte(bmide_dev, BMIDESR0, ®72);
130 (void) pci_read_config_byte(bmide_dev, UDIDETCR0, ®73);
131 (void) pci_read_config_byte(bmide_dev, BMIDESR1, ®7a);
132 (void) pci_read_config_byte(bmide_dev, UDIDETCR1, ®7b);
133
134 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
135 p += sprintf(p, " %sabled %sabled\n",
136 (reg72&0x80)?"dis":" en",(reg7a&0x80)?"dis":" en");
137 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
138 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
139 (reg72&0x20)?"yes":"no ",(reg72&0x40)?"yes":"no ",(reg7a&0x20)?"yes":"no ",(reg7a&0x40)?"yes":"no ");
140 p += sprintf(p, "DMA Mode: %s(%s) %s(%s) %s(%s) %s(%s)\n",
141 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
142 (reg72&0x20)?( ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
143 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
144 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
145 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):"X"):"?",
146 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
147 (reg72&0x40)?( ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
148 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
149 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
150 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):"X"):"?",
151 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
152 (reg7a&0x20)?( ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
153 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
154 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
155 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):"X"):"?",
156 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
157 (reg7a&0x40)?( ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
158 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
159 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
160 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):"X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s %s %s\n",
162 "?", "?", "?", "?");
163 p += sprintf(p, " %s %s\n",
164 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
165 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
166 p += sprintf(p, " %s %s\n",
167 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
168 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
169 p += sprintf(p, " %s %s\n",
170 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
171 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
172
173 SPLIT_BYTE(reg50, hi_byte, lo_byte);
174 p += sprintf(p, "CFR = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg50, hi_byte, lo_byte);
175 SPLIT_BYTE(reg57, hi_byte, lo_byte);
176 p += sprintf(p, "ARTTIM23 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg57, hi_byte, lo_byte);
177 SPLIT_BYTE(reg71, hi_byte, lo_byte);
178 p += sprintf(p, "MRDMODE = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg71, hi_byte, lo_byte);
179
180 return p-buffer; /* => must be less than 4k! */
181 }
182
183 #if 0
184 static char * cmd64x_chipset_data (char *buf, struct pci_dev *dev)
185 {
186 char *p = buf;
187 p += sprintf(p, "thingy stuff\n");
188 return (char *)p;
189 }
190 static int __init cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
191 {
192 char *p = buffer;
193 p = cmd64x_chipset_data(buffer, bmide_dev);
194 return p-buffer; /* hoping it is less than 4K... */
195 }
196 #endif
197
198 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
199
200 byte cmd64x_proc = 0;
201
202 /*
203 * Registers and masks for easy access by drive index:
204 */
205 #if 0
206 static byte prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
207 static byte prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
208 #endif
209
210 /*
211 * This routine writes the prepared setup/active/recovery counts
212 * for a drive into the cmd646 chipset registers to active them.
213 */
214 static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
215 {
216 unsigned long flags;
217 ide_drive_t *drives = HWIF(drive)->drives;
218 byte temp_b;
219 static const byte setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
220 static const byte recovery_counts[] =
221 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
222 static const byte arttim_regs[2][2] = {
223 { ARTTIM0, ARTTIM1 },
224 { ARTTIM23, ARTTIM23 }
225 };
226 static const byte drwtim_regs[2][2] = {
227 { DRWTIM0, DRWTIM1 },
228 { DRWTIM2, DRWTIM3 }
229 };
230 int channel = (int) HWIF(drive)->channel;
231 int slave = (drives != drive); /* Is this really the best way to determine this?? */
232
233 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n", setup_count,
234 active_count, recovery_count, drive->present);
235 /*
236 * Set up address setup count registers.
237 * Primary interface has individual count/timing registers for
238 * each drive. Secondary interface has one common set of registers,
239 * for address setup so we merge these timings, using the slowest
240 * value.
241 */
242 if (channel) {
243 drive->drive_data = setup_count;
244 setup_count = IDE_MAX(drives[0].drive_data, drives[1].drive_data);
245 cmdprintk("Secondary interface, setup_count = %d\n", setup_count);
246 }
247
248 /*
249 * Convert values to internal chipset representation
250 */
251 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
252 active_count &= 0xf; /* Remember, max value is 16 */
253 recovery_count = (int) recovery_counts[recovery_count];
254
255 cmdprintk("Final values = %d,%d,%d\n", setup_count, active_count, recovery_count);
256
257 /*
258 * Now that everything is ready, program the new timings
259 */
260 __save_flags (flags);
261 __cli();
262 /*
263 * Program the address_setup clocks into ARTTIM reg,
264 * and then the active/recovery counts into the DRWTIM reg
265 */
266 (void) pci_read_config_byte(HWIF(drive)->pci_dev, arttim_regs[channel][slave], &temp_b);
267 (void) pci_write_config_byte(HWIF(drive)->pci_dev, arttim_regs[channel][slave],
268 ((byte) setup_count) | (temp_b & 0x3f));
269 (void) pci_write_config_byte(HWIF(drive)->pci_dev, drwtim_regs[channel][slave],
270 (byte) ((active_count << 4) | recovery_count));
271 cmdprintk ("Write %x to %x\n", ((byte) setup_count) | (temp_b & 0x3f), arttim_regs[channel][slave]);
272 cmdprintk ("Write %x to %x\n", (byte) ((active_count << 4) | recovery_count), drwtim_regs[channel][slave]);
273 __restore_flags(flags);
274 }
275
276 /*
277 * Attempts to set the interface PIO mode.
278 * The preferred method of selecting PIO modes (e.g. mode 4) is
279 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
280 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
281 * Called with 255 at boot time.
282 */
283 static void cmd64x_tuneproc (ide_drive_t *drive, byte mode_wanted)
284 {
285 int setup_time, active_time, recovery_time, clock_time, pio_mode, cycle_time;
286 byte recovery_count2, cycle_count;
287 int setup_count, active_count, recovery_count;
288 int bus_speed = system_bus_clock();
289 /*byte b;*/
290 ide_pio_data_t d;
291
292 switch (mode_wanted) {
293 case 8: /* set prefetch off */
294 case 9: /* set prefetch on */
295 mode_wanted &= 1;
296 /*set_prefetch_mode(index, mode_wanted);*/
297 cmdprintk("%s: %sabled cmd640 prefetch\n", drive->name, mode_wanted ? "en" : "dis");
298 return;
299 }
300
301 mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
302 pio_mode = d.pio_mode;
303 cycle_time = d.cycle_time;
304
305 /*
306 * I copied all this complicated stuff from cmd640.c and made a few minor changes.
307 * For now I am just going to pray that it is correct.
308 */
309 if (pio_mode > 5)
310 pio_mode = 5;
311 setup_time = ide_pio_timings[pio_mode].setup_time;
312 active_time = ide_pio_timings[pio_mode].active_time;
313 recovery_time = cycle_time - (setup_time + active_time);
314 clock_time = 1000 / bus_speed;
315 cycle_count = (cycle_time + clock_time - 1) / clock_time;
316
317 setup_count = (setup_time + clock_time - 1) / clock_time;
318
319 active_count = (active_time + clock_time - 1) / clock_time;
320
321 recovery_count = (recovery_time + clock_time - 1) / clock_time;
322 recovery_count2 = cycle_count - (setup_count + active_count);
323 if (recovery_count2 > recovery_count)
324 recovery_count = recovery_count2;
325 if (recovery_count > 16) {
326 active_count += recovery_count - 16;
327 recovery_count = 16;
328 }
329 if (active_count > 16)
330 active_count = 16; /* maximum allowed by cmd646 */
331
332 /*
333 * In a perfect world, we might set the drive pio mode here
334 * (using WIN_SETFEATURE) before continuing.
335 *
336 * But we do not, because:
337 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
338 * 2) in practice this is rarely, if ever, necessary
339 */
340 program_drive_counts (drive, setup_count, active_count, recovery_count);
341
342 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, clocks=%d/%d/%d\n",
343 drive->name, pio_mode, mode_wanted, cycle_time,
344 d.overridden ? " (overriding vendor mode)" : "",
345 setup_count, active_count, recovery_count);
346 }
347
348 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
349 {
350 byte speed= 0x00;
351 byte set_pio= ide_get_best_pio_mode(drive, 4, 5, NULL);
352
353 cmd64x_tuneproc(drive, set_pio);
354 speed = XFER_PIO_0 + set_pio;
355 if (set_speed)
356 (void) ide_config_drive_speed(drive, speed);
357 }
358
359 static int cmd64x_tune_chipset (ide_drive_t *drive, byte speed)
360 {
361 #ifdef CONFIG_BLK_DEV_IDEDMA
362 ide_hwif_t *hwif = HWIF(drive);
363 struct pci_dev *dev = hwif->pci_dev;
364 int err = 0;
365
366 byte unit = (drive->select.b.unit & 0x01);
367 u8 pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
368 u8 pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
369 u8 regU = 0;
370 u8 regD = 0;
371
372 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0)) return 1;
373
374 (void) pci_read_config_byte(dev, pciD, ®D);
375 (void) pci_read_config_byte(dev, pciU, ®U);
376 regD &= ~(unit ? 0x40 : 0x20);
377 regU &= ~(unit ? 0xCA : 0x35);
378 (void) pci_write_config_byte(dev, pciD, regD);
379 (void) pci_write_config_byte(dev, pciU, regU);
380
381 (void) pci_read_config_byte(dev, pciD, ®D);
382 (void) pci_read_config_byte(dev, pciU, ®U);
383 switch(speed) {
384 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
385 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
386 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
387 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
388 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
389 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
390 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
391 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
392 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
393 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
394 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
395 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
396 #else
397 int err = 0;
398
399 switch(speed) {
400 #endif /* CONFIG_BLK_DEV_IDEDMA */
401 case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break;
402 case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break;
403 case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break;
404 case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break;
405 case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break;
406
407 default:
408 return 1;
409 }
410
411 #ifdef CONFIG_BLK_DEV_IDEDMA
412 (void) pci_write_config_byte(dev, pciU, regU);
413 #endif /* CONFIG_BLK_DEV_IDEDMA */
414
415 err = ide_config_drive_speed(drive, speed);
416
417 drive->current_speed = speed;
418
419 #ifdef CONFIG_BLK_DEV_IDEDMA
420 regD |= (unit ? 0x40 : 0x20);
421 (void) pci_write_config_byte(dev, pciD, regD);
422 #endif /* CONFIG_BLK_DEV_IDEDMA */
423
424 return err;
425 }
426
427 #ifdef CONFIG_BLK_DEV_IDEDMA
428 static int config_chipset_for_dma (ide_drive_t *drive, unsigned int rev, byte ultra_66)
429 {
430 struct hd_driveid *id = drive->id;
431 ide_hwif_t *hwif = HWIF(drive);
432 struct pci_dev *dev = hwif->pci_dev;
433
434 byte speed = 0x00;
435 byte set_pio = 0x00;
436 byte udma_33 = ((rev >= 0x05) || (ultra_66)) ? 1 : 0;
437 byte udma_66 = eighty_ninty_three(drive);
438 byte udma_100 = 0;
439 int rval;
440
441 switch(dev->device) {
442 case PCI_DEVICE_ID_CMD_649: udma_100 = 1; break;
443 case PCI_DEVICE_ID_CMD_648:
444 case PCI_DEVICE_ID_CMD_646:
445 case PCI_DEVICE_ID_CMD_643:
446 default:
447 break;
448 }
449
450 if (drive->media != ide_disk) {
451 cmdprintk("CMD64X: drive->media != ide_disk at double check, inital check failed!!\n");
452 return ((int) ide_dma_off);
453 }
454
455 /* UltraDMA only supported on PCI646U and PCI646U2,
456 * which correspond to revisions 0x03, 0x05 and 0x07 respectively.
457 * Actually, although the CMD tech support people won't
458 * tell me the details, the 0x03 revision cannot support
459 * UDMA correctly without hardware modifications, and even
460 * then it only works with Quantum disks due to some
461 * hold time assumptions in the 646U part which are fixed
462 * in the 646U2.
463 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
464 */
465 if ((id->dma_ultra & 0x0020) && (udma_100) && (udma_66) && (udma_33)) {
466 speed = XFER_UDMA_5;
467 } else if ((id->dma_ultra & 0x0010) && (udma_66) && (udma_33)) {
468 speed = XFER_UDMA_4;
469 } else if ((id->dma_ultra & 0x0008) && (udma_66) && (udma_33)) {
470 speed = XFER_UDMA_3;
471 } else if ((id->dma_ultra & 0x0004) && (udma_33)) {
472 speed = XFER_UDMA_2;
473 } else if ((id->dma_ultra & 0x0002) && (udma_33)) {
474 speed = XFER_UDMA_1;
475 } else if ((id->dma_ultra & 0x0001) && (udma_33)) {
476 speed = XFER_UDMA_0;
477 } else if (id->dma_mword & 0x0004) {
478 speed = XFER_MW_DMA_2;
479 } else if (id->dma_mword & 0x0002) {
480 speed = XFER_MW_DMA_1;
481 } else if (id->dma_mword & 0x0001) {
482 speed = XFER_MW_DMA_0;
483 } else if (id->dma_1word & 0x0004) {
484 speed = XFER_SW_DMA_2;
485 } else if (id->dma_1word & 0x0002) {
486 speed = XFER_SW_DMA_1;
487 } else if (id->dma_1word & 0x0001) {
488 speed = XFER_SW_DMA_0;
489 } else {
490 set_pio = 1;
491 }
492
493 if (!drive->init_speed)
494 drive->init_speed = speed;
495
496 config_chipset_for_pio(drive, set_pio);
497
498 if (set_pio)
499 return ((int) ide_dma_off_quietly);
500
501 if (cmd64x_tune_chipset(drive, speed))
502 return ((int) ide_dma_off);
503
504 rval = (int)( ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
505 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
506 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
507 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
508 ide_dma_off_quietly);
509
510 return rval;
511 }
512
513 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
514 {
515 struct hd_driveid *id = drive->id;
516 ide_hwif_t *hwif = HWIF(drive);
517 struct pci_dev *dev = hwif->pci_dev;
518 unsigned int class_rev = 0;
519 byte can_ultra_33 = 0;
520 byte can_ultra_66 = 0;
521 byte can_ultra_100 = 0;
522 ide_dma_action_t dma_func = ide_dma_on;
523
524 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
525 class_rev &= 0xff;
526
527 switch(dev->device) {
528 case PCI_DEVICE_ID_CMD_649:
529 can_ultra_100 = 1;
530 case PCI_DEVICE_ID_CMD_648:
531 can_ultra_66 = 1;
532 case PCI_DEVICE_ID_CMD_643:
533 can_ultra_33 = 1;
534 break;
535 case PCI_DEVICE_ID_CMD_646:
536 can_ultra_33 = (class_rev >= 0x05) ? 1 : 0;
537 can_ultra_66 = 0;
538 can_ultra_100 = 0;
539 break;
540 default:
541 return hwif->dmaproc(ide_dma_off, drive);
542 }
543
544 if ((id != NULL) && ((id->capability & 1) != 0) &&
545 hwif->autodma && (drive->media == ide_disk)) {
546 /* Consult the list of known "bad" drives */
547 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
548 dma_func = ide_dma_off;
549 goto fast_ata_pio;
550 }
551 dma_func = ide_dma_off_quietly;
552 if ((id->field_valid & 4) && (can_ultra_33)) {
553 if (id->dma_ultra & 0x002F) {
554 /* Force if Capable UltraDMA */
555 dma_func = config_chipset_for_dma(drive, class_rev, can_ultra_66);
556 if ((id->field_valid & 2) &&
557 (dma_func != ide_dma_on))
558 goto try_dma_modes;
559 }
560 } else if (id->field_valid & 2) {
561 try_dma_modes:
562 if ((id->dma_mword & 0x0007) ||
563 (id->dma_1word & 0x0007)) {
564 /* Force if Capable regular DMA modes */
565 dma_func = config_chipset_for_dma(drive, class_rev, 0);
566 if (dma_func != ide_dma_on)
567 goto no_dma_set;
568 }
569 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
570 if (id->eide_dma_time > 150) {
571 goto no_dma_set;
572 }
573 /* Consult the list of known "good" drives */
574 dma_func = config_chipset_for_dma(drive, class_rev, 0);
575 if (dma_func != ide_dma_on)
576 goto no_dma_set;
577 } else {
578 goto fast_ata_pio;
579 }
580 } else if ((id->capability & 8) || (id->field_valid & 2)) {
581 fast_ata_pio:
582 dma_func = ide_dma_off_quietly;
583 no_dma_set:
584 config_chipset_for_pio(drive, 1);
585 }
586 return HWIF(drive)->dmaproc(dma_func, drive);
587 }
588
589 static int cmd64x_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
590 {
591 byte dma_stat = 0;
592 byte dma_alt_stat = 0;
593 byte mask = (HWIF(drive)->channel) ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
594 unsigned long dma_base = HWIF(drive)->dma_base;
595 struct pci_dev *dev = HWIF(drive)->pci_dev;
596 byte jack_slap = ((dev->device == PCI_DEVICE_ID_CMD_648) || (dev->device == PCI_DEVICE_ID_CMD_649)) ? 1 : 0;
597
598 switch (func) {
599 case ide_dma_check:
600 return cmd64x_config_drive_for_dma(drive);
601 case ide_dma_end: /* returns 1 on error, 0 otherwise */
602 drive->waiting_for_dma = 0;
603 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
604 dma_stat = inb(dma_base+2); /* get DMA status */
605 outb(dma_stat|6, dma_base+2); /* clear the INTR & ERROR bits */
606 if (jack_slap) {
607 byte dma_intr = 0;
608 byte dma_mask = (HWIF(drive)->channel) ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
609 byte dma_reg = (HWIF(drive)->channel) ? ARTTIM2 : CFR;
610 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
611 /*
612 * DAMN BMIDE is not connected to PCI space!
613 * Have to manually jack-slap that bitch!
614 * To allow the PCI side to read incoming interrupts.
615 */
616 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask); /* clear the INTR bit */
617 }
618 ide_destroy_dmatable(drive); /* purge DMA mappings */
619 return (dma_stat & 7) != 4; /* verify good DMA status */
620 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */
621 dma_stat = inb(dma_base+2);
622 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
623 #ifdef DEBUG
624 printk("%s: dma_stat: 0x%02x dma_alt_stat: 0x%02x mask: 0x%02x\n", drive->name, dma_stat, dma_alt_stat, mask);
625 #endif
626 if (!(dma_alt_stat & mask)) {
627 return 0;
628 }
629 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
630 default:
631 break;
632 }
633 /* Other cases are done by generic IDE-DMA code. */
634 return ide_dmaproc(func, drive);
635 }
636
637 /*
638 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
639 * event order for DMA transfers.
640 */
641 static int cmd646_1_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
642 {
643 ide_hwif_t *hwif = HWIF(drive);
644 unsigned long dma_base = hwif->dma_base;
645 byte dma_stat;
646
647 switch (func) {
648 case ide_dma_check:
649 return cmd64x_config_drive_for_dma(drive);
650 case ide_dma_end:
651 drive->waiting_for_dma = 0;
652 dma_stat = inb(dma_base+2); /* get DMA status */
653 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
654 outb(dma_stat|6, dma_base+2); /* clear the INTR & ERROR bits */
655 ide_destroy_dmatable(drive); /* and free any DMA resources */
656 return (dma_stat & 7) != 4; /* verify good DMA status */
657 default:
658 break;
659 }
660
661 /* Other cases are done by generic IDE-DMA code. */
662 return ide_dmaproc(func, drive);
663 }
664 #endif /* CONFIG_BLK_DEV_IDEDMA */
665
666 unsigned int __init pci_init_cmd64x (struct pci_dev *dev, const char *name)
667 {
668 unsigned char mrdmode;
669 unsigned int class_rev;
670
671 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
672 class_rev &= 0xff;
673
674 #ifdef __i386__
675 if (dev->resource[PCI_ROM_RESOURCE].start) {
676 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
677 printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
678 }
679 #endif
680
681 switch(dev->device) {
682 case PCI_DEVICE_ID_CMD_643:
683 break;
684 case PCI_DEVICE_ID_CMD_646:
685 printk("%s: chipset revision 0x%02X, ", name, class_rev);
686 switch(class_rev) {
687 case 0x07:
688 case 0x05:
689 printk("UltraDMA Capable");
690 break;
691 case 0x03:
692 printk("MultiWord DMA Force Limited");
693 break;
694 case 0x01:
695 default:
696 printk("MultiWord DMA Limited, IRQ workaround enabled");
697 break;
698 }
699 printk("\n");
700 break;
701 case PCI_DEVICE_ID_CMD_648:
702 case PCI_DEVICE_ID_CMD_649:
703 break;
704 default:
705 break;
706 }
707
708 /* Set a good latency timer and cache line size value. */
709 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
710 #ifdef __sparc_v9__
711 (void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10);
712 #endif
713
714
715 /* Setup interrupts. */
716 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
717 mrdmode &= ~(0x30);
718 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
719
720 /* Use MEMORY READ LINE for reads.
721 * NOTE: Although not mentioned in the PCI0646U specs,
722 * these bits are write only and won't be read
723 * back as set or not. The PCI0646U2 specs clarify
724 * this point.
725 */
726 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
727
728 /* Set reasonable active/recovery/address-setup values. */
729 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
730 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
731 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
732 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
733 #ifdef __i386__
734 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
735 #else
736 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
737 #endif
738 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
739 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
740 #ifdef CONFIG_PPC
741 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
742 #endif /* CONFIG_PPC */
743
744 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
745 if (!cmd64x_proc) {
746 cmd64x_proc = 1;
747 bmide_dev = dev;
748 cmd64x_display_info = &cmd64x_get_info;
749 }
750 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
751
752 return 0;
753 }
754
755 unsigned int __init ata66_cmd64x (ide_hwif_t *hwif)
756 {
757 byte ata66 = 0;
758 byte mask = (hwif->channel) ? 0x02 : 0x01;
759
760 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
761 return (ata66 & mask) ? 1 : 0;
762 }
763
764 void __init ide_init_cmd64x (ide_hwif_t *hwif)
765 {
766 struct pci_dev *dev = hwif->pci_dev;
767 unsigned int class_rev;
768
769 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
770 class_rev &= 0xff;
771
772 hwif->tuneproc = &cmd64x_tuneproc;
773 hwif->speedproc = &cmd64x_tune_chipset;
774 hwif->drives[0].autotune = 1;
775 hwif->drives[1].autotune = 1;
776
777 if (!hwif->dma_base)
778 return;
779
780 #ifdef CONFIG_BLK_DEV_IDEDMA
781 switch(dev->device) {
782 case PCI_DEVICE_ID_CMD_649:
783 case PCI_DEVICE_ID_CMD_648:
784 case PCI_DEVICE_ID_CMD_643:
785 hwif->dmaproc = &cmd64x_dmaproc;
786 break;
787 case PCI_DEVICE_ID_CMD_646:
788 hwif->chipset = ide_cmd646;
789 if (class_rev == 0x01) {
790 hwif->dmaproc = &cmd646_1_dmaproc;
791 } else {
792 hwif->dmaproc = &cmd64x_dmaproc;
793 }
794 break;
795 default:
796 break;
797 }
798 #endif /* CONFIG_BLK_DEV_IDEDMA */
799 }
800