File: /usr/src/linux/drivers/ide/cs5530.c
1 /*
2 * linux/drivers/ide/cs5530.c Version 0.6 Mar. 18, 2000
3 *
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Ditto of GNU General Public License.
6 *
7 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
8 * May be copied or modified under the terms of the GNU General Public License
9 *
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
12 */
13
14 #include <linux/config.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/ioport.h>
21 #include <linux/blkdev.h>
22 #include <linux/hdreg.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27 #include <asm/io.h>
28 #include <asm/irq.h>
29
30 #include "ide_modes.h"
31
32 #define DISPLAY_CS5530_TIMINGS
33
34 #if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
35 #include <linux/stat.h>
36 #include <linux/proc_fs.h>
37
38 static int cs5530_get_info(char *, char **, off_t, int);
39 extern int (*cs5530_display_info)(char *, char **, off_t, int); /* ide-proc.c */
40 extern char *ide_media_verbose(ide_drive_t *);
41 static struct pci_dev *bmide_dev;
42
43 static int cs5530_get_info (char *buffer, char **addr, off_t offset, int count)
44 {
45 char *p = buffer;
46 u32 bibma = pci_resource_start(bmide_dev, 4);
47 u8 c0 = 0, c1 = 0;
48
49 /*
50 * at that point bibma+0x2 et bibma+0xa are byte registers
51 * to investigate:
52 */
53
54 c0 = inb_p((unsigned short)bibma + 0x02);
55 c1 = inb_p((unsigned short)bibma + 0x0a);
56
57 p += sprintf(p, "\n Cyrix 5530 Chipset.\n");
58 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
59 p += sprintf(p, " %sabled %sabled\n",
60 (c0&0x80) ? "dis" : " en",
61 (c1&0x80) ? "dis" : " en");
62 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
63 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
64 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
65 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
66
67 p += sprintf(p, "UDMA\n");
68 p += sprintf(p, "DMA\n");
69 p += sprintf(p, "PIO\n");
70
71 return p-buffer;
72 }
73 #endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
74
75 byte cs5530_proc = 0;
76
77 extern char *ide_xfer_verbose (byte xfer_rate);
78
79 /*
80 * Set a new transfer mode at the drive
81 */
82 int cs5530_set_xfer_mode (ide_drive_t *drive, byte mode)
83 {
84 int error = 0;
85
86 printk("%s: cs5530_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode));
87 error = ide_config_drive_speed(drive, mode);
88
89 return error;
90 }
91
92 /*
93 * Here are the standard PIO mode 0-4 timings for each "format".
94 * Format-0 uses fast data reg timings, with slower command reg timings.
95 * Format-1 uses fast timings for all registers, but won't work with all drives.
96 */
97 static unsigned int cs5530_pio_timings[2][5] =
98 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
99 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}};
100
101 /*
102 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
103 */
104 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
105 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
106
107 /*
108 * cs5530_tuneproc() handles selection/setting of PIO modes
109 * for both the chipset and drive.
110 *
111 * The ide_init_cs5530() routine guarantees that all drives
112 * will have valid default PIO timings set up before we get here.
113 */
114 static void cs5530_tuneproc (ide_drive_t *drive, byte pio) /* pio=255 means "autotune" */
115 {
116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned int format, basereg = CS5530_BASEREG(hwif);
118 static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
119
120 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
121 if (!cs5530_set_xfer_mode(drive, modes[pio])) {
122 format = (inl(basereg+4) >> 31) & 1;
123 outl(cs5530_pio_timings[format][pio], basereg+(drive->select.b.unit<<3));
124 }
125 }
126
127 #ifdef CONFIG_BLK_DEV_IDEDMA
128 /*
129 * cs5530_config_dma() handles selection/setting of DMA/UDMA modes
130 * for both the chipset and drive.
131 */
132 static int cs5530_config_dma (ide_drive_t *drive)
133 {
134 int udma_ok = 1, mode = 0;
135 ide_hwif_t *hwif = HWIF(drive);
136 int unit = drive->select.b.unit;
137 ide_drive_t *mate = &hwif->drives[unit^1];
138 struct hd_driveid *id = drive->id;
139 unsigned int basereg, reg, timings;
140
141
142 /*
143 * Default to DMA-off in case we run into trouble here.
144 */
145 (void)hwif->dmaproc(ide_dma_off_quietly, drive); /* turn off DMA while we fiddle */
146 outb(inb(hwif->dma_base+2)&~(unit?0x40:0x20), hwif->dma_base+2); /* clear DMA_capable bit */
147
148 /*
149 * The CS5530 specifies that two drives sharing a cable cannot
150 * mix UDMA/MDMA. It has to be one or the other, for the pair,
151 * though different timings can still be chosen for each drive.
152 * We could set the appropriate timing bits on the fly,
153 * but that might be a bit confusing. So, for now we statically
154 * handle this requirement by looking at our mate drive to see
155 * what it is capable of, before choosing a mode for our own drive.
156 */
157 if (mate->present) {
158 struct hd_driveid *mateid = mate->id;
159 if (mateid && (mateid->capability & 1) && !hwif->dmaproc(ide_dma_bad_drive, mate)) {
160 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
161 udma_ok = 1;
162 else if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
163 udma_ok = 0;
164 else
165 udma_ok = 1;
166 }
167 }
168
169 /*
170 * Now see what the current drive is capable of,
171 * selecting UDMA only if the mate said it was ok.
172 */
173 if (id && (id->capability & 1) && hwif->autodma && !hwif->dmaproc(ide_dma_bad_drive, drive)) {
174 if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
175 if (id->dma_ultra & 4)
176 mode = XFER_UDMA_2;
177 else if (id->dma_ultra & 2)
178 mode = XFER_UDMA_1;
179 else if (id->dma_ultra & 1)
180 mode = XFER_UDMA_0;
181 }
182 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
183 if (id->dma_mword & 4)
184 mode = XFER_MW_DMA_2;
185 else if (id->dma_mword & 2)
186 mode = XFER_MW_DMA_1;
187 else if (id->dma_mword & 1)
188 mode = XFER_MW_DMA_0;
189 }
190 }
191
192 /*
193 * Tell the drive to switch to the new mode; abort on failure.
194 */
195 if (!mode || cs5530_set_xfer_mode(drive, mode))
196 return 1; /* failure */
197
198 /*
199 * Now tune the chipset to match the drive:
200 */
201 switch (mode) {
202 case XFER_UDMA_0: timings = 0x00921250; break;
203 case XFER_UDMA_1: timings = 0x00911140; break;
204 case XFER_UDMA_2: timings = 0x00911030; break;
205 case XFER_MW_DMA_0: timings = 0x00077771; break;
206 case XFER_MW_DMA_1: timings = 0x00012121; break;
207 case XFER_MW_DMA_2: timings = 0x00002020; break;
208 default:
209 printk("%s: cs5530_config_dma: huh? mode=%02x\n", drive->name, mode);
210 return 1; /* failure */
211 }
212 basereg = CS5530_BASEREG(hwif);
213 reg = inl(basereg+4); /* get drive0 config register */
214 timings |= reg & 0x80000000; /* preserve PIO format bit */
215 if (unit == 0) { /* are we configuring drive0? */
216 outl(timings, basereg+4); /* write drive0 config register */
217 } else {
218 if (timings & 0x00100000)
219 reg |= 0x00100000; /* enable UDMA timings for both drives */
220 else
221 reg &= ~0x00100000; /* disable UDMA timings for both drives */
222 outl(reg, basereg+4); /* write drive0 config register */
223 outl(timings, basereg+12); /* write drive1 config register */
224 }
225 outb(inb(hwif->dma_base+2)|(unit?0x40:0x20), hwif->dma_base+2); /* set DMA_capable bit */
226
227 /*
228 * Finally, turn DMA on in software, and exit.
229 */
230 return hwif->dmaproc(ide_dma_on, drive); /* success */
231 }
232
233 /*
234 * This is a CS5530-specific wrapper for the standard ide_dmaproc().
235 * We need it for our custom "ide_dma_check" function.
236 * All other requests are forwarded to the standard ide_dmaproc().
237 */
238 int cs5530_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
239 {
240 switch (func) {
241 case ide_dma_check:
242 return cs5530_config_dma(drive);
243 default:
244 break;
245 }
246 /* Other cases are done by generic IDE-DMA code. */
247 return ide_dmaproc(func, drive);
248 }
249 #endif /* CONFIG_BLK_DEV_IDEDMA */
250
251 /*
252 * Initialize the cs5530 bridge for reliable IDE DMA operation.
253 */
254 unsigned int __init pci_init_cs5530 (struct pci_dev *dev, const char *name)
255 {
256 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
257 unsigned short pcicmd = 0;
258 unsigned long flags;
259
260 #if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
261 if (!cs5530_proc) {
262 cs5530_proc = 1;
263 bmide_dev = dev;
264 cs5530_display_info = &cs5530_get_info;
265 }
266 #endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
267
268 pci_for_each_dev (dev) {
269 if (dev->vendor == PCI_VENDOR_ID_CYRIX) {
270 switch (dev->device) {
271 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
272 master_0 = dev;
273 break;
274 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
275 cs5530_0 = dev;
276 break;
277 }
278 }
279 }
280 if (!master_0) {
281 printk("%s: unable to locate PCI MASTER function\n", name);
282 return 0;
283 }
284 if (!cs5530_0) {
285 printk("%s: unable to locate CS5530 LEGACY function\n", name);
286 return 0;
287 }
288
289 save_flags(flags);
290 cli(); /* all CPUs (there should only be one CPU with this chipset) */
291
292 /*
293 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
294 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
295 */
296 pci_read_config_word (cs5530_0, PCI_COMMAND, &pcicmd);
297 pci_write_config_word(cs5530_0, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
298
299 /*
300 * Set PCI CacheLineSize to 16-bytes:
301 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
302 */
303 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
304
305 /*
306 * Disable trapping of UDMA register accesses (Win98 hack):
307 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
308 */
309 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
310
311 /*
312 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
313 * The other settings are what is necessary to get the register
314 * into a sane state for IDE DMA operation.
315 */
316 pci_write_config_byte(master_0, 0x40, 0x1e);
317
318 /*
319 * Set max PCI burst size (16-bytes seems to work best):
320 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
321 * all others: clear bit-1 at 0x41, and do:
322 * 128bytes: OR 0x00 at 0x41
323 * 256bytes: OR 0x04 at 0x41
324 * 512bytes: OR 0x08 at 0x41
325 * 1024bytes: OR 0x0c at 0x41
326 */
327 pci_write_config_byte(master_0, 0x41, 0x14);
328
329 /*
330 * These settings are necessary to get the chip
331 * into a sane state for IDE DMA operation.
332 */
333 pci_write_config_byte(master_0, 0x42, 0x00);
334 pci_write_config_byte(master_0, 0x43, 0xc1);
335
336 restore_flags(flags);
337
338 return 0;
339 }
340
341 /*
342 * This gets invoked by the IDE driver once for each channel,
343 * and performs channel-specific pre-initialization before drive probing.
344 */
345 void __init ide_init_cs5530 (ide_hwif_t *hwif)
346 {
347 if (hwif->mate)
348 hwif->serialized = hwif->mate->serialized = 1;
349 if (!hwif->dma_base) {
350 hwif->autodma = 0;
351 } else {
352 unsigned int basereg, d0_timings;
353
354 #ifdef CONFIG_BLK_DEV_IDEDMA
355 hwif->dmaproc = &cs5530_dmaproc;
356 #else
357 hwif->autodma = 0;
358 #endif /* CONFIG_BLK_DEV_IDEDMA */
359
360 hwif->tuneproc = &cs5530_tuneproc;
361 basereg = CS5530_BASEREG(hwif);
362 d0_timings = inl(basereg+0);
363 if (CS5530_BAD_PIO(d0_timings)) { /* PIO timings not initialized? */
364 outl(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0);
365 if (!hwif->drives[0].autotune)
366 hwif->drives[0].autotune = 1; /* needs autotuning later */
367 }
368 if (CS5530_BAD_PIO(inl(basereg+8))) { /* PIO timings not initialized? */
369 outl(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8);
370 if (!hwif->drives[1].autotune)
371 hwif->drives[1].autotune = 1; /* needs autotuning later */
372 }
373 }
374 }
375