File: /usr/src/linux/drivers/ide/cy82c693.c
1 /*
2 * linux/drivers/ide/cy82c693.c Version 0.34 Dec. 13, 1999
3 *
4 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>, Integrater
6 *
7 * CYPRESS CY82C693 chipset IDE controller
8 *
9 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
10 * Writting the driver was quite simple, since most of the job is
11 * done by the generic pci-ide support.
12 * The hard part was finding the CY82C693's datasheet on Cypress's
13 * web page :-(. But Altavista solved this problem :-).
14 *
15 *
16 * Notes:
17 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
18 * a large and fast disk - the results look great, so I'd say the
19 * driver is working fine :-)
20 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
21 * - this is my first linux driver, so there's probably a lot of room
22 * for optimizations and bug fixing, so feel free to do it.
23 * - use idebus=xx parameter to set PCI bus speed - needed to calc
24 * timings for PIO modes (default will be 40)
25 * - if using PIO mode it's a good idea to set the PIO mode and
26 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
27 * - I had some problems with my IBM DHEA with PIO modes < 2
28 * (lost interrupts) ?????
29 * - first tests with DMA look okay, they seem to work, but there is a
30 * problem with sound - the BusMaster IDE TimeOut should fixed this
31 *
32 *
33 * History:
34 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
35 * ASK@1999-01-23: v0.33 made a few minor code clean ups
36 * removed DMA clock speed setting by default
37 * added boot message
38 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
39 * added support to set DMA Controller Clock Speed
40 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes on some drive
41 * ASK@1998-10-29: v0.3 added support to set DMA modes
42 * ASK@1998-10-28: v0.2 added support to set PIO modes
43 * ASK@1998-10-27: v0.1 first version - chipset detection
44 *
45 */
46
47 #include <linux/config.h>
48 #include <linux/types.h>
49 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/ide.h>
52 #include <linux/init.h>
53
54 #include <asm/io.h>
55
56 #include "ide_modes.h"
57
58 /* the current version */
59 #define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
60
61 /*
62 * The following are used to debug the driver.
63 */
64 #define CY82C693_DEBUG_LOGS 0
65 #define CY82C693_DEBUG_INFO 0
66
67 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
68 #undef CY82C693_SETDMA_CLOCK
69
70 /*
71 * note: the value for busmaster timeout is tricky and i got it by trial and error !
72 * using a to low value will cause DMA timeouts and drop IDE performance
73 * using a to high value will cause audio playback to scatter
74 * if you know a better value or how to calc it, please let me know
75 */
76 #define BUSMASTER_TIMEOUT 0x50 /* twice the value written in cy82c693ub datasheet */
77 /*
78 * the value above was tested on my machine and it seems to work okay
79 */
80
81 /* here are the offset definitions for the registers */
82 #define CY82_IDE_CMDREG 0x04
83 #define CY82_IDE_ADDRSETUP 0x48
84 #define CY82_IDE_MASTER_IOR 0x4C
85 #define CY82_IDE_MASTER_IOW 0x4D
86 #define CY82_IDE_SLAVE_IOR 0x4E
87 #define CY82_IDE_SLAVE_IOW 0x4F
88 #define CY82_IDE_MASTER_8BIT 0x50
89 #define CY82_IDE_SLAVE_8BIT 0x51
90
91 #define CY82_INDEX_PORT 0x22
92 #define CY82_DATA_PORT 0x23
93
94 #define CY82_INDEX_CTRLREG1 0x01
95 #define CY82_INDEX_CHANNEL0 0x30
96 #define CY82_INDEX_CHANNEL1 0x31
97 #define CY82_INDEX_TIMEOUT 0x32
98
99 /* the max PIO mode - from datasheet */
100 #define CY82C693_MAX_PIO 4
101
102 /* the min and max PCI bus speed in MHz - from datasheet */
103 #define CY82C963_MIN_BUS_SPEED 25
104 #define CY82C963_MAX_BUS_SPEED 33
105
106 /* the struct for the PIO mode timings */
107 typedef struct pio_clocks_s {
108 byte address_time; /* Address setup (clocks) */
109 byte time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
110 byte time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
111 byte time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
112 } pio_clocks_t;
113
114 /*
115 * calc clocks using bus_speed
116 * returns (rounded up) time in bus clocks for time in ns
117 */
118 static int calc_clk (int time, int bus_speed)
119 {
120 int clocks;
121
122 clocks = (time*bus_speed+999)/1000 -1;
123
124 if (clocks < 0)
125 clocks = 0;
126
127 if (clocks > 0x0F)
128 clocks = 0x0F;
129
130 return clocks;
131 }
132
133 /*
134 * compute the values for the clock registers for PIO
135 * mode and pci_clk [MHz] speed
136 *
137 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
138 * for mode 3 and 4 drives 8 and 16-bit timings are the same
139 *
140 */
141 static void compute_clocks (byte pio, pio_clocks_t *p_pclk)
142 {
143 int clk1, clk2;
144 int bus_speed = system_bus_clock(); /* get speed of PCI bus */
145
146 /* we don't check against CY82C693's min and max speed,
147 * so you can play with the idebus=xx parameter
148 */
149
150 if (pio > CY82C693_MAX_PIO)
151 pio = CY82C693_MAX_PIO;
152
153 /* let's calc the address setup time clocks */
154 p_pclk->address_time = (byte)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
155
156 /* let's calc the active and recovery time clocks */
157 clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
158
159 /* calc recovery timing */
160 clk2 = ide_pio_timings[pio].cycle_time -
161 ide_pio_timings[pio].active_time -
162 ide_pio_timings[pio].setup_time;
163
164 clk2 = calc_clk(clk2, bus_speed);
165
166 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
167
168 /* note: we use the same values for 16bit IOR and IOW
169 * those are all the same, since I don't have other
170 * timings than those from ide_modes.h
171 */
172
173 p_pclk->time_16r = (byte)clk1;
174 p_pclk->time_16w = (byte)clk1;
175
176 /* what are good values for 8bit ?? */
177 p_pclk->time_8 = (byte)clk1;
178 }
179
180 #ifdef CONFIG_BLK_DEV_IDEDMA
181 /*
182 * set DMA mode a specific channel for CY82C693
183 */
184 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
185 {
186 byte index;
187 byte data;
188
189 if (mode>2) /* make sure we set a valid mode */
190 mode = 2;
191
192 if (mode > drive->id->tDMA) /* to be absolutly sure we have a valid mode */
193 mode = drive->id->tDMA;
194
195 index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
196
197 #if CY82C693_DEBUG_LOGS
198 /* for debug let's show the previous values */
199
200 OUT_BYTE(index, CY82_INDEX_PORT);
201 data = IN_BYTE(CY82_DATA_PORT);
202
203 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, (data&0x3), ((data>>2)&1));
204 #endif /* CY82C693_DEBUG_LOGS */
205
206 data = (byte)mode|(byte)(single<<2);
207
208 OUT_BYTE(index, CY82_INDEX_PORT);
209 OUT_BYTE(data, CY82_DATA_PORT);
210
211 #if CY82C693_DEBUG_INFO
212 printk (KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, mode, single);
213 #endif /* CY82C693_DEBUG_INFO */
214
215 /*
216 * note: below we set the value for Bus Master IDE TimeOut Register
217 * I'm not absolutly sure what this does, but it solved my problem
218 * with IDE DMA and sound, so I now can play sound and work with
219 * my IDE driver at the same time :-)
220 *
221 * If you know the correct (best) value for this register please
222 * let me know - ASK
223 */
224
225 data = BUSMASTER_TIMEOUT;
226 OUT_BYTE(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
227 OUT_BYTE(data, CY82_DATA_PORT);
228
229 #if CY82C693_DEBUG_INFO
230 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", drive->name, data);
231 #endif /* CY82C693_DEBUG_INFO */
232 }
233
234 /*
235 * used to set DMA mode for CY82C693 (single and multi modes)
236 */
237 static int cy82c693_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
238 {
239 /*
240 * if the function is dma on, set dma mode for drive everything
241 * else is done by the defaul func
242 */
243 if (func == ide_dma_on) {
244 struct hd_driveid *id = drive->id;
245
246 #if CY82C693_DEBUG_INFO
247 printk (KERN_INFO "dma_on: %s\n", drive->name);
248 #endif /* CY82C693_DEBUG_INFO */
249
250 if (id != NULL) {
251 /* Enable DMA on any drive that has DMA (multi or single) enabled */
252 if (id->field_valid & 2) { /* regular DMA */
253 int mmode, smode;
254
255 mmode = id->dma_mword & (id->dma_mword >> 8);
256 smode = id->dma_1word & (id->dma_1word >> 8);
257
258 if (mmode != 0)
259 cy82c693_dma_enable(drive, (mmode >> 1), 0); /* enable multi */
260 else if (smode != 0)
261 cy82c693_dma_enable(drive, (smode >> 1), 1); /* enable single */
262 }
263 }
264 }
265 return ide_dmaproc(func, drive);
266 }
267 #endif /* CONFIG_BLK_DEV_IDEDMA */
268
269 /*
270 * tune ide drive - set PIO mode
271 */
272 static void cy82c693_tune_drive (ide_drive_t *drive, byte pio)
273 {
274 ide_hwif_t *hwif = HWIF(drive);
275 struct pci_dev *dev = hwif->pci_dev;
276 pio_clocks_t pclk;
277 unsigned int addrCtrl;
278
279 /* select primary or secondary channel */
280 if (hwif->index > 0) { /* drive is on the secondary channel */
281 dev = pci_find_slot(dev->bus->number, dev->devfn+1);
282 if (!dev) {
283 printk(KERN_ERR "%s: tune_drive: Cannot find secondary interface!\n", drive->name);
284 return;
285 }
286 }
287
288 #if CY82C693_DEBUG_LOGS
289 /* for debug let's show the register values */
290
291 if (drive->select.b.unit == 0) {
292 /*
293 * get master drive registers
294 * address setup control register
295 * is 32 bit !!!
296 */
297 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
298 addrCtrl &= 0x0F;
299
300 /* now let's get the remaining registers */
301 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
302 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
303 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
304 } else {
305 /*
306 * set slave drive registers
307 * address setup control register
308 * is 32 bit !!!
309 */
310 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
311
312 addrCtrl &= 0xF0;
313 addrCtrl >>= 4;
314
315 /* now let's get the remaining registers */
316 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
317 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
318 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
319 }
320
321 printk (KERN_INFO "%s (ch=%d, dev=%d): PIO timing is (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
322 #endif /* CY82C693_DEBUG_LOGS */
323
324 /* first let's calc the pio modes */
325 pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
326
327 #if CY82C693_DEBUG_INFO
328 printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
329 #endif /* CY82C693_DEBUG_INFO */
330
331 compute_clocks(pio, &pclk); /* let's calc the values for this PIO mode */
332
333 /* now let's write the clocks registers */
334 if (drive->select.b.unit == 0) {
335 /*
336 * set master drive
337 * address setup control register
338 * is 32 bit !!!
339 */
340 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
341
342 addrCtrl &= (~0xF);
343 addrCtrl |= (unsigned int)pclk.address_time;
344 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
345
346 /* now let's set the remaining registers */
347 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
348 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
349 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
350
351 addrCtrl &= 0xF;
352 } else {
353 /*
354 * set slave drive
355 * address setup control register
356 * is 32 bit !!!
357 */
358 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
359
360 addrCtrl &= (~0xF0);
361 addrCtrl |= ((unsigned int)pclk.address_time<<4);
362 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
363
364 /* now let's set the remaining registers */
365 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
366 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
367 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
368
369 addrCtrl >>= 4;
370 addrCtrl &= 0xF;
371 }
372
373 #if CY82C693_DEBUG_INFO
374 printk (KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
375 #endif /* CY82C693_DEBUG_INFO */
376 }
377
378 /*
379 * this function is called during init and is used to setup the cy82c693 chip
380 */
381 /*
382 * FIXME! "pci_init_cy82c693" really should replace
383 * the "init_cy82c693_chip", it is the correct location to tinker/setup
384 * the device prior to INIT.
385 */
386
387 unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
388 {
389 #ifdef CY82C693_SETDMA_CLOCK
390 byte data;
391 #endif /* CY82C693_SETDMA_CLOCK */
392
393 /* write info about this verion of the driver */
394 printk (KERN_INFO CY82_VERSION "\n");
395
396 #ifdef CY82C693_SETDMA_CLOCK
397 /* okay let's set the DMA clock speed */
398
399 OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
400 data = IN_BYTE(CY82_DATA_PORT);
401
402 #if CY82C693_DEBUG_INFO
403 printk (KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n", name, data);
404 #endif /* CY82C693_DEBUG_INFO */
405
406 /*
407 * for some reason sometimes the DMA controller
408 * speed is set to ATCLK/2 ???? - we fix this here
409 *
410 * note: i don't know what causes this strange behaviour,
411 * but even changing the dma speed doesn't solve it :-(
412 * the ide performance is still only half the normal speed
413 *
414 * if anybody knows what goes wrong with my machine, please
415 * let me know - ASK
416 */
417
418 data |= 0x03;
419
420 OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
421 OUT_BYTE(data, CY82_DATA_PORT);
422
423 #if CY82C693_DEBUG_INFO
424 printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", name, data);
425 #endif /* CY82C693_DEBUG_INFO */
426
427 #endif /* CY82C693_SETDMA_CLOCK */
428 return 0;
429 }
430
431 /*
432 * the init function - called for each ide channel once
433 */
434 void __init ide_init_cy82c693(ide_hwif_t *hwif)
435 {
436 hwif->chipset = ide_cy82c693;
437 hwif->tuneproc = &cy82c693_tune_drive;
438 hwif->drives[0].autotune = 1;
439 hwif->drives[1].autotune = 1;
440 hwif->autodma = 0;
441
442 #ifdef CONFIG_BLK_DEV_IDEDMA
443 if (hwif->dma_base) {
444 hwif->dmaproc = &cy82c693_dmaproc;
445 if (!noautodma)
446 hwif->autodma = 1;
447 }
448 #endif /* CONFIG_BLK_DEV_IDEDMA */
449 }
450