File: /usr/src/linux/drivers/ide/hpt34x.c
1 /*
2 * linux/drivers/ide/hpt34x.c Version 0.31 June. 9, 2000
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 *
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
11 *
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
18 *
19 * ide-pci.c reference
20 *
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
25 */
26
27 #include <linux/config.h>
28 #include <linux/types.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/timer.h>
32 #include <linux/mm.h>
33 #include <linux/ioport.h>
34 #include <linux/blkdev.h>
35 #include <linux/hdreg.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include "ide_modes.h"
44
45 #ifndef SPLIT_BYTE
46 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
47 #endif
48
49 #define HPT343_DEBUG_DRIVE_INFO 0
50
51 #undef DISPLAY_HPT34X_TIMINGS
52
53 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
54 #include <linux/stat.h>
55 #include <linux/proc_fs.h>
56
57 static int hpt34x_get_info(char *, char **, off_t, int);
58 extern int (*hpt34x_display_info)(char *, char **, off_t, int); /* ide-proc.c */
59 extern char *ide_media_verbose(ide_drive_t *);
60 static struct pci_dev *bmide_dev;
61
62 static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
63 {
64 char *p = buffer;
65 u32 bibma = pci_resource_start(bmide_dev, 4);
66 u8 c0 = 0, c1 = 0;
67
68 /*
69 * at that point bibma+0x2 et bibma+0xa are byte registers
70 * to investigate:
71 */
72 c0 = inb_p((unsigned short)bibma + 0x02);
73 c1 = inb_p((unsigned short)bibma + 0x0a);
74
75 p += sprintf(p, "\n HPT34X Chipset.\n");
76 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
77 p += sprintf(p, " %sabled %sabled\n",
78 (c0&0x80) ? "dis" : " en",
79 (c1&0x80) ? "dis" : " en");
80 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
81 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
82 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
83 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
84
85 p += sprintf(p, "UDMA\n");
86 p += sprintf(p, "DMA\n");
87 p += sprintf(p, "PIO\n");
88
89 return p-buffer; /* => must be less than 4k! */
90 }
91 #endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
92
93 byte hpt34x_proc = 0;
94
95 extern char *ide_xfer_verbose (byte xfer_rate);
96
97 static void hpt34x_clear_chipset (ide_drive_t *drive)
98 {
99 unsigned int reg1 = 0, tmp1 = 0;
100 unsigned int reg2 = 0, tmp2 = 0;
101
102 pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, ®1);
103 pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, ®2);
104 tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
105 tmp2 = (reg2 & ~(0x11 << drive->dn));
106 pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
107 pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
108 }
109
110 static int hpt34x_tune_chipset (ide_drive_t *drive, byte speed)
111 {
112 int err;
113 byte hi_speed, lo_speed;
114 unsigned int reg1 = 0, tmp1 = 0;
115 unsigned int reg2 = 0, tmp2 = 0;
116
117 SPLIT_BYTE(speed, hi_speed, lo_speed);
118
119 if (hi_speed & 7) {
120 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
121 } else {
122 lo_speed <<= 5;
123 lo_speed >>= 5;
124 }
125
126 pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, ®1);
127 pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, ®2);
128 tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
129 tmp2 = ((hi_speed << drive->dn) | reg2);
130 err = ide_config_drive_speed(drive, speed);
131 pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
132 pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
133
134 if (!drive->init_speed)
135 drive->init_speed = speed;
136
137 #if HPT343_DEBUG_DRIVE_INFO
138 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)"
139 " (0x%02x 0x%02x) 0x%04x\n",
140 drive->name, ide_xfer_verbose(speed),
141 drive->dn, reg1, tmp1, reg2, tmp2,
142 hi_speed, lo_speed, err);
143 #endif /* HPT343_DEBUG_DRIVE_INFO */
144
145 drive->current_speed = speed;
146 return(err);
147 }
148
149 static void config_chipset_for_pio (ide_drive_t *drive)
150 {
151 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
152 unsigned short xfer_pio = drive->id->eide_pio_modes;
153
154 byte timing, speed, pio;
155
156 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
157
158 if (xfer_pio> 4)
159 xfer_pio = 0;
160
161 if (drive->id->eide_pio_iordy > 0) {
162 for (xfer_pio = 5;
163 xfer_pio>0 &&
164 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
165 xfer_pio--);
166 } else {
167 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
168 (drive->id->eide_pio_modes & 2) ? 0x04 :
169 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
170 }
171
172 timing = (xfer_pio >= pio) ? xfer_pio : pio;
173
174 switch(timing) {
175 case 4: speed = XFER_PIO_4;break;
176 case 3: speed = XFER_PIO_3;break;
177 case 2: speed = XFER_PIO_2;break;
178 case 1: speed = XFER_PIO_1;break;
179 default:
180 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
181 break;
182 }
183 (void) hpt34x_tune_chipset(drive, speed);
184 }
185
186 static void hpt34x_tune_drive (ide_drive_t *drive, byte pio)
187 {
188 byte speed;
189
190 switch(pio) {
191 case 4: speed = XFER_PIO_4;break;
192 case 3: speed = XFER_PIO_3;break;
193 case 2: speed = XFER_PIO_2;break;
194 case 1: speed = XFER_PIO_1;break;
195 default: speed = XFER_PIO_0;break;
196 }
197 hpt34x_clear_chipset(drive);
198 (void) hpt34x_tune_chipset(drive, speed);
199 }
200
201 #ifdef CONFIG_BLK_DEV_IDEDMA
202 /*
203 * This allows the configuration of ide_pci chipset registers
204 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
205 * after the drive is reported by the OS. Initally for designed for
206 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
207 */
208 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
209 {
210 struct hd_driveid *id = drive->id;
211 byte speed = 0x00;
212
213 if (drive->media != ide_disk)
214 return ((int) ide_dma_off_quietly);
215
216 hpt34x_clear_chipset(drive);
217
218 if ((id->dma_ultra & 0x0010) && ultra) {
219 speed = XFER_UDMA_2;
220 } else if ((id->dma_ultra & 0x0008) && ultra) {
221 speed = XFER_UDMA_2;
222 } else if ((id->dma_ultra & 0x0004) && ultra) {
223 speed = XFER_UDMA_2;
224 } else if ((id->dma_ultra & 0x0002) && ultra) {
225 speed = XFER_UDMA_1;
226 } else if ((id->dma_ultra & 0x0001) && ultra) {
227 speed = XFER_UDMA_0;
228 } else if (id->dma_mword & 0x0004) {
229 speed = XFER_MW_DMA_2;
230 } else if (id->dma_mword & 0x0002) {
231 speed = XFER_MW_DMA_1;
232 } else if (id->dma_mword & 0x0001) {
233 speed = XFER_MW_DMA_0;
234 } else if (id->dma_1word & 0x0004) {
235 speed = XFER_SW_DMA_2;
236 } else if (id->dma_1word & 0x0002) {
237 speed = XFER_SW_DMA_1;
238 } else if (id->dma_1word & 0x0001) {
239 speed = XFER_SW_DMA_0;
240 } else {
241 return ((int) ide_dma_off_quietly);
242 }
243
244 (void) hpt34x_tune_chipset(drive, speed);
245
246 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_off :
247 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
248 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
249 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
250 ide_dma_off_quietly);
251 }
252
253 static int config_drive_xfer_rate (ide_drive_t *drive)
254 {
255 struct hd_driveid *id = drive->id;
256 ide_dma_action_t dma_func = ide_dma_on;
257
258 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
259 /* Consult the list of known "bad" drives */
260 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
261 dma_func = ide_dma_off;
262 goto fast_ata_pio;
263 }
264 dma_func = ide_dma_off_quietly;
265 if (id->field_valid & 4) {
266 if (id->dma_ultra & 0x0007) {
267 /* Force if Capable UltraDMA */
268 dma_func = config_chipset_for_dma(drive, 1);
269 if ((id->field_valid & 2) &&
270 (dma_func != ide_dma_on))
271 goto try_dma_modes;
272 }
273 } else if (id->field_valid & 2) {
274 try_dma_modes:
275 if ((id->dma_mword & 0x0007) ||
276 (id->dma_1word & 0x0007)) {
277 /* Force if Capable regular DMA modes */
278 dma_func = config_chipset_for_dma(drive, 0);
279 if (dma_func != ide_dma_on)
280 goto no_dma_set;
281 }
282 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
283 if (id->eide_dma_time > 150) {
284 goto no_dma_set;
285 }
286 /* Consult the list of known "good" drives */
287 dma_func = config_chipset_for_dma(drive, 0);
288 if (dma_func != ide_dma_on)
289 goto no_dma_set;
290 } else {
291 goto fast_ata_pio;
292 }
293 } else if ((id->capability & 8) || (id->field_valid & 2)) {
294 fast_ata_pio:
295 dma_func = ide_dma_off_quietly;
296 no_dma_set:
297 config_chipset_for_pio(drive);
298 }
299
300 #ifndef CONFIG_HPT34X_AUTODMA
301 if (dma_func == ide_dma_on)
302 dma_func = ide_dma_off;
303 #endif /* CONFIG_HPT34X_AUTODMA */
304
305 return HWIF(drive)->dmaproc(dma_func, drive);
306 }
307
308 /*
309 * hpt34x_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
310 *
311 * This is specific to the HPT343 UDMA bios-less chipset
312 * and HPT345 UDMA bios chipset (stamped HPT363)
313 * by HighPoint|Triones Technologies, Inc.
314 */
315
316 int hpt34x_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
317 {
318 ide_hwif_t *hwif = HWIF(drive);
319 unsigned long dma_base = hwif->dma_base;
320 unsigned int count, reading = 0;
321 byte dma_stat;
322
323 switch (func) {
324 case ide_dma_check:
325 return config_drive_xfer_rate(drive);
326 case ide_dma_read:
327 reading = 1 << 3;
328 case ide_dma_write:
329 if (!(count = ide_build_dmatable(drive, func)))
330 return 1; /* try PIO instead of DMA */
331 outl(hwif->dmatable_dma, dma_base + 4); /* PRD table */
332 reading |= 0x01;
333 outb(reading, dma_base); /* specify r/w */
334 outb(inb(dma_base+2)|6, dma_base+2); /* clear INTR & ERROR flags */
335 drive->waiting_for_dma = 1;
336 if (drive->media != ide_disk)
337 return 0;
338 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); /* issue cmd to drive */
339 OUT_BYTE((reading == 9) ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
340 return 0;
341 case ide_dma_end: /* returns 1 on error, 0 otherwise */
342 drive->waiting_for_dma = 0;
343 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
344 dma_stat = inb(dma_base+2); /* get DMA status */
345 outb(dma_stat|6, dma_base+2); /* clear the INTR & ERROR bits */
346 ide_destroy_dmatable(drive); /* purge DMA mappings */
347 return (dma_stat & 7) != 4; /* verify good DMA status */
348 default:
349 break;
350 }
351 return ide_dmaproc(func, drive); /* use standard DMA stuff */
352 }
353 #endif /* CONFIG_BLK_DEV_IDEDMA */
354
355 /*
356 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
357 */
358 #define HPT34X_PCI_INIT_REG 0x80
359
360 unsigned int __init pci_init_hpt34x (struct pci_dev *dev, const char *name)
361 {
362 int i = 0;
363 unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
364 unsigned short cmd;
365 unsigned long flags;
366
367 __save_flags(flags); /* local CPU only */
368 __cli(); /* local CPU only */
369
370 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
371 pci_read_config_word(dev, PCI_COMMAND, &cmd);
372
373 if (cmd & PCI_COMMAND_MEMORY) {
374 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
375 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
376 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n", dev->resource[PCI_ROM_RESOURCE].start);
377 }
378 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
379 } else {
380 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
381 }
382
383 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
384 dev->resource[0].start = (hpt34xIoBase + 0x20);
385 dev->resource[1].start = (hpt34xIoBase + 0x34);
386 dev->resource[2].start = (hpt34xIoBase + 0x28);
387 dev->resource[3].start = (hpt34xIoBase + 0x3c);
388 for(i=0; i<4; i++)
389 dev->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
390 /*
391 * Since 20-23 can be assigned and are R/W, we correct them.
392 */
393 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, dev->resource[0].start);
394 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start);
395 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, dev->resource[2].start);
396 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, dev->resource[3].start);
397 pci_write_config_word(dev, PCI_COMMAND, cmd);
398
399 __restore_flags(flags); /* local CPU only */
400
401 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
402 if (!hpt34x_proc) {
403 hpt34x_proc = 1;
404 bmide_dev = dev;
405 hpt34x_display_info = &hpt34x_get_info;
406 }
407 #endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
408
409 return dev->irq;
410 }
411
412 void __init ide_init_hpt34x (ide_hwif_t *hwif)
413 {
414 hwif->tuneproc = &hpt34x_tune_drive;
415 hwif->speedproc = &hpt34x_tune_chipset;
416
417 #ifdef CONFIG_BLK_DEV_IDEDMA
418 if (hwif->dma_base) {
419 unsigned short pcicmd = 0;
420
421 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
422 if (!noautodma)
423 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
424 else
425 hwif->autodma = 0;
426
427 hwif->dmaproc = &hpt34x_dmaproc;
428 } else {
429 hwif->drives[0].autotune = 1;
430 hwif->drives[1].autotune = 1;
431 }
432 #else /* !CONFIG_BLK_DEV_IDEDMA */
433 hwif->drives[0].autotune = 1;
434 hwif->drives[1].autotune = 1;
435 hwif->autodma = 0;
436 #endif /* CONFIG_BLK_DEV_IDEDMA */
437 }
438