File: /usr/src/linux/drivers/ide/hpt366.c
1 /*
2 * linux/drivers/ide/hpt366.c Version 0.18 June. 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to HighPoint Technologies for their assistance, and hardware.
8 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
9 * donation of an ABit BP6 mainboard, processor, and memory acellerated
10 * development and support.
11 *
12 * Note that final HPT370 support was done by force extraction of GPL.
13 *
14 */
15
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
21 #include <linux/mm.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
30
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #include "ide_modes.h"
35
36 #define DISPLAY_HPT366_TIMINGS
37
38 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
39 #include <linux/stat.h>
40 #include <linux/proc_fs.h>
41 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
42
43 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
44
45 const char *quirk_drives[] = {
46 "QUANTUM FIREBALLlct08 08",
47 "QUANTUM FIREBALLP KA6.4",
48 "QUANTUM FIREBALLP LM20.4",
49 "QUANTUM FIREBALLP LM20.5",
50 NULL
51 };
52
53 const char *bad_ata100_5[] = {
54 "IBM-DTLA-307075",
55 "IBM-DTLA-307060",
56 "IBM-DTLA-307045",
57 "IBM-DTLA-307030",
58 "IBM-DTLA-307020",
59 "IBM-DTLA-307015",
60 "IBM-DTLA-305040",
61 "IBM-DTLA-305030",
62 "IBM-DTLA-305020",
63 "IC35L010AVER07-0",
64 "IC35L020AVER07-0",
65 "IC35L030AVER07-0",
66 "IC35L040AVER07-0",
67 "IC35L060AVER07-0",
68 "WDC AC310200R",
69 NULL
70 };
71
72 const char *bad_ata66_4[] = {
73 "IBM-DTLA-307075",
74 "IBM-DTLA-307060",
75 "IBM-DTLA-307045",
76 "IBM-DTLA-307030",
77 "IBM-DTLA-307020",
78 "IBM-DTLA-307015",
79 "IBM-DTLA-305040",
80 "IBM-DTLA-305030",
81 "IBM-DTLA-305020",
82 "IC35L010AVER07-0",
83 "IC35L020AVER07-0",
84 "IC35L030AVER07-0",
85 "IC35L040AVER07-0",
86 "IC35L060AVER07-0",
87 "WDC AC310200R",
88 NULL
89 };
90
91 const char *bad_ata66_3[] = {
92 "WDC AC310200R",
93 NULL
94 };
95
96 const char *bad_ata33[] = {
97 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
98 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
99 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
100 "Maxtor 90510D4",
101 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
102 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
103 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
104 NULL
105 };
106
107 struct chipset_bus_clock_list_entry {
108 byte xfer_speed;
109 unsigned int chipset_settings_write;
110 unsigned int chipset_settings_read;
111 };
112
113 struct chipset_bus_clock_list_entry forty_base [] = {
114
115 { XFER_UDMA_4, 0x900fd943, 0x900fd943 },
116 { XFER_UDMA_3, 0x900ad943, 0x900ad943 },
117 { XFER_UDMA_2, 0x900bd943, 0x900bd943 },
118 { XFER_UDMA_1, 0x9008d943, 0x9008d943 },
119 { XFER_UDMA_0, 0x9008d943, 0x9008d943 },
120
121 { XFER_MW_DMA_2, 0xa008d943, 0xa008d943 },
122 { XFER_MW_DMA_1, 0xa010d955, 0xa010d955 },
123 { XFER_MW_DMA_0, 0xa010d9fc, 0xa010d9fc },
124
125 { XFER_PIO_4, 0xc008d963, 0xc008d963 },
126 { XFER_PIO_3, 0xc010d974, 0xc010d974 },
127 { XFER_PIO_2, 0xc010d997, 0xc010d997 },
128 { XFER_PIO_1, 0xc010d9c7, 0xc010d9c7 },
129 { XFER_PIO_0, 0xc018d9d9, 0xc018d9d9 },
130 { 0, 0x0120d9d9, 0x0120d9d9 }
131 };
132
133 struct chipset_bus_clock_list_entry thirty_three_base [] = {
134
135 { XFER_UDMA_4, 0x90c9a731, 0x90c9a731 },
136 { XFER_UDMA_3, 0x90cfa731, 0x90cfa731 },
137 { XFER_UDMA_2, 0x90caa731, 0x90caa731 },
138 { XFER_UDMA_1, 0x90cba731, 0x90cba731 },
139 { XFER_UDMA_0, 0x90c8a731, 0x90c8a731 },
140
141 { XFER_MW_DMA_2, 0xa0c8a731, 0xa0c8a731 },
142 { XFER_MW_DMA_1, 0xa0c8a732, 0xa0c8a732 }, /* 0xa0c8a733 */
143 { XFER_MW_DMA_0, 0xa0c8a797, 0xa0c8a797 },
144
145 { XFER_PIO_4, 0xc0c8a731, 0xc0c8a731 },
146 { XFER_PIO_3, 0xc0c8a742, 0xc0c8a742 },
147 { XFER_PIO_2, 0xc0d0a753, 0xc0d0a753 },
148 { XFER_PIO_1, 0xc0d0a7a3, 0xc0d0a7a3 }, /* 0xc0d0a793 */
149 { XFER_PIO_0, 0xc0d0a7aa, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
150 { 0, 0x0120a7a7, 0x0120a7a7 }
151 };
152
153 struct chipset_bus_clock_list_entry twenty_five_base [] = {
154
155 { XFER_UDMA_4, 0x90c98521, 0x90c98521 },
156 { XFER_UDMA_3, 0x90cf8521, 0x90cf8521 },
157 { XFER_UDMA_2, 0x90cf8521, 0x90cf8521 },
158 { XFER_UDMA_1, 0x90cb8521, 0x90cb8521 },
159 { XFER_UDMA_0, 0x90cb8521, 0x90cb8521 },
160
161 { XFER_MW_DMA_2, 0xa0ca8521, 0xa0ca8521 },
162 { XFER_MW_DMA_1, 0xa0ca8532, 0xa0ca8532 },
163 { XFER_MW_DMA_0, 0xa0ca8575, 0xa0ca8575 },
164
165 { XFER_PIO_4, 0xc0ca8521, 0xc0ca8521 },
166 { XFER_PIO_3, 0xc0ca8532, 0xc0ca8532 },
167 { XFER_PIO_2, 0xc0ca8542, 0xc0ca8542 },
168 { XFER_PIO_1, 0xc0d08572, 0xc0d08572 },
169 { XFER_PIO_0, 0xc0d08585, 0xc0d08585 },
170 { 0, 0x01208585, 0x01208585 }
171 };
172
173 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
174 { XFER_UDMA_5, 0x1A85F442, 0x16454e31 },
175 { XFER_UDMA_4, 0x16454e31, 0x16454e31 },
176 { XFER_UDMA_3, 0x166d4e31, 0x166d4e31 },
177 { XFER_UDMA_2, 0x16494e31, 0x16494e31 },
178 { XFER_UDMA_1, 0x164d4e31, 0x164d4e31 },
179 { XFER_UDMA_0, 0x16514e31, 0x16514e31 },
180
181 { XFER_MW_DMA_2, 0x26514e21, 0x26514e21 },
182 { XFER_MW_DMA_1, 0x26514e33, 0x26514e33 },
183 { XFER_MW_DMA_0, 0x26514e97, 0x26514e97 },
184
185 { XFER_PIO_4, 0x06514e21, 0x06514e21 },
186 { XFER_PIO_3, 0x06514e22, 0x06514e22 },
187 { XFER_PIO_2, 0x06514e33, 0x06514e33 },
188 { XFER_PIO_1, 0x06914e43, 0x06914e43 },
189 { XFER_PIO_0, 0x06914e57, 0x06914e57 },
190 { 0, 0x06514e57, 0x06514e57 }
191 };
192
193 #define HPT366_DEBUG_DRIVE_INFO 0
194 #define HPT370_ALLOW_ATA100_5 1
195 #define HPT366_ALLOW_ATA66_4 1
196 #define HPT366_ALLOW_ATA66_3 1
197
198 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
199 static int hpt366_get_info(char *, char **, off_t, int);
200 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
201 extern char *ide_media_verbose(ide_drive_t *);
202 static struct pci_dev *bmide_dev;
203 static struct pci_dev *bmide2_dev;
204
205 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
206 {
207 char *p = buffer;
208 u32 bibma = bmide_dev->resource[4].start;
209 u32 bibma2 = bmide2_dev->resource[4].start;
210 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
211 u8 c0 = 0, c1 = 0;
212 u32 class_rev;
213
214 pci_read_config_dword(bmide_dev, PCI_CLASS_REVISION, &class_rev);
215 class_rev &= 0xff;
216
217 /*
218 * at that point bibma+0x2 et bibma+0xa are byte registers
219 * to investigate:
220 */
221 c0 = inb_p((unsigned short)bibma + 0x02);
222 if (bmide2_dev)
223 c1 = inb_p((unsigned short)bibma2 + 0x02);
224
225 p += sprintf(p, "\n %s Chipset.\n", chipset_names[class_rev]);
226 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
227 p += sprintf(p, " %sabled %sabled\n",
228 (c0&0x80) ? "dis" : " en",
229 (c1&0x80) ? "dis" : " en");
230 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
231 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
232 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
233 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
234
235 p += sprintf(p, "UDMA\n");
236 p += sprintf(p, "DMA\n");
237 p += sprintf(p, "PIO\n");
238
239 return p-buffer;/* => must be less than 4k! */
240 }
241 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
242
243 byte hpt366_proc = 0;
244
245 extern char *ide_xfer_verbose (byte xfer_rate);
246 byte hpt363_shared_irq;
247 byte hpt363_shared_pin;
248
249 static unsigned int pci_rev_check_hpt3xx (struct pci_dev *dev)
250 {
251 unsigned int class_rev;
252 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
253 class_rev &= 0xff;
254 return ((int) (class_rev > 0x02) ? 1 : 0);
255 }
256
257 static unsigned int pci_rev2_check_hpt3xx (struct pci_dev *dev)
258 {
259 unsigned int class_rev;
260 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
261 class_rev &= 0xff;
262 return ((int) (class_rev > 0x01) ? 1 : 0);
263 }
264
265 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
266 {
267 struct hd_driveid *id = drive->id;
268
269 if (quirk_drives == list) {
270 while (*list) {
271 if (strstr(id->model, *list++)) {
272 return 1;
273 }
274 }
275 } else {
276 while (*list) {
277 if (!strcmp(*list++,id->model)) {
278 return 1;
279 }
280 }
281 }
282 return 0;
283 }
284
285 static unsigned int pci_bus_clock_list (byte speed, int direction, struct chipset_bus_clock_list_entry * chipset_table)
286 {
287 for ( ; chipset_table->xfer_speed ; chipset_table++)
288 if (chipset_table->xfer_speed == speed) {
289 return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
290 }
291 return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
292 }
293
294 static void hpt366_tune_chipset (ide_drive_t *drive, byte speed, int direction)
295 {
296 byte regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
297 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
298 /*
299 * since the channel is always 0 it does not matter.
300 */
301
302 unsigned int reg1 = 0;
303 unsigned int reg2 = 0;
304 byte drive_fast = 0;
305
306 /*
307 * Disable the "fast interrupt" prediction.
308 */
309 pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
310 if (drive_fast & 0x02)
311 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x20);
312
313 pci_read_config_dword(HWIF(drive)->pci_dev, regtime, ®1);
314 /* detect bus speed by looking at control reg timing: */
315 switch((reg1 >> 8) & 7) {
316 case 5:
317 reg2 = pci_bus_clock_list(speed, direction, forty_base);
318 break;
319 case 9:
320 reg2 = pci_bus_clock_list(speed, direction, twenty_five_base);
321 break;
322 default:
323 case 7:
324 reg2 = pci_bus_clock_list(speed, direction, thirty_three_base);
325 break;
326 }
327 /*
328 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
329 */
330 if (speed >= XFER_MW_DMA_0) {
331 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
332 } else {
333 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
334 }
335 reg2 &= ~0x80000000;
336
337 pci_write_config_dword(HWIF(drive)->pci_dev, regtime, reg2);
338 }
339
340 static void hpt370_tune_chipset (ide_drive_t *drive, byte speed, int direction)
341 {
342 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
343 byte reg5bh = (speed != XFER_UDMA_5) ? 0x22 : (direction) ? 0x20 : 0x22;
344 unsigned int list_conf = pci_bus_clock_list(speed, direction, thirty_three_base_hpt370);
345 unsigned int drive_conf = 0;
346 unsigned int conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
347 byte drive_pci = 0;
348 byte drive_fast = 0;
349
350 switch (drive->dn) {
351 case 0: drive_pci = 0x40; break;
352 case 1: drive_pci = 0x44; break;
353 case 2: drive_pci = 0x48; break;
354 case 3: drive_pci = 0x4c; break;
355 default: return;
356 }
357 /*
358 * Disable the "fast interrupt" prediction.
359 */
360 pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
361 if (drive_fast & 0x80)
362 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x80);
363
364 pci_read_config_dword(HWIF(drive)->pci_dev, drive_pci, &drive_conf);
365 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5b, reg5bh);
366
367 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
368 /*
369 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
370 */
371 list_conf &= ~0x80000000;
372
373 pci_write_config_dword(HWIF(drive)->pci_dev, drive_pci, list_conf);
374 }
375
376 static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed)
377 {
378 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
379 return -1;
380
381 if (!drive->init_speed)
382 drive->init_speed = speed;
383
384 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
385 hpt370_tune_chipset(drive, speed, 0);
386 } else {
387 hpt366_tune_chipset(drive, speed, 0);
388 }
389 drive->current_speed = speed;
390 return ((int) ide_config_drive_speed(drive, speed));
391 }
392
393 static void config_chipset_for_pio (ide_drive_t *drive)
394 {
395 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
396 unsigned short xfer_pio = drive->id->eide_pio_modes;
397 byte timing, speed, pio;
398
399 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
400
401 if (xfer_pio> 4)
402 xfer_pio = 0;
403
404 if (drive->id->eide_pio_iordy > 0) {
405 for (xfer_pio = 5;
406 xfer_pio>0 &&
407 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
408 xfer_pio--);
409 } else {
410 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
411 (drive->id->eide_pio_modes & 2) ? 0x04 :
412 (drive->id->eide_pio_modes & 1) ? 0x03 :
413 (drive->id->tPIO & 2) ? 0x02 :
414 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
415 }
416
417 timing = (xfer_pio >= pio) ? xfer_pio : pio;
418
419 switch(timing) {
420 case 4: speed = XFER_PIO_4;break;
421 case 3: speed = XFER_PIO_3;break;
422 case 2: speed = XFER_PIO_2;break;
423 case 1: speed = XFER_PIO_1;break;
424 default:
425 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
426 break;
427 }
428 (void) hpt3xx_tune_chipset(drive, speed);
429 }
430
431 static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio)
432 {
433 byte speed;
434 switch(pio) {
435 case 4: speed = XFER_PIO_4;break;
436 case 3: speed = XFER_PIO_3;break;
437 case 2: speed = XFER_PIO_2;break;
438 case 1: speed = XFER_PIO_1;break;
439 default: speed = XFER_PIO_0;break;
440 }
441 (void) hpt3xx_tune_chipset(drive, speed);
442 }
443
444 #ifdef CONFIG_BLK_DEV_IDEDMA
445 /*
446 * This allows the configuration of ide_pci chipset registers
447 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
448 * after the drive is reported by the OS. Initally for designed for
449 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
450 *
451 * check_in_drive_lists(drive, bad_ata66_4)
452 * check_in_drive_lists(drive, bad_ata66_3)
453 * check_in_drive_lists(drive, bad_ata33)
454 *
455 */
456 static int config_chipset_for_dma (ide_drive_t *drive)
457 {
458 struct hd_driveid *id = drive->id;
459 byte speed = 0x00;
460 byte ultra66 = eighty_ninty_three(drive);
461 int rval;
462
463 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
464 return ((int) ide_dma_off_quietly);
465
466 if ((id->dma_ultra & 0x0020) &&
467 (!check_in_drive_lists(drive, bad_ata100_5)) &&
468 (HPT370_ALLOW_ATA100_5) &&
469 (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) &&
470 (ultra66)) {
471 speed = XFER_UDMA_5;
472 } else if ((id->dma_ultra & 0x0010) &&
473 (!check_in_drive_lists(drive, bad_ata66_4)) &&
474 (HPT366_ALLOW_ATA66_4) &&
475 (ultra66)) {
476 speed = XFER_UDMA_4;
477 } else if ((id->dma_ultra & 0x0008) &&
478 (!check_in_drive_lists(drive, bad_ata66_3)) &&
479 (HPT366_ALLOW_ATA66_3) &&
480 (ultra66)) {
481 speed = XFER_UDMA_3;
482 } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) {
483 if (id->dma_ultra & 0x0004) {
484 speed = XFER_UDMA_2;
485 } else if (id->dma_ultra & 0x0002) {
486 speed = XFER_UDMA_1;
487 } else if (id->dma_ultra & 0x0001) {
488 speed = XFER_UDMA_0;
489 }
490 } else if (id->dma_mword & 0x0004) {
491 speed = XFER_MW_DMA_2;
492 } else if (id->dma_mword & 0x0002) {
493 speed = XFER_MW_DMA_1;
494 } else if (id->dma_mword & 0x0001) {
495 speed = XFER_MW_DMA_0;
496 } else {
497 return ((int) ide_dma_off_quietly);
498 }
499
500 (void) hpt3xx_tune_chipset(drive, speed);
501
502 rval = (int)( ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
503 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
504 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
505 ide_dma_off_quietly);
506 return rval;
507 }
508
509 int hpt3xx_quirkproc (ide_drive_t *drive)
510 {
511 return ((int) check_in_drive_lists(drive, quirk_drives));
512 }
513
514 void hpt3xx_intrproc (ide_drive_t *drive)
515 {
516 if (drive->quirk_list) {
517 /* drives in the quirk_list may not like intr setups/cleanups */
518 } else {
519 OUT_BYTE((drive)->ctl|2, HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]);
520 }
521 }
522
523 void hpt3xx_maskproc (ide_drive_t *drive, int mask)
524 {
525 if (drive->quirk_list) {
526 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
527 byte reg5a = 0;
528 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5a);
529 if (((reg5a & 0x10) >> 4) != mask)
530 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
531 } else {
532 if (mask) {
533 disable_irq(HWIF(drive)->irq);
534 } else {
535 enable_irq(HWIF(drive)->irq);
536 }
537 }
538 } else {
539 if (IDE_CONTROL_REG)
540 OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG);
541 }
542 }
543
544 void hpt370_rw_proc (ide_drive_t *drive, ide_dma_action_t func)
545 {
546 if ((func != ide_dma_write) || (func != ide_dma_read))
547 return;
548 hpt370_tune_chipset(drive, drive->current_speed, (func == ide_dma_write));
549 }
550
551 static int config_drive_xfer_rate (ide_drive_t *drive)
552 {
553 struct hd_driveid *id = drive->id;
554 ide_dma_action_t dma_func = ide_dma_on;
555
556 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
557 /* Consult the list of known "bad" drives */
558 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
559 dma_func = ide_dma_off;
560 goto fast_ata_pio;
561 }
562 dma_func = ide_dma_off_quietly;
563 if (id->field_valid & 4) {
564 if (id->dma_ultra & 0x002F) {
565 /* Force if Capable UltraDMA */
566 dma_func = config_chipset_for_dma(drive);
567 if ((id->field_valid & 2) &&
568 (dma_func != ide_dma_on))
569 goto try_dma_modes;
570 }
571 } else if (id->field_valid & 2) {
572 try_dma_modes:
573 if (id->dma_mword & 0x0007) {
574 /* Force if Capable regular DMA modes */
575 dma_func = config_chipset_for_dma(drive);
576 if (dma_func != ide_dma_on)
577 goto no_dma_set;
578 }
579 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
580 if (id->eide_dma_time > 150) {
581 goto no_dma_set;
582 }
583 /* Consult the list of known "good" drives */
584 dma_func = config_chipset_for_dma(drive);
585 if (dma_func != ide_dma_on)
586 goto no_dma_set;
587 } else {
588 goto fast_ata_pio;
589 }
590 } else if ((id->capability & 8) || (id->field_valid & 2)) {
591 fast_ata_pio:
592 dma_func = ide_dma_off_quietly;
593 no_dma_set:
594
595 config_chipset_for_pio(drive);
596 }
597 return HWIF(drive)->dmaproc(dma_func, drive);
598 }
599
600 /*
601 * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
602 *
603 * This is specific to the HPT366 UDMA bios chipset
604 * by HighPoint|Triones Technologies, Inc.
605 */
606 int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
607 {
608 byte reg50h = 0, reg52h = 0, reg5ah = 0, dma_stat = 0;
609 unsigned long dma_base = HWIF(drive)->dma_base;
610
611 switch (func) {
612 case ide_dma_check:
613 return config_drive_xfer_rate(drive);
614 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */
615 dma_stat = inb(dma_base+2);
616 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
617 case ide_dma_lostirq:
618 pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, ®50h);
619 pci_read_config_byte(HWIF(drive)->pci_dev, 0x52, ®52h);
620 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5ah);
621 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
622 drive->name,
623 ide_dmafunc_verbose(func),
624 reg50h, reg52h, reg5ah);
625 if (reg5ah & 0x10)
626 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, reg5ah & ~0x10);
627 break;
628 case ide_dma_timeout:
629 default:
630 break;
631 }
632 return ide_dmaproc(func, drive); /* use standard DMA stuff */
633 }
634
635 int hpt370_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
636 {
637 switch (func) {
638 case ide_dma_check:
639 return config_drive_xfer_rate(drive);
640 default:
641 break;
642 }
643 return ide_dmaproc(func, drive); /* use standard DMA stuff */
644 }
645 #endif /* CONFIG_BLK_DEV_IDEDMA */
646
647 unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name)
648 {
649 byte test = 0;
650
651 if (dev->resource[PCI_ROM_RESOURCE].start)
652 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
653
654 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
655
656 #if 0
657 if (test != 0x08)
658 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x08);
659 #else
660 if (test != (L1_CACHE_BYTES / 4))
661 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
662 #endif
663
664 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
665 if (test != 0x78)
666 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
667
668 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
669 if (test != 0x08)
670 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
671
672 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
673 if (test != 0x08)
674 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
675
676 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
677 if (!hpt366_proc) {
678 hpt366_proc = 1;
679 bmide_dev = dev;
680 if (pci_rev_check_hpt3xx(dev))
681 bmide2_dev = dev;
682 hpt366_display_info = &hpt366_get_info;
683 }
684 if ((hpt366_proc) && ((dev->devfn - bmide_dev->devfn) == 1)) {
685 bmide2_dev = dev;
686 }
687 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
688
689 return dev->irq;
690 }
691
692 unsigned int __init ata66_hpt366 (ide_hwif_t *hwif)
693 {
694 byte ata66 = 0;
695
696 pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
697 #ifdef DEBUG
698 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
699 ata66, (ata66 & 0x02) ? "33" : "66",
700 PCI_FUNC(hwif->pci_dev->devfn));
701 #endif /* DEBUG */
702 return ((ata66 & 0x02) ? 0 : 1);
703 }
704
705 void __init ide_init_hpt366 (ide_hwif_t *hwif)
706 {
707 hwif->tuneproc = &hpt3xx_tune_drive;
708 hwif->speedproc = &hpt3xx_tune_chipset;
709 hwif->quirkproc = &hpt3xx_quirkproc;
710 hwif->intrproc = &hpt3xx_intrproc;
711 hwif->maskproc = &hpt3xx_maskproc;
712
713 if (pci_rev2_check_hpt3xx(hwif->pci_dev)) {
714 /* do nothing now but will split device types */
715 }
716
717 #ifdef CONFIG_BLK_DEV_IDEDMA
718 if (hwif->dma_base) {
719 if (pci_rev_check_hpt3xx(hwif->pci_dev)) {
720 byte reg5ah = 0;
721 pci_read_config_byte(hwif->pci_dev, 0x5a, ®5ah);
722 if (reg5ah & 0x10) /* interrupt force enable */
723 pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10);
724 hwif->dmaproc = &hpt370_dmaproc;
725 hwif->rwproc = &hpt370_rw_proc;
726 } else {
727 hwif->dmaproc = &hpt366_dmaproc;
728 }
729 if (!noautodma)
730 hwif->autodma = 1;
731 else
732 hwif->autodma = 0;
733 } else {
734 hwif->autodma = 0;
735 hwif->drives[0].autotune = 1;
736 hwif->drives[1].autotune = 1;
737 }
738 #else /* !CONFIG_BLK_DEV_IDEDMA */
739 hwif->drives[0].autotune = 1;
740 hwif->drives[1].autotune = 1;
741 hwif->autodma = 0;
742 #endif /* CONFIG_BLK_DEV_IDEDMA */
743 }
744
745 void __init ide_dmacapable_hpt366 (ide_hwif_t *hwif, unsigned long dmabase)
746 {
747 byte masterdma = 0, slavedma = 0;
748 byte dma_new = 0, dma_old = inb(dmabase+2);
749 byte primary = hwif->channel ? 0x4b : 0x43;
750 byte secondary = hwif->channel ? 0x4f : 0x47;
751 unsigned long flags;
752
753 __save_flags(flags); /* local CPU only */
754 __cli(); /* local CPU only */
755
756 dma_new = dma_old;
757 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
758 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
759
760 if (masterdma & 0x30) dma_new |= 0x20;
761 if (slavedma & 0x30) dma_new |= 0x40;
762 if (dma_new != dma_old) outb(dma_new, dmabase+2);
763
764 __restore_flags(flags); /* local CPU only */
765
766 ide_setup_dma(hwif, dmabase, 8);
767 }
768