File: /usr/src/linux/drivers/ide/ide-pmac.c
1 /*
2 * linux/drivers/ide/ide-pmac.c Version ?.?? Mar. 18, 2000
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998 Paul Mackerras.
9 *
10 * Bits from Benjamin Herrenschmidt
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 *
17 * Some code taken from drivers/ide/ide-dma.c:
18 *
19 * Copyright (c) 1995-1998 Mark Lord
20 *
21 */
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/ide.h>
29
30 #include <asm/prom.h>
31 #include <asm/io.h>
32 #include <asm/dbdma.h>
33 #include <asm/ide.h>
34 #include <asm/mediabay.h>
35 #include <asm/feature.h>
36 #ifdef CONFIG_PMAC_PBOOK
37 #include <linux/adb.h>
38 #include <linux/pmu.h>
39 #include <asm/irq.h>
40 #endif
41 #include "ide_modes.h"
42
43 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
44
45 #undef IDE_PMAC_DEBUG
46
47 #define IDE_SYSCLK_NS 30
48 #define IDE_SYSCLK_ULTRA_PS 0x1d4c /* (15 * 1000 / 2)*/
49
50 struct pmac_ide_hwif {
51 ide_ioreg_t regbase;
52 int irq;
53 int kind;
54 int aapl_bus_id;
55 struct device_node* node;
56 u32 timings[2];
57 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
58 volatile struct dbdma_regs* dma_regs;
59 struct dbdma_cmd* dma_table;
60 #endif
61
62 } pmac_ide[MAX_HWIFS];
63
64 static int pmac_ide_count;
65
66 enum {
67 controller_ohare, /* OHare based */
68 controller_heathrow, /* Heathrow/Paddington */
69 controller_kl_ata3, /* KeyLargo ATA-3 */
70 controller_kl_ata4 /* KeyLargo ATA-4 */
71 };
72
73
74 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
75
76 typedef struct {
77 int accessTime;
78 int cycleTime;
79 } pmac_ide_timing;
80
81 /* Multiword DMA timings */
82 static pmac_ide_timing mdma_timings[] =
83 {
84 { 215, 480 }, /* Mode 0 */
85 { 80, 150 }, /* 1 */
86 { 70, 120 } /* 2 */
87 };
88
89 /* Ultra DMA timings (for use when I know how to calculate them */
90 static pmac_ide_timing udma_timings[] =
91 {
92 { 0, 114 }, /* Mode 0 */
93 { 0, 75 }, /* 1 */
94 { 0, 55 }, /* 2 */
95 { 100, 45 }, /* 3 */
96 { 100, 25 } /* 4 */
97 };
98
99 /* allow up to 256 DBDMA commands per xfer */
100 #define MAX_DCMDS 256
101
102 /* Wait 1.5s for disk to answer on IDE bus after
103 * enable operation.
104 * NOTE: There is at least one case I know of a disk that needs about 10sec
105 * before anwering on the bus. I beleive we could add a kernel command
106 * line arg to override this delay for such cases.
107 */
108 #define IDE_WAKEUP_DELAY_MS 1500
109
110 static void pmac_ide_setup_dma(struct device_node *np, int ix);
111 static int pmac_ide_dmaproc(ide_dma_action_t func, ide_drive_t *drive);
112 static int pmac_ide_build_dmatable(ide_drive_t *drive, int ix, int wr);
113 static int pmac_ide_tune_chipset(ide_drive_t *drive, byte speed);
114 static void pmac_ide_tuneproc(ide_drive_t *drive, byte pio);
115 static void pmac_ide_selectproc(ide_drive_t *drive);
116
117 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
118
119 #ifdef CONFIG_PMAC_PBOOK
120 static int idepmac_notify_sleep(struct pmu_sleep_notifier *self, int when);
121 struct pmu_sleep_notifier idepmac_sleep_notifier = {
122 idepmac_notify_sleep, SLEEP_LEVEL_BLOCK,
123 };
124 #endif /* CONFIG_PMAC_PBOOK */
125
126 static int
127 pmac_ide_find(ide_drive_t *drive)
128 {
129 ide_hwif_t *hwif = HWIF(drive);
130 ide_ioreg_t base;
131 int i;
132
133 for (i=0; i<pmac_ide_count; i++) {
134 base = pmac_ide[i].regbase;
135 if (base && base == hwif->io_ports[0])
136 return i;
137 }
138 return -1;
139 }
140
141 /*
142 * N.B. this can't be an initfunc, because the media-bay task can
143 * call ide_[un]register at any time.
144 */
145 void pmac_ide_init_hwif_ports(hw_regs_t *hw,
146 ide_ioreg_t data_port, ide_ioreg_t ctrl_port,
147 int *irq)
148 {
149 int i, ix;
150
151 if (data_port == 0)
152 return;
153
154 for (ix = 0; ix < MAX_HWIFS; ++ix)
155 if (data_port == pmac_ide[ix].regbase)
156 break;
157
158 if (ix >= MAX_HWIFS) {
159 /* Probably a PCI interface... */
160 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
161 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
162 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
163 return;
164 }
165
166 for (i = 0; i < 8; ++i)
167 hw->io_ports[i] = data_port + i * 0x10;
168 hw->io_ports[8] = data_port + 0x160;
169
170 if (irq != NULL)
171 *irq = pmac_ide[ix].irq;
172
173 ide_hwifs[ix].tuneproc = pmac_ide_tuneproc;
174 ide_hwifs[ix].selectproc = pmac_ide_selectproc;
175 ide_hwifs[ix].speedproc = &pmac_ide_tune_chipset;
176 if (pmac_ide[ix].dma_regs && pmac_ide[ix].dma_table) {
177 ide_hwifs[ix].dmaproc = &pmac_ide_dmaproc;
178 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO
179 if (!noautodma)
180 ide_hwifs[ix].autodma = 1;
181 #endif
182 }
183 }
184
185 #if 0
186 /* This one could be later extended to handle CMD IDE and be used by some kind
187 * of /proc interface. I want to be able to get the devicetree path of a block
188 * device for yaboot configuration
189 */
190 struct device_node*
191 pmac_ide_get_devnode(ide_drive_t *drive)
192 {
193 int i = pmac_ide_find(drive);
194 if (i < 0)
195 return NULL;
196 return pmac_ide[i].node;
197 }
198 #endif
199
200 /* Setup timings for the selected drive (master/slave). I still need to verify if this
201 * is enough, I beleive selectproc will be called whenever an IDE command is started,
202 * but... */
203 static void
204 pmac_ide_selectproc(ide_drive_t *drive)
205 {
206 int i = pmac_ide_find(drive);
207 if (i < 0)
208 return;
209
210 if (drive->select.all & 0x10)
211 out_le32((unsigned *)(IDE_DATA_REG + 0x200 + _IO_BASE), pmac_ide[i].timings[1]);
212 else
213 out_le32((unsigned *)(IDE_DATA_REG + 0x200 + _IO_BASE), pmac_ide[i].timings[0]);
214 }
215
216 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
217 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
218 #define SYSCLK_TICKS_UDMA(t) (((t) + IDE_SYSCLK_ULTRA_PS - 1) / IDE_SYSCLK_ULTRA_PS)
219
220 static __inline__ int
221 wait_for_ready(ide_drive_t *drive)
222 {
223 /* Timeout bumped for some powerbooks */
224 int timeout = 2000;
225 byte stat;
226
227 while(--timeout) {
228 stat = GET_STAT();
229 if(!(stat & BUSY_STAT)) {
230 if (drive->ready_stat == 0)
231 break;
232 else if((stat & drive->ready_stat) || (stat & ERR_STAT))
233 break;
234 }
235 mdelay(1);
236 }
237 if((stat & ERR_STAT) || timeout <= 0) {
238 if (stat & ERR_STAT) {
239 printk("ide_pmace: wait_for_ready, error status: %x\n", stat);
240 }
241 return 1;
242 }
243 return 0;
244 }
245
246 static int
247 pmac_ide_do_setfeature(ide_drive_t *drive, byte command)
248 {
249 unsigned long flags;
250 int result = 1;
251
252 save_flags(flags);
253 cli();
254 udelay(1);
255 SELECT_DRIVE(HWIF(drive), drive);
256 SELECT_MASK(HWIF(drive), drive, 0);
257 udelay(1);
258 if(wait_for_ready(drive)) {
259 printk("pmac_ide_do_setfeature disk not ready before SET_FEATURE!\n");
260 goto out;
261 }
262 OUT_BYTE(SETFEATURES_XFER, IDE_FEATURE_REG);
263 OUT_BYTE(command, IDE_NSECTOR_REG);
264 OUT_BYTE(WIN_SETFEATURES, IDE_COMMAND_REG);
265 udelay(1);
266 result = wait_for_ready(drive);
267 if (result)
268 printk("pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");
269 out:
270 restore_flags(flags);
271
272 return result;
273 }
274
275 /* Calculate PIO timings */
276 static void
277 pmac_ide_tuneproc(ide_drive_t *drive, byte pio)
278 {
279 ide_pio_data_t d;
280 int i;
281 u32 *timings;
282 int accessTicks, recTicks;
283
284 i = pmac_ide_find(drive);
285 if (i < 0)
286 return;
287
288 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
289 accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
290 if (drive->select.all & 0x10)
291 timings = &pmac_ide[i].timings[1];
292 else
293 timings = &pmac_ide[i].timings[0];
294
295 if (pmac_ide[i].kind == controller_kl_ata4) {
296 /* The "ata-4" IDE controller of Core99 machines */
297 accessTicks = SYSCLK_TICKS_UDMA(ide_pio_timings[pio].active_time * 1000);
298 recTicks = SYSCLK_TICKS_UDMA(d.cycle_time * 1000) - accessTicks;
299
300 *timings = ((*timings) & 0x1FFFFFC00) | accessTicks | (recTicks << 5);
301 } else {
302 /* The old "ata-3" IDE controller */
303 accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
304 if (accessTicks < 4)
305 accessTicks = 4;
306 recTicks = SYSCLK_TICKS(d.cycle_time) - accessTicks - 4;
307 if (recTicks < 1)
308 recTicks = 1;
309
310 *timings = ((*timings) & 0xFFFFFF800) | accessTicks | (recTicks << 5);
311 }
312
313 #ifdef IDE_PMAC_DEBUG
314 printk("ide_pmac: Set PIO timing for mode %d, reg: 0x%08x\n",
315 pio, *timings);
316 #endif
317
318 if (drive->select.all == IN_BYTE(IDE_SELECT_REG))
319 pmac_ide_selectproc(drive);
320 }
321
322 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
323 static int
324 set_timings_udma(int intf, u32 *timings, byte speed)
325 {
326 int cycleTime, accessTime;
327 int rdyToPauseTicks, cycleTicks;
328
329 if (pmac_ide[intf].kind != controller_kl_ata4)
330 return 1;
331
332 cycleTime = udma_timings[speed & 0xf].cycleTime;
333 accessTime = udma_timings[speed & 0xf].accessTime;
334
335 rdyToPauseTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
336 cycleTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000);
337
338 *timings = ((*timings) & 0xe00fffff) |
339 ((cycleTicks << 1) | (rdyToPauseTicks << 5) | 1) << 20;
340
341 return 0;
342 }
343
344 static int
345 set_timings_mdma(int intf, u32 *timings, byte speed)
346 {
347 int cycleTime, accessTime;
348 int accessTicks, recTicks;
349
350 /* Calculate accesstime and cycle time */
351 cycleTime = mdma_timings[speed & 0xf].cycleTime;
352 accessTime = mdma_timings[speed & 0xf].accessTime;
353 if ((pmac_ide[intf].kind == controller_ohare) && (cycleTime < 150))
354 cycleTime = 150;
355
356 /* For ata-4 controller */
357 if (pmac_ide[intf].kind == controller_kl_ata4) {
358 accessTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
359 recTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000) - accessTicks;
360 *timings = ((*timings) & 0xffe003ff) |
361 (accessTicks | (recTicks << 5)) << 10;
362 } else {
363 int halfTick = 0;
364 int origAccessTime = accessTime;
365 int origCycleTime = cycleTime;
366
367 accessTicks = SYSCLK_TICKS(accessTime);
368 if (accessTicks < 1)
369 accessTicks = 1;
370 accessTime = accessTicks * IDE_SYSCLK_NS;
371 recTicks = SYSCLK_TICKS(cycleTime - accessTime) - 1;
372 if (recTicks < 1)
373 recTicks = 1;
374 cycleTime = (recTicks + 1 + accessTicks) * IDE_SYSCLK_NS;
375
376 /* KeyLargo ata-3 don't support the half-tick stuff */
377 if ((pmac_ide[intf].kind != controller_kl_ata3) &&
378 (accessTicks > 1) &&
379 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
380 ((cycleTime - IDE_SYSCLK_NS) >= origCycleTime)) {
381 halfTick = 1;
382 accessTicks--;
383 }
384 *timings = ((*timings) & 0x7FF) |
385 (accessTicks | (recTicks << 5) | (halfTick << 10)) << 11;
386 }
387 return 0;
388 }
389 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
390
391 /* You may notice we don't use this function on normal operation,
392 * our, normal mdma function is supposed to be more precise
393 */
394 static int
395 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
396 {
397 int intf = pmac_ide_find(drive);
398 int unit = (drive->select.all & 0x10) ? 1:0;
399 int ret = 0;
400 u32 *timings;
401
402 if (intf < 0)
403 return 1;
404
405 timings = &pmac_ide[intf].timings[unit];
406
407 switch(speed) {
408 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
409 case XFER_UDMA_4:
410 case XFER_UDMA_3:
411 case XFER_UDMA_2:
412 case XFER_UDMA_1:
413 case XFER_UDMA_0:
414 ret = set_timings_udma(intf, timings, speed);
415 break;
416 case XFER_MW_DMA_2:
417 case XFER_MW_DMA_1:
418 case XFER_MW_DMA_0:
419 case XFER_SW_DMA_2:
420 case XFER_SW_DMA_1:
421 case XFER_SW_DMA_0:
422 ret = set_timings_mdma(intf, timings, speed);
423 break;
424 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
425 case XFER_PIO_4:
426 case XFER_PIO_3:
427 case XFER_PIO_2:
428 case XFER_PIO_1:
429 case XFER_PIO_0:
430 pmac_ide_tuneproc(drive, speed & 0x07);
431 break;
432 default:
433 ret = 1;
434 }
435 if (ret)
436 return ret;
437
438 ret = pmac_ide_do_setfeature(drive, speed);
439 if (ret)
440 return ret;
441
442 pmac_ide_selectproc(drive);
443 drive->current_speed = speed;
444
445 return 0;
446 }
447
448 ide_ioreg_t
449 pmac_ide_get_base(int index)
450 {
451 return pmac_ide[index].regbase;
452 }
453
454 int
455 pmac_ide_get_irq(ide_ioreg_t base)
456 {
457 int ix;
458
459 for (ix = 0; ix < MAX_HWIFS; ++ix)
460 if (base == pmac_ide[ix].regbase)
461 return pmac_ide[ix].irq;
462 return 0;
463 }
464
465 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
466
467 kdev_t __init
468 pmac_find_ide_boot(char *bootdevice, int n)
469 {
470 int i;
471
472 /*
473 * Look through the list of IDE interfaces for this one.
474 */
475 for (i = 0; i < pmac_ide_count; ++i) {
476 char *name;
477 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
478 continue;
479 name = pmac_ide[i].node->full_name;
480 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
481 /* XXX should cope with the 2nd drive as well... */
482 return MKDEV(ide_majors[i], 0);
483 }
484 }
485
486 return 0;
487 }
488
489 void __init
490 pmac_ide_probe(void)
491 {
492 struct device_node *np;
493 int i;
494 struct device_node *atas;
495 struct device_node *p, **pp, *removables, **rp;
496 unsigned long base;
497 int irq, big_delay;
498 ide_hwif_t *hwif;
499
500 if (_machine != _MACH_Pmac)
501 return;
502 pp = &atas;
503 rp = &removables;
504 p = find_devices("ATA");
505 if (p == NULL)
506 p = find_devices("IDE");
507 if (p == NULL)
508 p = find_type_devices("ide");
509 if (p == NULL)
510 p = find_type_devices("ata");
511 /* Move removable devices such as the media-bay CDROM
512 on the PB3400 to the end of the list. */
513 for (; p != NULL; p = p->next) {
514 if (p->parent && p->parent->type
515 && strcasecmp(p->parent->type, "media-bay") == 0) {
516 *rp = p;
517 rp = &p->next;
518 } else {
519 *pp = p;
520 pp = &p->next;
521 }
522 }
523 *rp = NULL;
524 *pp = removables;
525 big_delay = 0;
526
527 for (i = 0, np = atas; i < MAX_HWIFS && np != NULL; np = np->next) {
528 struct device_node *tp;
529 int *bidp;
530 int in_bay = 0;
531
532 /*
533 * If this node is not under a mac-io or dbdma node,
534 * leave it to the generic PCI driver.
535 */
536 for (tp = np->parent; tp != 0; tp = tp->parent)
537 if (tp->type && (strcmp(tp->type, "mac-io") == 0
538 || strcmp(tp->type, "dbdma") == 0))
539 break;
540 if (tp == 0)
541 continue;
542
543 if (np->n_addrs == 0) {
544 printk(KERN_WARNING "ide: no address for device %s\n",
545 np->full_name);
546 continue;
547 }
548
549 /*
550 * If this slot is taken (e.g. by ide-pci.c) try the next one.
551 */
552 while (i < MAX_HWIFS
553 && ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0)
554 ++i;
555 if (i >= MAX_HWIFS)
556 break;
557
558 base = (unsigned long) ioremap(np->addrs[0].address, 0x200) - _IO_BASE;
559
560 /* XXX This is bogus. Should be fixed in the registry by checking
561 the kind of host interrupt controller, a bit like gatwick
562 fixes in irq.c
563 */
564 if (np->n_intrs == 0) {
565 printk("ide: no intrs for device %s, using 13\n",
566 np->full_name);
567 irq = 13;
568 } else {
569 irq = np->intrs[0].line;
570 }
571 pmac_ide[i].regbase = base;
572 pmac_ide[i].irq = irq;
573 pmac_ide[i].node = np;
574 if (device_is_compatible(np, "keylargo-ata")) {
575 if (strcmp(np->name, "ata-4") == 0)
576 pmac_ide[i].kind = controller_kl_ata4;
577 else
578 pmac_ide[i].kind = controller_kl_ata3;
579 } else if (device_is_compatible(np, "heathrow-ata"))
580 pmac_ide[i].kind = controller_heathrow;
581 else
582 pmac_ide[i].kind = controller_ohare;
583
584 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
585 pmac_ide[i].aapl_bus_id = bidp ? *bidp : 0;
586
587 if (np->parent && np->parent->name
588 && strcasecmp(np->parent->name, "media-bay") == 0) {
589 #ifdef CONFIG_PMAC_PBOOK
590 media_bay_set_ide_infos(np->parent,base,irq,i);
591 #endif /* CONFIG_PMAC_PBOOK */
592 in_bay = 1;
593 } else if (pmac_ide[i].kind == controller_ohare) {
594 /* The code below is having trouble on some ohare machines
595 * (timing related ?). Until I can put my hand on one of these
596 * units, I keep the old way
597 */
598 feature_set(np, FEATURE_IDE0_enable);
599 } else {
600 /* This is necessary to enable IDE when net-booting */
601 printk("pmac_ide: enabling IDE bus ID %d\n",
602 pmac_ide[i].aapl_bus_id);
603 switch(pmac_ide[i].aapl_bus_id) {
604 case 0:
605 feature_set(np, FEATURE_IDE0_reset);
606 mdelay(10);
607 feature_set(np, FEATURE_IDE0_enable);
608 mdelay(10);
609 feature_clear(np, FEATURE_IDE0_reset);
610 break;
611 case 1:
612 feature_set(np, FEATURE_IDE1_reset);
613 mdelay(10);
614 feature_set(np, FEATURE_IDE1_enable);
615 mdelay(10);
616 feature_clear(np, FEATURE_IDE1_reset);
617 break;
618 case 2:
619 /* This one exists only for KL, I don't know
620 about any enable bit */
621 feature_set(np, FEATURE_IDE2_reset);
622 mdelay(10);
623 feature_clear(np, FEATURE_IDE2_reset);
624 break;
625 }
626 big_delay = 1;
627 }
628
629 hwif = &ide_hwifs[i];
630 pmac_ide_init_hwif_ports(&hwif->hw, base, 0, &hwif->irq);
631 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
632 hwif->chipset = ide_pmac;
633 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || in_bay;
634 #ifdef CONFIG_PMAC_PBOOK
635 if (in_bay && check_media_bay_by_base(base, MB_CD) == 0)
636 hwif->noprobe = 0;
637 #endif /* CONFIG_PMAC_PBOOK */
638
639 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
640 if (np->n_addrs >= 2) {
641 /* has a DBDMA controller channel */
642 pmac_ide_setup_dma(np, i);
643 }
644 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
645
646 ++i;
647 }
648 pmac_ide_count = i;
649 if (big_delay)
650 mdelay(IDE_WAKEUP_DELAY_MS);
651
652 #ifdef CONFIG_PMAC_PBOOK
653 pmu_register_sleep_notifier(&idepmac_sleep_notifier);
654 #endif /* CONFIG_PMAC_PBOOK */
655 }
656
657 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
658
659 static void __init
660 pmac_ide_setup_dma(struct device_node *np, int ix)
661 {
662 pmac_ide[ix].dma_regs =
663 (volatile struct dbdma_regs*)ioremap(np->addrs[1].address, 0x200);
664
665 /*
666 * Allocate space for the DBDMA commands.
667 * The +2 is +1 for the stop command and +1 to allow for
668 * aligning the start address to a multiple of 16 bytes.
669 */
670 pmac_ide[ix].dma_table = (struct dbdma_cmd*)
671 kmalloc((MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), GFP_KERNEL);
672 if (pmac_ide[ix].dma_table == 0) {
673 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
674 ide_hwifs[ix].name);
675 return;
676 }
677
678 ide_hwifs[ix].dmaproc = &pmac_ide_dmaproc;
679 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO
680 if (!noautodma)
681 ide_hwifs[ix].autodma = 1;
682 #endif
683 }
684
685 /*
686 * pmac_ide_build_dmatable builds the DBDMA command list
687 * for a transfer and sets the DBDMA channel to point to it.
688 */
689 static int
690 pmac_ide_build_dmatable(ide_drive_t *drive, int ix, int wr)
691 {
692 struct dbdma_cmd *table, *tstart;
693 int count = 0;
694 struct request *rq = HWGROUP(drive)->rq;
695 struct buffer_head *bh = rq->bh;
696 unsigned int size, addr;
697 volatile struct dbdma_regs *dma = pmac_ide[ix].dma_regs;
698
699 table = tstart = (struct dbdma_cmd *) DBDMA_ALIGN(pmac_ide[ix].dma_table);
700 out_le32(&dma->control, (RUN|PAUSE|FLUSH|WAKE|DEAD) << 16);
701 while (in_le32(&dma->status) & RUN)
702 udelay(1);
703
704 do {
705 /*
706 * Determine addr and size of next buffer area. We assume that
707 * individual virtual buffers are always composed linearly in
708 * physical memory. For example, we assume that any 8kB buffer
709 * is always composed of two adjacent physical 4kB pages rather
710 * than two possibly non-adjacent physical 4kB pages.
711 */
712 if (bh == NULL) { /* paging requests have (rq->bh == NULL) */
713 addr = virt_to_bus(rq->buffer);
714 size = rq->nr_sectors << 9;
715 } else {
716 /* group sequential buffers into one large buffer */
717 addr = virt_to_bus(bh->b_data);
718 size = bh->b_size;
719 while ((bh = bh->b_reqnext) != NULL) {
720 if ((addr + size) != virt_to_bus(bh->b_data))
721 break;
722 size += bh->b_size;
723 }
724 }
725
726 /*
727 * Fill in the next DBDMA command block.
728 * Note that one DBDMA command can transfer
729 * at most 65535 bytes.
730 */
731 while (size) {
732 unsigned int tc = (size < 0xfe00)? size: 0xfe00;
733
734 if (++count >= MAX_DCMDS) {
735 printk("%s: DMA table too small\n",
736 drive->name);
737 return 0; /* revert to PIO for this request */
738 }
739 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
740 st_le16(&table->req_count, tc);
741 st_le32(&table->phy_addr, addr);
742 table->cmd_dep = 0;
743 table->xfer_status = 0;
744 table->res_count = 0;
745 addr += tc;
746 size -= tc;
747 ++table;
748 }
749 } while (bh != NULL);
750
751 /* convert the last command to an input/output last command */
752 if (count)
753 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
754 else
755 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
756
757 /* add the stop command to the end of the list */
758 memset(table, 0, sizeof(struct dbdma_cmd));
759 out_le16(&table->command, DBDMA_STOP);
760
761 out_le32(&dma->cmdptr, virt_to_bus(tstart));
762 return 1;
763 }
764
765
766 static __inline__ unsigned char
767 dma_bits_to_command(unsigned char bits)
768 {
769 if(bits & 0x04)
770 return XFER_MW_DMA_2;
771 if(bits & 0x02)
772 return XFER_MW_DMA_1;
773 if(bits & 0x01)
774 return XFER_MW_DMA_0;
775 return 0;
776 }
777
778 static __inline__ unsigned char
779 udma_bits_to_command(unsigned char bits)
780 {
781 if(bits & 0x10)
782 return XFER_UDMA_4;
783 if(bits & 0x08)
784 return XFER_UDMA_3;
785 if(bits & 0x04)
786 return XFER_UDMA_2;
787 if(bits & 0x02)
788 return XFER_UDMA_1;
789 if(bits & 0x01)
790 return XFER_UDMA_0;
791 return 0;
792 }
793
794 /* Calculate MultiWord DMA timings */
795 static int
796 pmac_ide_mdma_enable(ide_drive_t *drive, int idx)
797 {
798 byte bits = drive->id->dma_mword & 0x07;
799 byte feature = dma_bits_to_command(bits);
800 u32 *timings;
801 int cycleTime, accessTime;
802 int accessTicks, recTicks;
803 struct hd_driveid *id = drive->id;
804 int ret;
805
806 /* Set feature on drive */
807 printk("%s: Enabling MultiWord DMA %d\n", drive->name, feature & 0xf);
808 ret = pmac_ide_do_setfeature(drive, feature);
809 if (ret) {
810 printk("%s: Failed !\n", drive->name);
811 return 0;
812 }
813
814 if (!drive->init_speed)
815 drive->init_speed = feature;
816
817 /* which drive is it ? */
818 if (drive->select.all & 0x10)
819 timings = &pmac_ide[idx].timings[1];
820 else
821 timings = &pmac_ide[idx].timings[0];
822
823 /* Calculate accesstime and cycle time */
824 cycleTime = mdma_timings[feature & 0xf].cycleTime;
825 accessTime = mdma_timings[feature & 0xf].accessTime;
826 if ((id->field_valid & 2) && (id->eide_dma_time))
827 cycleTime = id->eide_dma_time;
828 if ((pmac_ide[idx].kind == controller_ohare) && (cycleTime < 150))
829 cycleTime = 150;
830
831 /* For ata-4 controller */
832 if (pmac_ide[idx].kind == controller_kl_ata4) {
833 accessTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
834 recTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000) - accessTicks;
835 *timings = ((*timings) & 0xffe003ff) |
836 (accessTicks | (recTicks << 5)) << 10;
837 } else {
838 int halfTick = 0;
839 int origAccessTime = accessTime;
840 int origCycleTime = cycleTime;
841
842 accessTicks = SYSCLK_TICKS(accessTime);
843 if (accessTicks < 1)
844 accessTicks = 1;
845 accessTime = accessTicks * IDE_SYSCLK_NS;
846 recTicks = SYSCLK_TICKS(cycleTime - accessTime) - 1;
847 if (recTicks < 1)
848 recTicks = 1;
849 cycleTime = (recTicks + 1 + accessTicks) * IDE_SYSCLK_NS;
850
851 /* KeyLargo ata-3 don't support the half-tick stuff */
852 if ((pmac_ide[idx].kind != controller_kl_ata3) &&
853 (accessTicks > 1) &&
854 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
855 ((cycleTime - IDE_SYSCLK_NS) >= origCycleTime)) {
856 halfTick = 1;
857 accessTicks--;
858 }
859 *timings = ((*timings) & 0x7FF) |
860 (accessTicks | (recTicks << 5) | (halfTick << 10)) << 11;
861 }
862 #ifdef IDE_PMAC_DEBUG
863 printk("ide_pmac: Set MDMA timing for mode %d, reg: 0x%08x\n",
864 feature & 0xf, *timings);
865 #endif
866 drive->current_speed = feature;
867 return 1;
868 }
869
870 /* Calculate Ultra DMA timings */
871 static int
872 pmac_ide_udma_enable(ide_drive_t *drive, int idx)
873 {
874 byte bits = drive->id->dma_ultra & 0x1f;
875 byte feature = udma_bits_to_command(bits);
876 int cycleTime, accessTime;
877 int rdyToPauseTicks, cycleTicks;
878 u32 *timings;
879 int ret;
880
881 /* Set feature on drive */
882 printk("%s: Enabling Ultra DMA %d\n", drive->name, feature & 0xf);
883 ret = pmac_ide_do_setfeature(drive, feature);
884 if (ret) {
885 printk("%s: Failed !\n", drive->name);
886 return 0;
887 }
888
889 if (!drive->init_speed)
890 drive->init_speed = feature;
891
892 /* which drive is it ? */
893 if (drive->select.all & 0x10)
894 timings = &pmac_ide[idx].timings[1];
895 else
896 timings = &pmac_ide[idx].timings[0];
897
898 cycleTime = udma_timings[feature & 0xf].cycleTime;
899 accessTime = udma_timings[feature & 0xf].accessTime;
900
901 rdyToPauseTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
902 cycleTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000);
903
904 *timings = ((*timings) & 0xe00fffff) |
905 ((cycleTicks << 1) | (rdyToPauseTicks << 5) | 1) << 20;
906
907 drive->current_speed = feature;
908 return 1;
909 }
910
911 static int
912 pmac_ide_check_dma(ide_drive_t *drive)
913 {
914 int ata4, udma, idx;
915 struct hd_driveid *id = drive->id;
916 int enable = 1;
917
918 drive->using_dma = 0;
919
920 idx = pmac_ide_find(drive);
921 if (idx < 0)
922 return 0;
923
924 if (drive->media == ide_floppy)
925 enable = 0;
926 if (((id->capability & 1) == 0) && !check_drive_lists(drive, GOOD_DMA_DRIVE))
927 enable = 0;
928 if (check_drive_lists(drive, BAD_DMA_DRIVE))
929 enable = 0;
930
931 udma = 0;
932 ata4 = (pmac_ide[idx].kind == controller_kl_ata4);
933
934 if(enable) {
935 if (ata4 && (drive->media == ide_disk) &&
936 (id->field_valid & 0x0004) && (id->dma_ultra & 0x17)) {
937 /* UltraDMA modes. */
938 drive->using_dma = pmac_ide_udma_enable(drive, idx);
939 }
940 if (!drive->using_dma && (id->dma_mword & 0x0007)) {
941 /* Normal MultiWord DMA modes. */
942 drive->using_dma = pmac_ide_mdma_enable(drive, idx);
943 }
944 /* Without this, strange things will happen on Keylargo-based
945 * machines
946 */
947 OUT_BYTE(0, IDE_CONTROL_REG);
948 /* Apply settings to controller */
949 pmac_ide_selectproc(drive);
950 }
951 return 0;
952 }
953
954 int pmac_ide_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
955 {
956 int ix, dstat;
957 volatile struct dbdma_regs *dma;
958
959 /* Can we stuff a pointer to our intf structure in config_data
960 * or select_data in hwif ?
961 */
962 ix = pmac_ide_find(drive);
963 if (ix < 0)
964 return 0;
965 dma = pmac_ide[ix].dma_regs;
966
967 switch (func) {
968 case ide_dma_off:
969 printk("%s: DMA disabled\n", drive->name);
970 case ide_dma_off_quietly:
971 drive->using_dma = 0;
972 break;
973 case ide_dma_on:
974 case ide_dma_check:
975 pmac_ide_check_dma(drive);
976 break;
977 case ide_dma_read:
978 case ide_dma_write:
979 if (!pmac_ide_build_dmatable(drive, ix, func==ide_dma_write))
980 return 1;
981 drive->waiting_for_dma = 1;
982 if (drive->media != ide_disk)
983 return 0;
984 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
985 OUT_BYTE(func==ide_dma_write? WIN_WRITEDMA: WIN_READDMA,
986 IDE_COMMAND_REG);
987 case ide_dma_begin:
988 out_le32(&dma->control, (RUN << 16) | RUN);
989 break;
990 case ide_dma_end:
991 drive->waiting_for_dma = 0;
992 dstat = in_le32(&dma->status);
993 out_le32(&dma->control, ((RUN|WAKE|DEAD) << 16));
994 /* verify good dma status */
995 return (dstat & (RUN|DEAD|ACTIVE)) != RUN;
996 case ide_dma_test_irq:
997 return (in_le32(&dma->status) & (RUN|ACTIVE)) == RUN;
998
999 /* Let's implement tose just in case someone wants them */
1000 case ide_dma_bad_drive:
1001 case ide_dma_good_drive:
1002 return check_drive_lists(drive, (func == ide_dma_good_drive));
1003 case ide_dma_verbose:
1004 return report_drive_dmaing(drive);
1005 case ide_dma_retune:
1006 case ide_dma_lostirq:
1007 case ide_dma_timeout:
1008 printk("ide_pmac_dmaproc: chipset supported %s func only: %d\n", ide_dmafunc_verbose(func), func);
1009 return 1;
1010 default:
1011 printk("ide_pmac_dmaproc: unsupported %s func: %d\n", ide_dmafunc_verbose(func), func);
1012 return 1;
1013 }
1014 return 0;
1015 }
1016 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1017
1018 #ifdef CONFIG_PMAC_PBOOK
1019 static void idepmac_sleep_disk(int i, unsigned long base)
1020 {
1021 struct device_node* np = pmac_ide[i].node;
1022 int j;
1023
1024 /* FIXME: We only handle the master IDE */
1025 if (ide_hwifs[i].drives[0].media == ide_disk) {
1026 /* Spin down the drive */
1027 outb(0xa0, base+0x60);
1028 outb(0x0, base+0x30);
1029 outb(0x0, base+0x20);
1030 outb(0x0, base+0x40);
1031 outb(0x0, base+0x50);
1032 outb(0xe0, base+0x70);
1033 outb(0x2, base+0x160);
1034 for (j = 0; j < 10; j++) {
1035 int status;
1036 mdelay(100);
1037 status = inb(base+0x70);
1038 if (!(status & BUSY_STAT) && (status & DRQ_STAT))
1039 break;
1040 }
1041 }
1042 feature_set(np, FEATURE_IDE0_reset);
1043 feature_clear(np, FEATURE_IDE0_enable);
1044 switch(pmac_ide[i].aapl_bus_id) {
1045 case 0:
1046 feature_set(np, FEATURE_IDE0_reset);
1047 feature_clear(np, FEATURE_IDE0_enable);
1048 break;
1049 case 1:
1050 feature_set(np, FEATURE_IDE1_reset);
1051 feature_clear(np, FEATURE_IDE1_enable);
1052 break;
1053 case 2:
1054 feature_set(np, FEATURE_IDE2_reset);
1055 break;
1056 }
1057 pmac_ide[i].timings[0] = 0;
1058 pmac_ide[i].timings[1] = 0;
1059 }
1060
1061 static void idepmac_wake_disk(int i, unsigned long base)
1062 {
1063 struct device_node* np = pmac_ide[i].node;
1064 int j;
1065
1066 /* Revive IDE disk and controller */
1067 switch(pmac_ide[i].aapl_bus_id) {
1068 case 0:
1069 feature_set(np, FEATURE_IDE0_reset);
1070 mdelay(10);
1071 feature_set(np, FEATURE_IDE0_enable);
1072 mdelay(10);
1073 feature_clear(np, FEATURE_IDE0_reset);
1074 break;
1075 case 1:
1076 feature_set(np, FEATURE_IDE1_reset);
1077 mdelay(10);
1078 feature_set(np, FEATURE_IDE1_enable);
1079 mdelay(10);
1080 feature_clear(np, FEATURE_IDE1_reset);
1081 break;
1082 case 2:
1083 /* This one exists only for KL, I don't know
1084 about any enable bit */
1085 feature_set(np, FEATURE_IDE2_reset);
1086 mdelay(10);
1087 feature_clear(np, FEATURE_IDE2_reset);
1088 break;
1089 }
1090 mdelay(IDE_WAKEUP_DELAY_MS);
1091
1092 /* Reset timings */
1093 pmac_ide_selectproc(&ide_hwifs[i].drives[0]);
1094 mdelay(10);
1095
1096 /* Wait up to 10 seconds (enough for recent drives) */
1097 for (j = 0; j < 100; j++) {
1098 int status;
1099 mdelay(100);
1100 status = inb(base + 0x70);
1101 if (!(status & BUSY_STAT))
1102 break;
1103 }
1104 }
1105
1106 /* Here we handle media bay devices */
1107 static void
1108 idepmac_wake_bay(int i, unsigned long base)
1109 {
1110 int timeout;
1111
1112 /* Reset timings */
1113 pmac_ide_selectproc(&ide_hwifs[i].drives[0]);
1114 mdelay(10);
1115
1116 timeout = 10000;
1117 while ((inb(base + 0x70) & BUSY_STAT) && timeout) {
1118 mdelay(1);
1119 --timeout;
1120 }
1121 }
1122
1123 /* Note: We support only master drives for now. This will have to be
1124 * improved if we want to handle sleep on the iMacDV where the CD-ROM
1125 * is a slave
1126 */
1127 static int idepmac_notify_sleep(struct pmu_sleep_notifier *self, int when)
1128 {
1129 int i, ret;
1130 unsigned long base;
1131
1132 switch (when) {
1133 case PBOOK_SLEEP_REQUEST:
1134 break;
1135 case PBOOK_SLEEP_REJECT:
1136 break;
1137 case PBOOK_SLEEP_NOW:
1138 for (i = 0; i < pmac_ide_count; ++i) {
1139 if ((base = pmac_ide[i].regbase) == 0)
1140 continue;
1141 /* Disable irq during sleep */
1142 disable_irq(pmac_ide[i].irq);
1143 ret = check_media_bay_by_base(base, MB_CD);
1144 if ((ret == -ENODEV) && ide_hwifs[i].drives[0].present)
1145 /* not media bay - put the disk to sleep */
1146 idepmac_sleep_disk(i, base);
1147 }
1148 break;
1149 case PBOOK_WAKE:
1150 for (i = 0; i < pmac_ide_count; ++i) {
1151 ide_hwif_t *hwif;
1152 if ((base = pmac_ide[i].regbase) == 0)
1153 continue;
1154 hwif = &ide_hwifs[i];
1155 /* We don't handle media bay devices this way */
1156 ret = check_media_bay_by_base(base, MB_CD);
1157 if ((ret == -ENODEV) && ide_hwifs[i].drives[0].present)
1158 idepmac_wake_disk(i, base);
1159 else if (ret == 0)
1160 idepmac_wake_bay(i, base);
1161 enable_irq(pmac_ide[i].irq);
1162
1163 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1164 if (hwif->drives[0].present && hwif->drives[0].using_dma)
1165 pmac_ide_check_dma(&hwif->drives[0]);
1166 #endif
1167 }
1168 break;
1169 }
1170 return PBOOK_SLEEP_OK;
1171 }
1172 #endif /* CONFIG_PMAC_PBOOK */
1173