File: /usr/src/linux/drivers/ide/trm290.c
1 /*
2 * linux/drivers/ide/trm290.c Version 1.02 Mar. 18, 2000
3 *
4 * Copyright (c) 1997-1998 Mark Lord
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8 /*
9 * This module provides support for the bus-master IDE DMA function
10 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
11 * including a "Precision Instruments" board. The TRM290 pre-dates
12 * the sff-8038 standard (ide-dma.c) by a few months, and differs
13 * significantly enough to warrant separate routines for some functions,
14 * while re-using others from ide-dma.c.
15 *
16 * EXPERIMENTAL! It works for me (a sample of one).
17 *
18 * Works reliably for me in DMA mode (READs only),
19 * DMA WRITEs are disabled by default (see #define below);
20 *
21 * DMA is not enabled automatically for this chipset,
22 * but can be turned on manually (with "hdparm -d1") at run time.
23 *
24 * I need volunteers with "spare" drives for further testing
25 * and development, and maybe to help figure out the peculiarities.
26 * Even knowing the registers (below), some things behave strangely.
27 */
28
29 #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
30
31 /*
32 * TRM-290 PCI-IDE2 Bus Master Chip
33 * ================================
34 * The configuration registers are addressed in normal I/O port space
35 * and are used as follows:
36 *
37 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
38 *
39 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
40 * bit7 must always be written as "1"
41 * bits6-2 undefined
42 * bit1 1=legacy_compatible_mode, 0=native_pci_mode
43 * bit0 1=test_mode, 0=normal(default)
44 *
45 * trm290_base+2 when READ: status register (byte, read-only)
46 * bits7-2 undefined
47 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
48 * bit0 channel0 interrupt status 0=none, 1=asserted
49 *
50 * trm290_base+3 Interrupt mask register
51 * bits7-5 undefined
52 * bit4 legacy_header: 1=present, 0=absent
53 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
54 * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
55 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
56 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
57 *
58 * trm290_base+1 "CPR" Config Pointer Register (byte)
59 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
60 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
61 * bit5 0=enabled master burst access (default), 1=disable (write only)
62 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
63 * bit3 0=primary IDE channel, 1=secondary IDE channel
64 * bits2-0 register index for accesses through CDR port
65 *
66 * trm290_base+0 "CDR" Config Data Register (word)
67 * two sets of seven config registers,
68 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
69 * each index defined below:
70 *
71 * Index-0 Base address register for command block (word)
72 * defaults: 0x1f0 for primary, 0x170 for secondary
73 *
74 * Index-1 general config register (byte)
75 * bit7 1=DMA enable, 0=DMA disable
76 * bit6 1=activate IDE_RESET, 0=no action (default)
77 * bit5 1=enable IORDY, 0=disable IORDY (default)
78 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
79 * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
80 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
81 * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
82 * bit0 enable_io_ports: 1=enable(default), 0=disable
83 *
84 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
85 * bits7-0 bits7-0 of readahead count
86 *
87 * Index-3 read-ahead config register (byte, write only)
88 * bit7 1=enable_readahead, 0=disable_readahead(default)
89 * bit6 1=clear_FIFO, 0=no_action
90 * bit5 undefined
91 * bit4 mode4 timing control: 1=enable, 0=disable(default)
92 * bit3 undefined
93 * bit2 undefined
94 * bits1-0 bits9-8 of read-ahead count
95 *
96 * Index-4 base address register for control block (word)
97 * defaults: 0x3f6 for primary, 0x376 for secondary
98 *
99 * Index-5 data port timings (shared by both drives) (byte)
100 * standard PCI "clk" (clock) counts, default value = 0xf5
101 *
102 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
103 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
104 * 011=4clk, 100=5clk, 101=6clk,
105 * 110=8clk, 111=12clk
106 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
107 * 011=5clk, 100=6clk, 101=8clk,
108 * 110=12clk, 111=16clk
109 *
110 * Index-6 command/control port timings (shared by both drives) (byte)
111 * same layout as Index-5, default value = 0xde
112 *
113 * Suggested CDR programming for PIO mode0 (600ns):
114 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
115 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
116 *
117 * Suggested CDR programming for PIO mode3 (180ns):
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
119 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
120 *
121 * Suggested CDR programming for PIO mode4 (120ns):
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
123 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
124 *
125 */
126
127 #include <linux/config.h>
128 #include <linux/types.h>
129 #include <linux/kernel.h>
130 #include <linux/mm.h>
131 #include <linux/ioport.h>
132 #include <linux/interrupt.h>
133 #include <linux/blkdev.h>
134 #include <linux/init.h>
135 #include <linux/hdreg.h>
136 #include <linux/pci.h>
137 #include <linux/delay.h>
138 #include <linux/ide.h>
139
140 #include <asm/io.h>
141
142 static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
143 {
144 ide_hwif_t *hwif = HWIF(drive);
145 unsigned int reg;
146 unsigned long flags;
147
148 /* select PIO or DMA */
149 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
150
151 __save_flags(flags); /* local CPU only */
152 __cli(); /* local CPU only */
153
154 if (reg != hwif->select_data) {
155 hwif->select_data = reg;
156 outb(0x51|(hwif->channel<<3), hwif->config_data+1); /* set PIO/DMA */
157 outw(reg & 0xff, hwif->config_data);
158 }
159
160 /* enable IRQ if not probing */
161 if (drive->present) {
162 reg = inw(hwif->config_data+3) & 0x13;
163 reg &= ~(1 << hwif->channel);
164 outw(reg, hwif->config_data+3);
165 }
166
167 __restore_flags(flags); /* local CPU only */
168 }
169
170 static void trm290_selectproc (ide_drive_t *drive)
171 {
172 trm290_prepare_drive(drive, drive->using_dma);
173 }
174
175 #ifdef CONFIG_BLK_DEV_IDEDMA
176 static int trm290_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
177 {
178 ide_hwif_t *hwif = HWIF(drive);
179 unsigned int count, reading = 2, writing = 0;
180
181 switch (func) {
182 case ide_dma_write:
183 reading = 0;
184 writing = 1;
185 #ifdef TRM290_NO_DMA_WRITES
186 break; /* always use PIO for writes */
187 #endif
188 case ide_dma_read:
189 if (!(count = ide_build_dmatable(drive, func)))
190 break; /* try PIO instead of DMA */
191 trm290_prepare_drive(drive, 1); /* select DMA xfer */
192 outl(hwif->dmatable_dma|reading|writing, hwif->dma_base);
193 drive->waiting_for_dma = 1;
194 outw((count * 2) - 1, hwif->dma_base+2); /* start DMA */
195 if (drive->media != ide_disk)
196 return 0;
197 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
198 OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
199 return 0;
200 case ide_dma_begin:
201 return 0;
202 case ide_dma_end:
203 drive->waiting_for_dma = 0;
204 ide_destroy_dmatable(drive); /* purge DMA mappings */
205 return (inw(hwif->dma_base+2) != 0x00ff);
206 case ide_dma_test_irq:
207 return (inw(hwif->dma_base+2) == 0x00ff);
208 default:
209 return ide_dmaproc(func, drive);
210 }
211 trm290_prepare_drive(drive, 0); /* select PIO xfer */
212 return 1;
213 }
214 #endif /* CONFIG_BLK_DEV_IDEDMA */
215
216 /*
217 * Invoked from ide-dma.c at boot time.
218 */
219 void __init ide_init_trm290 (ide_hwif_t *hwif)
220 {
221 unsigned int cfgbase = 0;
222 unsigned long flags;
223 byte reg;
224 struct pci_dev *dev = hwif->pci_dev;
225
226 hwif->chipset = ide_trm290;
227 cfgbase = pci_resource_start(dev, 4);
228 if ((dev->class & 5) && cfgbase)
229 {
230 hwif->config_data = cfgbase;
231 printk("TRM290: chip config base at 0x%04lx\n", hwif->config_data);
232 } else {
233 hwif->config_data = 0x3df0;
234 printk("TRM290: using default config base at 0x%04lx\n", hwif->config_data);
235 }
236
237 __save_flags(flags); /* local CPU only */
238 __cli(); /* local CPU only */
239 /* put config reg into first byte of hwif->select_data */
240 outb(0x51|(hwif->channel<<3), hwif->config_data+1);
241 hwif->select_data = 0x21; /* select PIO as default */
242 outb(hwif->select_data, hwif->config_data);
243 reg = inb(hwif->config_data+3); /* get IRQ info */
244 reg = (reg & 0x10) | 0x03; /* mask IRQs for both ports */
245 outb(reg, hwif->config_data+3);
246 __restore_flags(flags); /* local CPU only */
247
248 if ((reg & 0x10))
249 hwif->irq = hwif->channel ? 15 : 14; /* legacy mode */
250 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
251 hwif->irq = hwif->mate->irq; /* sharing IRQ with mate */
252 ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
253
254 #ifdef CONFIG_BLK_DEV_IDEDMA
255 hwif->dmaproc = &trm290_dmaproc;
256 #endif /* CONFIG_BLK_DEV_IDEDMA */
257
258 hwif->selectproc = &trm290_selectproc;
259 hwif->autodma = 0; /* play it safe for now */
260 #if 1
261 {
262 /*
263 * My trm290-based card doesn't seem to work with all possible values
264 * for the control basereg, so this kludge ensures that we use only
265 * values that are known to work. Ugh. -ml
266 */
267 unsigned short old, compat = hwif->channel ? 0x374 : 0x3f4;
268 static unsigned short next_offset = 0;
269
270 outb(0x54|(hwif->channel<<3), hwif->config_data+1);
271 old = inw(hwif->config_data) & ~1;
272 if (old != compat && inb(old+2) == 0xff) {
273 compat += (next_offset += 0x400); /* leave lower 10 bits untouched */
274 #if 1
275 if (ide_check_region(compat + 2, 1))
276 printk("Aieee %s: ide_check_region failure at 0x%04x\n", hwif->name, (compat + 2));
277 /*
278 * The region check is not needed; however.........
279 * Since this is the checked in ide-probe.c,
280 * this is only an assignment.
281 */
282 #endif
283 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
284 outw(compat|1, hwif->config_data);
285 printk("%s: control basereg workaround: old=0x%04x, new=0x%04x\n", hwif->name, old, inw(hwif->config_data) & ~1);
286 }
287 }
288 #endif
289 }
290