File: /usr/src/linux/drivers/ide/ide-timing.h
1 #ifndef _IDE_TIMING_H
2 #define _IDE_TIMING_H
3
4 /*
5 * $Id: ide-timing.h,v 1.5 2001/01/15 21:48:56 vojtech Exp $
6 *
7 * Copyright (c) 1999-2000 Vojtech Pavlik
8 *
9 * Sponsored by SuSE
10 */
11
12 /*
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 * Should you need to contact me, the author, you can do so either by
28 * e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
29 * Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
30 */
31
32 #include <linux/hdreg.h>
33
34 #ifndef XFER_PIO_5
35 #define XFER_PIO_5 0x0d
36 #define XFER_UDMA_SLOW 0x4f
37 #endif
38
39 struct ide_timing {
40 short mode;
41 short setup; /* t1 */
42 short act8b; /* t2 for 8-bit io */
43 short rec8b; /* t2i for 8-bit io */
44 short cyc8b; /* t0 for 8-bit io */
45 short active; /* t2 or tD */
46 short recover; /* t2i or tK */
47 short cycle; /* t0 */
48 short udma; /* t2CYCTYP/2 */
49 };
50
51 /*
52 * PIO 0-5, MWDMA 0-2 and UDMA 0-5 timings (in nanoseconds).
53 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
54 * for PIO 5, which is a nonstandard extension.
55 */
56
57 static struct ide_timing ide_timing[] = {
58
59 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
60 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
61 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
62
63 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
64 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
65 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
66
67 { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 },
68
69 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
70 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
71 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
72
73 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
74 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
75 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
76
77 { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
78 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
79 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
80
81 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
82 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
83 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
84
85 { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
86
87 { -1 }
88 };
89
90 #define IDE_TIMING_SETUP 0x01
91 #define IDE_TIMING_ACT8B 0x02
92 #define IDE_TIMING_REC8B 0x04
93 #define IDE_TIMING_CYC8B 0x08
94 #define IDE_TIMING_8BIT 0x0e
95 #define IDE_TIMING_ACTIVE 0x10
96 #define IDE_TIMING_RECOVER 0x20
97 #define IDE_TIMING_CYCLE 0x40
98 #define IDE_TIMING_UDMA 0x80
99 #define IDE_TIMING_ALL 0xff
100
101 #define MIN(a,b) ((a)<(b)?(a):(b))
102 #define MAX(a,b) ((a)>(b)?(a):(b))
103 #define FIT(v,min,max) MAX(MIN(v,max),min)
104 #define ENOUGH(v,unit) (((v)-1)/(unit)+1)
105 #define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
106
107 #define XFER_MODE 0xf0
108 #define XFER_UDMA_100 0x44
109 #define XFER_UDMA_66 0x42
110 #define XFER_UDMA 0x40
111 #define XFER_MWDMA 0x20
112 #define XFER_SWDMA 0x10
113 #define XFER_EPIO 0x01
114 #define XFER_PIO 0x00
115
116 static short ide_find_best_mode(ide_drive_t *drive, int map)
117 {
118 struct hd_driveid *id = drive->id;
119 short best = 0;
120
121 if (!id)
122 return XFER_PIO_SLOW;
123
124 if ((map & XFER_UDMA) && (id->field_valid & 4)) { /* Want UDMA and UDMA bitmap valid */
125
126 if ((map & XFER_UDMA_100) == XFER_UDMA_100)
127 if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;
128
129 if ((map & XFER_UDMA_66) == XFER_UDMA_66)
130 if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
131 (id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;
132
133 if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
134 (id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
135 (id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
136 }
137
138 if ((map & XFER_MWDMA) && (id->field_valid & 2)) { /* Want MWDMA and drive has EIDE fields */
139
140 if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
141 (id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
142 (id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0)) return best;
143 }
144
145 if (map & XFER_SWDMA) { /* Want SWDMA */
146
147 if (id->field_valid & 2) { /* EIDE SWDMA */
148
149 if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
150 (id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
151 (id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0)) return best;
152 }
153
154 if (id->capability & 1) { /* Pre-EIDE style SWDMA */
155
156 if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
157 (id->tDMA == 1) ? XFER_SW_DMA_1 :
158 (id->tDMA == 0) ? XFER_SW_DMA_0 : 0)) return best;
159 }
160 }
161
162
163 if ((map & XFER_EPIO) && (id->field_valid & 2)) { /* EIDE PIO modes */
164
165 if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
166 (drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
167 (drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0)) return best;
168 }
169
170 return (drive->id->tPIO == 2) ? XFER_PIO_2 :
171 (drive->id->tPIO == 1) ? XFER_PIO_1 :
172 (drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
173 }
174
175 static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
176 {
177 q->setup = EZ(t->setup, T);
178 q->act8b = EZ(t->act8b, T);
179 q->rec8b = EZ(t->rec8b, T);
180 q->cyc8b = EZ(t->cyc8b, T);
181 q->active = EZ(t->active, T);
182 q->recover = EZ(t->recover, T);
183 q->cycle = EZ(t->cycle, T);
184 q->udma = EZ(t->udma, UT);
185 }
186
187 static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
188 {
189 if (what & IDE_TIMING_SETUP ) m->setup = MAX(a->setup, b->setup);
190 if (what & IDE_TIMING_ACT8B ) m->act8b = MAX(a->act8b, b->act8b);
191 if (what & IDE_TIMING_REC8B ) m->rec8b = MAX(a->rec8b, b->rec8b);
192 if (what & IDE_TIMING_CYC8B ) m->cyc8b = MAX(a->cyc8b, b->cyc8b);
193 if (what & IDE_TIMING_ACTIVE ) m->active = MAX(a->active, b->active);
194 if (what & IDE_TIMING_RECOVER) m->recover = MAX(a->recover, b->recover);
195 if (what & IDE_TIMING_CYCLE ) m->cycle = MAX(a->cycle, b->cycle);
196 if (what & IDE_TIMING_UDMA ) m->udma = MAX(a->udma, b->udma);
197 }
198
199 static struct ide_timing* ide_timing_find_mode(short speed)
200 {
201 struct ide_timing *t;
202
203 for (t = ide_timing; t->mode != speed; t++)
204 if (t->mode < 0)
205 return NULL;
206 return t;
207 }
208
209 static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
210 {
211 struct hd_driveid *id = drive->id;
212 struct ide_timing *s, p;
213
214 /*
215 * Find the mode.
216 */
217
218 if (!(s = ide_timing_find_mode(speed)))
219 return -EINVAL;
220
221 /*
222 * If the drive is an EIDE drive, it can tell us it needs extended
223 * PIO/MWDMA cycle timing.
224 */
225
226 if (id && id->field_valid & 2) { /* EIDE drive */
227
228 memset(&p, 0, sizeof(p));
229
230 switch (speed & XFER_MODE) {
231
232 case XFER_PIO:
233 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
234 else p.cycle = p.cyc8b = id->eide_pio_iordy;
235 break;
236
237 case XFER_MWDMA:
238 p.cycle = id->eide_dma_min;
239 break;
240 }
241
242 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
243 }
244
245 /*
246 * Convert the timing to bus clock counts.
247 */
248
249 ide_timing_quantize(s, t, T, UT);
250
251 /*
252 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
253 * and some other commands. We have to ensure that the DMA cycle timing is
254 * slower/equal than the fastest PIO timing.
255 */
256
257 if ((speed & XFER_MODE) != XFER_PIO) {
258 ide_timing_compute(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
259 ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
260 }
261
262 /*
263 * Lenghten active & recovery time so that cycle time is correct.
264 */
265
266 if (t->act8b + t->rec8b < t->cyc8b) {
267 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
268 t->rec8b = t->cyc8b - t->act8b;
269 }
270
271 if (t->active + t->recover < t->cycle) {
272 t->active += (t->cycle - (t->active + t->recover)) / 2;
273 t->recover = t->cycle - t->active;
274 }
275
276 return 0;
277 }
278
279 #endif
280