File: /usr/src/linux/drivers/ieee1394/ohci1394.c
1 /*
2 * ohci1394.c - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 * 2001 Ben Collins <bcollins@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 /*
23 * Things known to be working:
24 * . Async Request Transmit
25 * . Async Response Receive
26 * . Async Request Receive
27 * . Async Response Transmit
28 * . Iso Receive
29 * . DMA mmap for iso receive
30 * . Config ROM generation
31 *
32 * Things implemented, but still in test phase:
33 * . Iso Transmit
34 *
35 * Things not implemented:
36 * . Async Stream Packets
37 * . DMA error recovery
38 *
39 * Known bugs:
40 * . Apple PowerBook detected but not working yet (still true?)
41 */
42
43 /*
44 * Acknowledgments:
45 *
46 * Adam J Richter <adam@yggdrasil.com>
47 * . Use of pci_class to find device
48 *
49 * Andreas Tobler <toa@pop.agri.ch>
50 * . Updated proc_fs calls
51 *
52 * Emilie Chung <emilie.chung@axis.com>
53 * . Tip on Async Request Filter
54 *
55 * Pascal Drolet <pascal.drolet@informission.ca>
56 * . Various tips for optimization and functionnalities
57 *
58 * Robert Ficklin <rficklin@westengineering.com>
59 * . Loop in irq_handler
60 *
61 * James Goodwin <jamesg@Filanet.com>
62 * . Various tips on initialization, self-id reception, etc.
63 *
64 * Albrecht Dress <ad@mpifr-bonn.mpg.de>
65 * . Apple PowerBook detection
66 *
67 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
68 * . Reset the board properly before leaving + misc cleanups
69 *
70 * Leon van Stuivenberg <leonvs@iae.nl>
71 * . Bug fixes
72 *
73 * Ben Collins <bcollins@debian.org>
74 * . Working big-endian support
75 * . Updated to 2.4.x module scheme (PCI aswell)
76 * . Removed procfs support since it trashes random mem
77 * . Config ROM generation
78 */
79
80 #include <linux/config.h>
81 #include <linux/kernel.h>
82 #include <linux/list.h>
83 #include <linux/slab.h>
84 #include <linux/interrupt.h>
85 #include <linux/wait.h>
86 #include <linux/errno.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/fs.h>
90 #include <linux/poll.h>
91 #include <asm/byteorder.h>
92 #include <asm/atomic.h>
93 #include <asm/io.h>
94 #include <asm/uaccess.h>
95 #include <linux/tqueue.h>
96 #include <linux/delay.h>
97 #include <linux/spinlock.h>
98
99 #include <asm/pgtable.h>
100 #include <asm/page.h>
101 #include <linux/sched.h>
102 #include <asm/segment.h>
103 #include <linux/types.h>
104 #include <linux/wrapper.h>
105 #include <linux/vmalloc.h>
106 #include <linux/init.h>
107
108 #include "ieee1394.h"
109 #include "ieee1394_types.h"
110 #include "hosts.h"
111 #include "ieee1394_core.h"
112 #include "highlevel.h"
113 #include "ohci1394.h"
114
115
116 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
117 #define OHCI1394_DEBUG
118 #endif
119
120 #ifdef DBGMSG
121 #undef DBGMSG
122 #endif
123
124 #ifdef OHCI1394_DEBUG
125 #define DBGMSG(card, fmt, args...) \
126 printk(KERN_INFO "ohci1394_%d: " fmt "\n" , card , ## args)
127 #else
128 #define DBGMSG(card, fmt, args...)
129 #endif
130
131 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
132 #define OHCI_DMA_ALLOC(fmt, args...) \
133 HPSB_ERR("ohci1394("__FUNCTION__")alloc(%d): "fmt, \
134 ++global_outstanding_dmas, ## args)
135 #define OHCI_DMA_FREE(fmt, args...) \
136 HPSB_ERR("ohci1394("__FUNCTION__")free(%d): "fmt, \
137 --global_outstanding_dmas, ## args)
138 u32 global_outstanding_dmas = 0;
139 #else
140 #define OHCI_DMA_ALLOC(fmt, args...)
141 #define OHCI_DMA_FREE(fmt, args...)
142 #endif
143
144 /* print general (card independent) information */
145 #define PRINT_G(level, fmt, args...) \
146 printk(level "ohci1394: " fmt "\n" , ## args)
147
148 /* print card specific information */
149 #define PRINT(level, card, fmt, args...) \
150 printk(level "ohci1394_%d: " fmt "\n" , card , ## args)
151
152 #define FAIL(fmt, args...) \
153 do { \
154 PRINT_G(KERN_ERR, fmt , ## args); \
155 remove_card(ohci); \
156 return 1; \
157 } while(0)
158
159 #define PCI_CLASS_FIREWIRE_OHCI ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
160
161 static struct pci_device_id ohci1394_pci_tbl[] __devinitdata = {
162 {
163 class: PCI_CLASS_FIREWIRE_OHCI,
164 class_mask: 0x00ffffff,
165 vendor: PCI_ANY_ID,
166 device: PCI_ANY_ID,
167 subvendor: PCI_ANY_ID,
168 subdevice: PCI_ANY_ID,
169 },
170 { 0, },
171 };
172 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
173
174 static char version[] __devinitdata =
175 "v0.51 08/08/01 Ben Collins <bcollins@debian.org>";
176
177 /* Module Parameters */
178 MODULE_PARM(attempt_root,"i");
179 MODULE_PARM_DESC(attempt_root, "Attempt to make the host root.");
180 static int attempt_root = 0;
181
182 #ifdef __LITTLE_ENDIAN
183 /* Don't waste cycles on same sex byte swaps */
184 #define packet_swab(w,x,y,z)
185 #define block_swab32(x,y)
186 #else
187 static void packet_swab(quadlet_t *data, char tcode, int len, int payload_swap);
188 static __inline__ void block_swab32(quadlet_t *data, size_t size);
189 #endif
190
191 static unsigned int card_id_counter = 0;
192
193 static void dma_trm_tasklet(unsigned long data);
194 static void remove_card(struct ti_ohci *ohci);
195 static void dma_trm_reset(struct dma_trm_ctx *d);
196
197 /***********************************
198 * IEEE-1394 functionality section *
199 ***********************************/
200
201 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
202 {
203 int i;
204 unsigned long flags;
205 quadlet_t r;
206
207 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
208
209 reg_write(ohci, OHCI1394_PhyControl, (((u16)addr << 8) & 0x00000f00) | 0x00008000);
210
211 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
212 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
213 break;
214
215 mdelay(1);
216 }
217
218 r = reg_read(ohci, OHCI1394_PhyControl);
219
220 if (i >= OHCI_LOOP_COUNT)
221 PRINT (KERN_ERR, ohci->id, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
222 r, r & 0x80000000, i);
223
224 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
225
226 return (r & 0x00ff0000) >> 16;
227 }
228
229 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
230 {
231 int i;
232 unsigned long flags;
233 u32 r;
234
235 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
236
237 reg_write(ohci, OHCI1394_PhyControl, 0x00004000 | (((u16)addr << 8) & 0x00000f00) | data);
238
239 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
240 r = reg_read(ohci, OHCI1394_PhyControl);
241 if (!(r & 0x00004000))
242 break;
243
244 mdelay(1);
245 }
246
247 if (i == OHCI_LOOP_COUNT)
248 PRINT (KERN_ERR, ohci->id, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
249 r, r & 0x00004000, i);
250
251 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
252
253 return;
254 }
255
256 /* Or's our value into the current value */
257 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
258 {
259 u8 old;
260
261 old = get_phy_reg (ohci, addr);
262 old |= data;
263 set_phy_reg (ohci, addr, old);
264
265 return;
266 }
267
268 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
269 int phyid, int isroot)
270 {
271 quadlet_t *q = ohci->selfid_buf_cpu;
272 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
273 size_t size;
274 quadlet_t q0, q1;
275
276 mdelay(10);
277
278 /* Check status of self-id reception */
279
280 if (ohci->selfid_swap)
281 q0 = le32_to_cpu(q[0]);
282 else
283 q0 = q[0];
284
285 if ((self_id_count & 0x80000000) ||
286 ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
287 PRINT(KERN_ERR, ohci->id,
288 "Error in reception of SelfID packets [0x%08x/0x%08x]",
289 self_id_count, q0);
290
291 /* Tip by James Goodwin <jamesg@Filanet.com>:
292 * We had an error, generate another bus reset in response. */
293 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
294 set_phy_reg_mask (ohci, 1, 0x40);
295 ohci->self_id_errors++;
296 } else {
297 PRINT(KERN_ERR, ohci->id,
298 "Too many errors on SelfID error reception, giving up!");
299 }
300 return;
301 }
302
303 size = ((self_id_count & 0x00001FFC) >> 2) - 1;
304 q++;
305
306 while (size > 0) {
307 if (ohci->selfid_swap) {
308 q0 = le32_to_cpu(q[0]);
309 q1 = le32_to_cpu(q[1]);
310 } else {
311 q0 = q[0];
312 q1 = q[1];
313 }
314
315 if (q0 == ~q1) {
316 DBGMSG (ohci->id, "SelfID packet 0x%x received", q0);
317 hpsb_selfid_received(host, cpu_to_be32(q0));
318 if (((q0 & 0x3f000000) >> 24) == phyid)
319 DBGMSG (ohci->id, "SelfID for this node is 0x%08x", q0);
320 } else {
321 PRINT(KERN_ERR, ohci->id,
322 "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
323 }
324 q += 2;
325 size -= 2;
326 }
327
328 DBGMSG(ohci->id, "SelfID complete");
329
330 hpsb_selfid_complete(host, phyid, isroot);
331
332 return;
333 }
334
335 static int ohci_soft_reset(struct ti_ohci *ohci) {
336 int i;
337
338 reg_write(ohci, OHCI1394_HCControlSet, 0x00010000);
339
340 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
341 if (reg_read(ohci, OHCI1394_HCControlSet) & 0x00010000)
342 break;
343 mdelay(1);
344 }
345
346 DBGMSG (ohci->id, "Soft reset finished");
347
348 return 0;
349 }
350
351 static int run_context(struct ti_ohci *ohci, int reg, char *msg)
352 {
353 u32 nodeId;
354
355 /* check that the node id is valid */
356 nodeId = reg_read(ohci, OHCI1394_NodeID);
357 if (!(nodeId&0x80000000)) {
358 PRINT(KERN_ERR, ohci->id,
359 "Running dma failed because Node ID is not valid");
360 return -1;
361 }
362
363 /* check that the node number != 63 */
364 if ((nodeId&0x3f)==63) {
365 PRINT(KERN_ERR, ohci->id,
366 "Running dma failed because Node ID == 63");
367 return -1;
368 }
369
370 /* Run the dma context */
371 reg_write(ohci, reg, 0x8000);
372
373 if (msg) PRINT(KERN_DEBUG, ohci->id, "%s", msg);
374
375 return 0;
376 }
377
378 /* Generate the dma receive prgs and start the context */
379 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d)
380 {
381 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
382 int i;
383
384 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
385
386 for (i=0; i<d->num_desc; i++) {
387
388 d->prg_cpu[i]->control =
389 cpu_to_le32((0x280C << 16) | d->buf_size);
390
391 /* End of descriptor list? */
392 if ((i+1) < d->num_desc) {
393 d->prg_cpu[i]->branchAddress =
394 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
395 } else {
396 d->prg_cpu[i]->branchAddress =
397 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
398 }
399
400 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
401 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
402 }
403
404 d->buf_ind = 0;
405 d->buf_offset = 0;
406
407 /* Tell the controller where the first AR program is */
408 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
409
410 /* Run AR context */
411 reg_write(ohci, d->ctrlSet, 0x00008000);
412
413 DBGMSG(ohci->id, "Receive DMA ctx=%d initialized", d->ctx);
414 }
415
416 /* Initialize the dma transmit context */
417 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
418 {
419 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
420
421 /* Stop the context */
422 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
423
424 d->prg_ind = 0;
425 d->sent_ind = 0;
426 d->free_prgs = d->num_desc;
427 d->branchAddrPtr = NULL;
428 d->fifo_first = NULL;
429 d->fifo_last = NULL;
430 d->pending_first = NULL;
431 d->pending_last = NULL;
432
433 DBGMSG(ohci->id, "Transmit DMA ctx=%d initialized", d->ctx);
434 }
435
436 /* Count the number of available iso contexts */
437 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
438 {
439 int i,ctx=0;
440 u32 tmp;
441
442 reg_write(ohci, reg, 0xffffffff);
443 tmp = reg_read(ohci, reg);
444
445 DBGMSG(ohci->id,"Iso contexts reg: %08x implemented: %08x", reg, tmp);
446
447 /* Count the number of contexts */
448 for(i=0; i<32; i++) {
449 if(tmp & 1) ctx++;
450 tmp >>= 1;
451 }
452 return ctx;
453 }
454
455 static void ohci_init_config_rom(struct ti_ohci *ohci);
456
457 /* Global initialization */
458 static int ohci_initialize(struct hpsb_host *host)
459 {
460 struct ti_ohci *ohci=host->hostdata;
461 int retval, i;
462 quadlet_t buf;
463
464 spin_lock_init(&ohci->phy_reg_lock);
465 spin_lock_init(&ohci->event_lock);
466
467 /* Soft reset */
468 if ((retval = ohci_soft_reset(ohci)) < 0)
469 return retval;
470
471 /* Put some defaults to these undefined bus options */
472 buf = reg_read(ohci, OHCI1394_BusOptions);
473 buf |= 0x60000000; /* Enable CMC and ISC */
474 buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
475 buf &= ~0x98000000; /* Disable PMC, IRMC and BMC */
476 reg_write(ohci, OHCI1394_BusOptions, buf);
477
478 /* Set Link Power Status (LPS) */
479 reg_write(ohci, OHCI1394_HCControlSet, 0x00080000);
480
481 /* After enabling LPS, we need to wait for the connection
482 * between phy and link to be established. This should be
483 * signaled by the LPS bit becoming 1, but this happens
484 * immediately. Instead we wait for reads from LinkControl to
485 * give a valid result, i.e. not 0xffffffff. */
486 while (reg_read(ohci, OHCI1394_LinkControlSet) == 0xffffffff) {
487 DBGMSG(ohci->id, "waiting for phy-link connection");
488 mdelay(2);
489 }
490
491 /* Set the bus number */
492 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
493
494 /* Enable posted writes */
495 reg_write(ohci, OHCI1394_HCControlSet, 0x00040000);
496
497 /* Clear link control register */
498 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
499
500 /* Enable cycle timer and cycle master */
501 reg_write(ohci, OHCI1394_LinkControlSet, 0x00300000);
502
503 /* Clear interrupt registers */
504 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
505 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
506
507 /* Set up self-id dma buffer */
508 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
509
510 /* enable self-id dma */
511 reg_write(ohci, OHCI1394_LinkControlSet, 0x00000200);
512
513 /* Set the Config ROM mapping register */
514 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
515
516 /* Initialize the Config ROM */
517 ohci_init_config_rom(ohci);
518
519 /* Now get our max packet size */
520 ohci->max_packet_size =
521 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
522
523 /* Don't accept phy packets into AR request context */
524 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
525
526 /* Initialize IR dma */
527 ohci->nb_iso_rcv_ctx =
528 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
529 DBGMSG(ohci->id, "%d iso receive contexts available",
530 ohci->nb_iso_rcv_ctx);
531 for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
532 reg_write(ohci, OHCI1394_IsoRcvContextControlClear+32*i,
533 0xffffffff);
534 reg_write(ohci, OHCI1394_IsoRcvContextMatch+32*i, 0);
535 reg_write(ohci, OHCI1394_IsoRcvCommandPtr+32*i, 0);
536 }
537
538 /* Set bufferFill, isochHeader, multichannel for IR context */
539 reg_write(ohci, OHCI1394_IsoRcvContextControlSet, 0xd0000000);
540
541 /* Set the context match register to match on all tags */
542 reg_write(ohci, OHCI1394_IsoRcvContextMatch, 0xf0000000);
543
544 /* Clear the interrupt mask */
545 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
546 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
547
548 /* Initialize IT dma */
549 ohci->nb_iso_xmit_ctx =
550 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
551 DBGMSG(ohci->id, "%d iso transmit contexts available",
552 ohci->nb_iso_xmit_ctx);
553 for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
554 reg_write(ohci, OHCI1394_IsoXmitContextControlClear+32*i,
555 0xffffffff);
556 reg_write(ohci, OHCI1394_IsoXmitCommandPtr+32*i, 0);
557 }
558
559 /* Clear the interrupt mask */
560 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
561 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
562
563 /* Clear the multi channel mask high and low registers */
564 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
565 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
566
567 /* Initialize AR dma */
568 initialize_dma_rcv_ctx(ohci->ar_req_context);
569 initialize_dma_rcv_ctx(ohci->ar_resp_context);
570
571 /* Initialize AT dma */
572 initialize_dma_trm_ctx(ohci->at_req_context);
573 initialize_dma_trm_ctx(ohci->at_resp_context);
574
575 /* Initialize IR dma */
576 initialize_dma_rcv_ctx(ohci->ir_context);
577
578 /* Initialize IT dma */
579 initialize_dma_trm_ctx(ohci->it_context);
580
581 /* Set up isoRecvIntMask to generate interrupts for context 0
582 (thanks to Michael Greger for seeing that I forgot this) */
583 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 0x00000001);
584
585 /* Set up isoXmitIntMask to generate interrupts for context 0 */
586 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 0x00000001);
587
588 /*
589 * Accept AT requests from all nodes. This probably
590 * will have to be controlled from the subsystem
591 * on a per node basis.
592 */
593 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
594
595 /* Specify AT retries */
596 reg_write(ohci, OHCI1394_ATRetries,
597 OHCI1394_MAX_AT_REQ_RETRIES |
598 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
599 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
600
601 /* We don't want hardware swapping */
602 reg_write(ohci, OHCI1394_HCControlClear, 0x40000000);
603
604 /* Enable interrupts */
605 reg_write(ohci, OHCI1394_IntMaskSet,
606 OHCI1394_masterIntEnable |
607 OHCI1394_phyRegRcvd |
608 OHCI1394_busReset |
609 OHCI1394_selfIDComplete |
610 OHCI1394_RSPkt |
611 OHCI1394_RQPkt |
612 OHCI1394_respTxComplete |
613 OHCI1394_reqTxComplete |
614 OHCI1394_isochRx |
615 OHCI1394_isochTx |
616 OHCI1394_unrecoverableError
617 );
618
619 /* Enable link */
620 reg_write(ohci, OHCI1394_HCControlSet, 0x00020000);
621
622 buf = reg_read(ohci, OHCI1394_Version);
623 PRINT(KERN_INFO, ohci->id, "OHCI-1394 %d.%d (PCI): IRQ=[%d] MMIO=[%lx-%lx]"
624 " Max Packet=[%d]", ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
625 ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
626 pci_resource_start(ohci->dev, 0),
627 pci_resource_start(ohci->dev, 0) + pci_resource_len(ohci->dev, 0),
628 ohci->max_packet_size);
629
630 return 1;
631 }
632
633 static void ohci_remove(struct hpsb_host *host)
634 {
635 struct ti_ohci *ohci;
636
637 if (host != NULL) {
638 ohci = host->hostdata;
639 remove_card(ohci);
640 }
641 }
642
643 /*
644 * Insert a packet in the AT DMA fifo and generate the DMA prg
645 * FIXME: rewrite the program in order to accept packets crossing
646 * page boundaries.
647 * check also that a single dma descriptor doesn't cross a
648 * page boundary.
649 */
650 static void insert_packet(struct ti_ohci *ohci,
651 struct dma_trm_ctx *d, struct hpsb_packet *packet)
652 {
653 u32 cycleTimer;
654 int idx = d->prg_ind;
655
656 DBGMSG(ohci->id, "Inserting packet for node %d, tlabel=%d, tcode=0x%x, speed=%d",
657 packet->node_id, packet->tlabel, packet->tcode, packet->speed_code);
658
659 d->prg_cpu[idx]->begin.address = 0;
660 d->prg_cpu[idx]->begin.branchAddress = 0;
661
662 if (d->ctx==1) {
663 /*
664 * For response packets, we need to put a timeout value in
665 * the 16 lower bits of the status... let's try 1 sec timeout
666 */
667 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
668 d->prg_cpu[idx]->begin.status = cpu_to_le32(
669 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
670 ((cycleTimer&0x01fff000)>>12));
671
672 DBGMSG(ohci->id, "cycleTimer: %08x timeStamp: %08x",
673 cycleTimer, d->prg_cpu[idx]->begin.status);
674 } else
675 d->prg_cpu[idx]->begin.status = 0;
676
677 if ( (packet->type == async) || (packet->type == raw) ) {
678
679 if (packet->type == raw) {
680 d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
681 d->prg_cpu[idx]->data[1] = packet->header[0];
682 d->prg_cpu[idx]->data[2] = packet->header[1];
683 } else {
684 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
685 (packet->header[0] & 0xFFFF);
686 d->prg_cpu[idx]->data[1] =
687 (packet->header[1] & 0xFFFF) |
688 (packet->header[0] & 0xFFFF0000);
689 d->prg_cpu[idx]->data[2] = packet->header[2];
690 d->prg_cpu[idx]->data[3] = packet->header[3];
691 packet_swab(d->prg_cpu[idx]->data, packet->tcode,
692 packet->header_size>>2, ohci->payload_swap);
693 }
694
695 if (packet->data_size) { /* block transmit */
696 d->prg_cpu[idx]->begin.control =
697 cpu_to_le32(OUTPUT_MORE_IMMEDIATE | 0x10);
698 d->prg_cpu[idx]->end.control =
699 cpu_to_le32(OUTPUT_LAST | packet->data_size);
700 /*
701 * Check that the packet data buffer
702 * does not cross a page boundary.
703 */
704 if (cross_bound((unsigned long)packet->data,
705 packet->data_size)>0) {
706 /* FIXME: do something about it */
707 PRINT(KERN_ERR, ohci->id, __FUNCTION__
708 ": packet data addr: %p size %Zd bytes "
709 "cross page boundary",
710 packet->data, packet->data_size);
711 }
712
713 d->prg_cpu[idx]->end.address = cpu_to_le32(
714 pci_map_single(ohci->dev, packet->data,
715 packet->data_size,
716 PCI_DMA_TODEVICE));
717 OHCI_DMA_ALLOC("single, block transmit packet");
718
719 if (ohci->payload_swap)
720 block_swab32(packet->data, packet->data_size >> 2);
721
722 d->prg_cpu[idx]->end.branchAddress = 0;
723 d->prg_cpu[idx]->end.status = 0;
724 if (d->branchAddrPtr)
725 *(d->branchAddrPtr) =
726 cpu_to_le32(d->prg_bus[idx] | 0x3);
727 d->branchAddrPtr =
728 &(d->prg_cpu[idx]->end.branchAddress);
729 } else { /* quadlet transmit */
730 if (packet->type == raw)
731 d->prg_cpu[idx]->begin.control = cpu_to_le32(
732 OUTPUT_LAST_IMMEDIATE |
733 (packet->header_size+4));
734 else
735 d->prg_cpu[idx]->begin.control = cpu_to_le32(
736 OUTPUT_LAST_IMMEDIATE |
737 packet->header_size);
738
739 if (d->branchAddrPtr)
740 *(d->branchAddrPtr) =
741 cpu_to_le32(d->prg_bus[idx] | 0x2);
742 d->branchAddrPtr =
743 &(d->prg_cpu[idx]->begin.branchAddress);
744 }
745
746 } else { /* iso packet */
747 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
748 (packet->header[0] & 0xFFFF);
749 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
750 packet_swab(d->prg_cpu[idx]->data, packet->tcode, packet->header_size>>2,
751 ohci->payload_swap);
752
753 d->prg_cpu[idx]->begin.control = cpu_to_le32(OUTPUT_MORE_IMMEDIATE | 0x8);
754 d->prg_cpu[idx]->end.control = cpu_to_le32(
755 OUTPUT_LAST | 0x08000000 | packet->data_size);
756 d->prg_cpu[idx]->end.address = cpu_to_le32(
757 pci_map_single(ohci->dev, packet->data,
758 packet->data_size, PCI_DMA_TODEVICE));
759 OHCI_DMA_ALLOC("single, iso transmit packet");
760
761 if (ohci->payload_swap)
762 block_swab32(packet->data, packet->data_size>>2);
763
764 d->prg_cpu[idx]->end.branchAddress = 0;
765 d->prg_cpu[idx]->end.status = 0;
766 DBGMSG(ohci->id, "Iso xmit context info: header[%08x %08x]\n"
767 " begin=%08x %08x %08x %08x\n"
768 " %08x %08x %08x %08x\n"
769 " end =%08x %08x %08x %08x",
770 d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
771 d->prg_cpu[idx]->begin.control,
772 d->prg_cpu[idx]->begin.address,
773 d->prg_cpu[idx]->begin.branchAddress,
774 d->prg_cpu[idx]->begin.status,
775 d->prg_cpu[idx]->data[0],
776 d->prg_cpu[idx]->data[1],
777 d->prg_cpu[idx]->data[2],
778 d->prg_cpu[idx]->data[3],
779 d->prg_cpu[idx]->end.control,
780 d->prg_cpu[idx]->end.address,
781 d->prg_cpu[idx]->end.branchAddress,
782 d->prg_cpu[idx]->end.status);
783 if (d->branchAddrPtr)
784 *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
785 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
786 }
787 d->free_prgs--;
788
789 /* queue the packet in the appropriate context queue */
790 if (d->fifo_last) {
791 d->fifo_last->xnext = packet;
792 d->fifo_last = packet;
793 } else {
794 d->fifo_first = packet;
795 d->fifo_last = packet;
796 }
797 d->prg_ind = (d->prg_ind+1)%d->num_desc;
798 }
799
800 /*
801 * This function fills the AT FIFO with the (eventual) pending packets
802 * and runs or wakes up the AT DMA prg if necessary.
803 *
804 * The function MUST be called with the d->lock held.
805 */
806 static int dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
807 {
808 int idx,z;
809
810 if (d->pending_first == NULL || d->free_prgs == 0)
811 return 0;
812
813 idx = d->prg_ind;
814 z = (d->pending_first->data_size) ? 3 : 2;
815
816 /* insert the packets into the at dma fifo */
817 while (d->free_prgs>0 && d->pending_first) {
818 insert_packet(ohci, d, d->pending_first);
819 d->pending_first = d->pending_first->xnext;
820 }
821 if (d->pending_first == NULL)
822 d->pending_last = NULL;
823 else
824 PRINT(KERN_INFO, ohci->id,
825 "Transmit DMA FIFO ctx=%d is full... waiting",d->ctx);
826
827 /* Is the context running ? (should be unless it is
828 the first packet to be sent in this context) */
829 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
830 DBGMSG(ohci->id,"Starting transmit DMA ctx=%d",d->ctx);
831 reg_write(ohci, d->cmdPtr, d->prg_bus[idx]|z);
832 run_context(ohci, d->ctrlSet, NULL);
833 }
834 else {
835 /* Wake up the dma context if necessary */
836 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
837 DBGMSG(ohci->id,"Waking transmit DMA ctx=%d",d->ctx);
838 reg_write(ohci, d->ctrlSet, 0x1000);
839 }
840 }
841 return 1;
842 }
843
844 /* Transmission of an async packet */
845 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
846 {
847 struct ti_ohci *ohci = host->hostdata;
848 struct dma_trm_ctx *d;
849 unsigned char tcode;
850 unsigned long flags;
851
852 if (packet->data_size > ohci->max_packet_size) {
853 PRINT(KERN_ERR, ohci->id,
854 "Transmit packet size %Zd is too big",
855 packet->data_size);
856 return 0;
857 }
858 packet->xnext = NULL;
859
860 /* Decide wether we have an iso, a request, or a response packet */
861 tcode = (packet->header[0]>>4)&0xf;
862 if (tcode == TCODE_ISO_DATA) d = ohci->it_context;
863 else if (tcode & 0x02) d = ohci->at_resp_context;
864 else d = ohci->at_req_context;
865
866 spin_lock_irqsave(&d->lock,flags);
867
868 /* queue the packet for later insertion into the dma fifo */
869 if (d->pending_last) {
870 d->pending_last->xnext = packet;
871 d->pending_last = packet;
872 }
873 else {
874 d->pending_first = packet;
875 d->pending_last = packet;
876 }
877
878 dma_trm_flush(ohci, d);
879
880 spin_unlock_irqrestore(&d->lock,flags);
881
882 return 1;
883 }
884
885 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
886 {
887 struct ti_ohci *ohci = host->hostdata;
888 int retval = 0;
889 unsigned long flags;
890
891 switch (cmd) {
892 case RESET_BUS:
893 DBGMSG(ohci->id, "devctl: Bus reset requested%s",
894 ((host->attempt_root || attempt_root) ?
895 " and attempting to become root" : ""));
896 set_phy_reg_mask (ohci, 1, 0x40 | ((host->attempt_root || attempt_root) ?
897 0x80 : 0));
898 break;
899
900 case GET_CYCLE_COUNTER:
901 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
902 break;
903
904 case SET_CYCLE_COUNTER:
905 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
906 break;
907
908 case SET_BUS_ID:
909 PRINT(KERN_ERR, ohci->id, "devctl command SET_BUS_ID err");
910 break;
911
912 case ACT_CYCLE_MASTER:
913 if (arg) {
914 /* check if we are root and other nodes are present */
915 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
916 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
917 /*
918 * enable cycleTimer, cycleMaster
919 */
920 DBGMSG(ohci->id, "Cycle master enabled");
921 reg_write(ohci, OHCI1394_LinkControlSet,
922 0x00300000);
923 }
924 } else {
925 /* disable cycleTimer, cycleMaster, cycleSource */
926 reg_write(ohci, OHCI1394_LinkControlClear, 0x00700000);
927 }
928 break;
929
930 case CANCEL_REQUESTS:
931 DBGMSG(ohci->id, "Cancel request received");
932 dma_trm_reset(ohci->at_req_context);
933 dma_trm_reset(ohci->at_resp_context);
934 break;
935
936 case MODIFY_USAGE:
937 if (arg) {
938 MOD_INC_USE_COUNT;
939 } else {
940 MOD_DEC_USE_COUNT;
941 }
942 break;
943
944 case ISO_LISTEN_CHANNEL:
945 {
946 u64 mask;
947
948 if (arg<0 || arg>63) {
949 PRINT(KERN_ERR, ohci->id, __FUNCTION__
950 "IS0 listne channel %d is out of range",
951 arg);
952 return -EFAULT;
953 }
954
955 mask = (u64)0x1<<arg;
956
957 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
958
959 if (ohci->ISO_channel_usage & mask) {
960 PRINT(KERN_ERR, ohci->id, __FUNCTION__
961 "IS0 listen channel %d is already used",
962 arg);
963 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
964 return -EFAULT;
965 }
966
967 ohci->ISO_channel_usage |= mask;
968
969 if (arg>31)
970 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
971 1<<(arg-32));
972 else
973 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
974 1<<arg);
975
976 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
977 DBGMSG(ohci->id, "Listening enabled on channel %d", arg);
978 break;
979 }
980 case ISO_UNLISTEN_CHANNEL:
981 {
982 u64 mask;
983
984 if (arg<0 || arg>63) {
985 PRINT(KERN_ERR, ohci->id, __FUNCTION__
986 "IS0 unlisten channel %d is out of range",
987 arg);
988 return -EFAULT;
989 }
990
991 mask = (u64)0x1<<arg;
992
993 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
994
995 if (!(ohci->ISO_channel_usage & mask)) {
996 PRINT(KERN_ERR, ohci->id, __FUNCTION__
997 "IS0 unlisten channel %d is not used",
998 arg);
999 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1000 return -EFAULT;
1001 }
1002
1003 ohci->ISO_channel_usage &= ~mask;
1004
1005 if (arg>31)
1006 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1007 1<<(arg-32));
1008 else
1009 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1010 1<<arg);
1011
1012 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1013 DBGMSG(ohci->id, "Listening disabled on channel %d", arg);
1014 break;
1015 }
1016 default:
1017 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1018 cmd);
1019 break;
1020 }
1021 return retval;
1022 }
1023
1024 /***************************************
1025 * IEEE-1394 functionality section END *
1026 ***************************************/
1027
1028
1029 /********************************************************
1030 * Global stuff (interrupt handler, init/shutdown code) *
1031 ********************************************************/
1032
1033 static void dma_trm_reset(struct dma_trm_ctx *d)
1034 {
1035 struct ti_ohci *ohci;
1036 unsigned long flags;
1037 struct hpsb_packet *nextpacket;
1038
1039 if (d==NULL) {
1040 PRINT_G(KERN_ERR, "dma_trm_reset called with NULL arg");
1041 return;
1042 }
1043 ohci = (struct ti_ohci *)(d->ohci);
1044 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
1045
1046 spin_lock_irqsave(&d->lock,flags);
1047
1048 /* Is there still any packet pending in the fifo ? */
1049 while(d->fifo_first) {
1050 PRINT(KERN_INFO, ohci->id,
1051 "AT dma reset ctx=%d, aborting transmission",
1052 d->ctx);
1053 nextpacket = d->fifo_first->xnext;
1054 hpsb_packet_sent(ohci->host, d->fifo_first, ACKX_ABORTED);
1055 d->fifo_first = nextpacket;
1056 }
1057 d->fifo_first = d->fifo_last = NULL;
1058
1059 /* is there still any packet pending ? */
1060 while(d->pending_first) {
1061 PRINT(KERN_INFO, ohci->id,
1062 "AT dma reset ctx=%d, aborting transmission",
1063 d->ctx);
1064 nextpacket = d->pending_first->xnext;
1065 hpsb_packet_sent(ohci->host, d->pending_first,
1066 ACKX_ABORTED);
1067 d->pending_first = nextpacket;
1068 }
1069 d->pending_first = d->pending_last = NULL;
1070
1071 d->branchAddrPtr=NULL;
1072 d->sent_ind = d->prg_ind;
1073 d->free_prgs = d->num_desc;
1074 spin_unlock_irqrestore(&d->lock,flags);
1075 }
1076
1077 static void ohci_irq_handler(int irq, void *dev_id,
1078 struct pt_regs *regs_are_unused)
1079 {
1080 quadlet_t event, node_id;
1081 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
1082 struct hpsb_host *host = ohci->host;
1083 int phyid = -1, isroot = 0;
1084 unsigned long flags;
1085
1086 /* Read the interrupt event register. We don't clear the bus reset
1087 * here. We wait till we get a selfid complete interrupt and clear
1088 * it then, and _only_ then. */
1089 spin_lock_irqsave(&ohci->event_lock, flags);
1090 event = reg_read(ohci, OHCI1394_IntEventClear);
1091 reg_write(ohci, OHCI1394_IntEventClear,
1092 event & ~(OHCI1394_selfIDComplete | OHCI1394_busReset));
1093 spin_unlock_irqrestore(&ohci->event_lock, flags);
1094
1095 if (!event) return;
1096
1097 DBGMSG(ohci->id, "IntEvent: %08x", event);
1098
1099 /* Die right here an now */
1100 if (event & OHCI1394_unrecoverableError) {
1101 PRINT(KERN_ERR, ohci->id, "Unrecoverable error, shutting down card!");
1102 remove_card(ohci);
1103 return;
1104 }
1105
1106 /* Someone wants a bus reset. Better watch what you wish for... */
1107 if (event & OHCI1394_busReset) {
1108 if (!host->in_bus_reset) {
1109 DBGMSG(ohci->id, "irq_handler: Bus reset requested%s",
1110 ((host->attempt_root || attempt_root) ?
1111 " and attempting to become root" : ""));
1112
1113 /* Wait for the AT fifo to be flushed */
1114 dma_trm_reset(ohci->at_req_context);
1115 dma_trm_reset(ohci->at_resp_context);
1116
1117 /* Subsystem call */
1118 hpsb_bus_reset(ohci->host);
1119
1120 ohci->NumBusResets++;
1121 }
1122 /* Mask out everything except selfid */
1123 event &= OHCI1394_selfIDComplete;
1124 }
1125
1126 /* XXX: We need a way to also queue the OHCI1394_reqTxComplete,
1127 * but for right now we simply run it upon reception, to make sure
1128 * we get sent acks before response packets. This sucks mainly
1129 * because it halts the interrupt handler. */
1130 if (event & OHCI1394_reqTxComplete) {
1131 struct dma_trm_ctx *d = ohci->at_req_context;
1132 DBGMSG(ohci->id, "Got reqTxComplete interrupt "
1133 "status=0x%08X", reg_read(ohci, d->ctrlSet));
1134 if (reg_read(ohci, d->ctrlSet) & 0x800)
1135 ohci1394_stop_context(ohci, d->ctrlClear,
1136 "reqTxComplete");
1137 else
1138 dma_trm_tasklet ((unsigned long)d);
1139 event &= ~OHCI1394_reqTxComplete;
1140 }
1141 if (event & OHCI1394_respTxComplete) {
1142 struct dma_trm_ctx *d = ohci->at_resp_context;
1143 DBGMSG(ohci->id, "Got respTxComplete interrupt "
1144 "status=0x%08X", reg_read(ohci, d->ctrlSet));
1145 if (reg_read(ohci, d->ctrlSet) & 0x800)
1146 ohci1394_stop_context(ohci, d->ctrlClear,
1147 "respTxComplete");
1148 else
1149 tasklet_schedule(&d->task);
1150 event &= ~OHCI1394_respTxComplete;
1151 }
1152 if (event & OHCI1394_RQPkt) {
1153 struct dma_rcv_ctx *d = ohci->ar_req_context;
1154 DBGMSG(ohci->id, "Got RQPkt interrupt status=0x%08X",
1155 reg_read(ohci, d->ctrlSet));
1156 if (reg_read(ohci, d->ctrlSet) & 0x800)
1157 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
1158 else
1159 tasklet_schedule(&d->task);
1160 event &= ~OHCI1394_RQPkt;
1161 }
1162 if (event & OHCI1394_RSPkt) {
1163 struct dma_rcv_ctx *d = ohci->ar_resp_context;
1164 DBGMSG(ohci->id, "Got RSPkt interrupt status=0x%08X",
1165 reg_read(ohci, d->ctrlSet));
1166 if (reg_read(ohci, d->ctrlSet) & 0x800)
1167 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
1168 else
1169 tasklet_schedule(&d->task);
1170 event &= ~OHCI1394_RSPkt;
1171 }
1172 if (event & OHCI1394_isochRx) {
1173 quadlet_t isoRecvIntEvent;
1174 struct dma_rcv_ctx *d = ohci->ir_context;
1175 isoRecvIntEvent =
1176 reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
1177 reg_write(ohci, OHCI1394_IsoRecvIntEventClear,
1178 isoRecvIntEvent);
1179 DBGMSG(ohci->id, "Got isochRx interrupt "
1180 "status=0x%08X isoRecvIntEvent=%08x",
1181 reg_read(ohci, d->ctrlSet), isoRecvIntEvent);
1182 if (isoRecvIntEvent & 0x1) {
1183 if (reg_read(ohci, d->ctrlSet) & 0x800)
1184 ohci1394_stop_context(ohci, d->ctrlClear,
1185 "isochRx");
1186 else
1187 tasklet_schedule(&d->task);
1188 }
1189 if (ohci->video_tmpl)
1190 ohci->video_tmpl->irq_handler(ohci->id, isoRecvIntEvent,
1191 0);
1192 event &= ~OHCI1394_isochRx;
1193 }
1194 if (event & OHCI1394_isochTx) {
1195 quadlet_t isoXmitIntEvent;
1196 struct dma_trm_ctx *d = ohci->it_context;
1197 isoXmitIntEvent =
1198 reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
1199 reg_write(ohci, OHCI1394_IsoXmitIntEventClear,
1200 isoXmitIntEvent);
1201 DBGMSG(ohci->id, "Got isochTx interrupt "
1202 "status=0x%08x isoXmitIntEvent=%08x",
1203 reg_read(ohci, d->ctrlSet), isoXmitIntEvent);
1204 if (ohci->video_tmpl)
1205 ohci->video_tmpl->irq_handler(ohci->id, 0,
1206 isoXmitIntEvent);
1207 if (isoXmitIntEvent & 0x1) {
1208 if (reg_read(ohci, d->ctrlSet) & 0x800)
1209 ohci1394_stop_context(ohci, d->ctrlClear, "isochTx");
1210 else
1211 tasklet_schedule(&d->task);
1212 }
1213 event &= ~OHCI1394_isochTx;
1214 }
1215 if (event & OHCI1394_selfIDComplete) {
1216 if (host->in_bus_reset) {
1217 node_id = reg_read(ohci, OHCI1394_NodeID);
1218
1219 /* If our nodeid is not valid, give a msec delay
1220 * to let it settle in and try again. */
1221 if (!(node_id & 0x80000000)) {
1222 mdelay(1);
1223 node_id = reg_read(ohci, OHCI1394_NodeID);
1224 }
1225
1226 if (node_id & 0x80000000) { /* NodeID valid */
1227 phyid = node_id & 0x0000003f;
1228 isroot = (node_id & 0x40000000) != 0;
1229
1230 DBGMSG(ohci->id,
1231 "SelfID interrupt received "
1232 "(phyid %d, %s)", phyid,
1233 (isroot ? "root" : "not root"));
1234
1235 handle_selfid(ohci, host,
1236 phyid, isroot);
1237 } else
1238 PRINT(KERN_ERR, ohci->id,
1239 "SelfID interrupt received, but "
1240 "NodeID is not valid: %08X",
1241 node_id);
1242
1243 /* Accept Physical requests from all nodes. */
1244 reg_write(ohci,OHCI1394_AsReqFilterHiSet,
1245 0xffffffff);
1246 reg_write(ohci,OHCI1394_AsReqFilterLoSet,
1247 0xffffffff);
1248 /* Turn on phys dma reception. We should
1249 * probably manage the filtering somehow,
1250 * instead of blindly turning it on. */
1251 reg_write(ohci,OHCI1394_PhyReqFilterHiSet,
1252 0xffffffff);
1253 reg_write(ohci,OHCI1394_PhyReqFilterLoSet,
1254 0xffffffff);
1255 reg_write(ohci,OHCI1394_PhyUpperBound,
1256 0xffff0000);
1257 } else
1258 PRINT(KERN_ERR, ohci->id,
1259 "SelfID received outside of bus reset sequence");
1260
1261 /* Clear everything, it's a new day */
1262 spin_lock_irqsave(&ohci->event_lock, flags);
1263 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
1264 spin_unlock_irqrestore(&ohci->event_lock, flags);
1265
1266 event &= ~OHCI1394_selfIDComplete;
1267 }
1268 if (event & OHCI1394_phyRegRcvd) {
1269 if (host->in_bus_reset) {
1270 DBGMSG (ohci->id, "PhyControl: %08X",
1271 reg_read(ohci, OHCI1394_PhyControl));
1272 } else
1273 PRINT(KERN_ERR, ohci->id,
1274 "Physical register received outside of bus reset sequence");
1275 event &= ~OHCI1394_phyRegRcvd;
1276 }
1277
1278 /* Make sure we handle everything, just in case we accidentally
1279 * enabled an interrupt that we didn't write a handler for. */
1280 if (event)
1281 PRINT(KERN_ERR, ohci->id, "Unhandled interrupt(s) 0x%08x",
1282 event);
1283 }
1284
1285 /* Put the buffer back into the dma context */
1286 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
1287 {
1288 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1289 DBGMSG(ohci->id, "Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
1290
1291 d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
1292 d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
1293 idx = (idx + d->num_desc - 1 ) % d->num_desc;
1294 d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
1295
1296 /* wake up the dma context if necessary */
1297 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
1298 PRINT(KERN_INFO, ohci->id,
1299 "Waking dma ctx=%d ... processing is probably too slow",
1300 d->ctx);
1301 reg_write(ohci, d->ctrlSet, 0x1000);
1302 }
1303 }
1304
1305 #define cond_le32_to_cpu(data, noswap) \
1306 (noswap ? data : le32_to_cpu(data))
1307
1308 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
1309 -1, 0, -1, 0, -1, -1, 16, -1};
1310
1311 /*
1312 * Determine the length of a packet in the buffer
1313 * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
1314 */
1315 static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
1316 int offset, unsigned char tcode, int noswap)
1317 {
1318 int length = -1;
1319
1320 if (d->ctx < 2) { /* Async Receive Response/Request */
1321 length = TCODE_SIZE[tcode];
1322 if (length == 0) {
1323 if (offset + 12 >= d->buf_size) {
1324 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
1325 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
1326 } else {
1327 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
1328 }
1329 length += 20;
1330 }
1331 } else if (d->ctx == 2) { /* Iso receive */
1332 /* Assumption: buffer fill mode with header/trailer */
1333 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
1334 }
1335
1336 if (length > 0 && length % 4)
1337 length += 4 - (length % 4);
1338
1339 return length;
1340 }
1341
1342 /* Tasklet that processes dma receive buffers */
1343 static void dma_rcv_tasklet (unsigned long data)
1344 {
1345 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
1346 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1347 unsigned int split_left, idx, offset, rescount;
1348 unsigned char tcode;
1349 int length, bytes_left, ack;
1350 unsigned long flags;
1351 quadlet_t *buf_ptr;
1352 char *split_ptr;
1353 char msg[256];
1354
1355 spin_lock_irqsave(&d->lock, flags);
1356
1357 idx = d->buf_ind;
1358 offset = d->buf_offset;
1359 buf_ptr = d->buf_cpu[idx] + offset/4;
1360
1361 dma_cache_wback_inv(&(d->prg_cpu[idx]->status), sizeof(d->prg_cpu[idx]->status));
1362 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
1363
1364 bytes_left = d->buf_size - rescount - offset;
1365 dma_cache_wback_inv(buf_ptr, bytes_left);
1366
1367 while (bytes_left > 0) {
1368 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->payload_swap) >> 4) & 0xf;
1369
1370 /* packet_length() will return < 4 for an error */
1371 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->payload_swap);
1372
1373 if (length < 4) { /* something is wrong */
1374 sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
1375 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->payload_swap),
1376 d->ctx, length);
1377 ohci1394_stop_context(ohci, d->ctrlClear, msg);
1378 spin_unlock_irqrestore(&d->lock, flags);
1379 return;
1380 }
1381
1382 /* The first case is where we have a packet that crosses
1383 * over more than one descriptor. The next case is where
1384 * it's all in the first descriptor. */
1385 if ((offset + length) > d->buf_size) {
1386 DBGMSG(ohci->id,"Split packet rcv'd");
1387 if (length > d->split_buf_size) {
1388 ohci1394_stop_context(ohci, d->ctrlClear,
1389 "Split packet size exceeded");
1390 d->buf_ind = idx;
1391 d->buf_offset = offset;
1392 spin_unlock_irqrestore(&d->lock, flags);
1393 return;
1394 }
1395
1396 if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
1397 == d->buf_size) {
1398 /* Other part of packet not written yet.
1399 * this should never happen I think
1400 * anyway we'll get it on the next call. */
1401 PRINT(KERN_INFO, ohci->id,
1402 "Got only half a packet!");
1403 d->buf_ind = idx;
1404 d->buf_offset = offset;
1405 spin_unlock_irqrestore(&d->lock, flags);
1406 return;
1407 }
1408
1409 split_left = length;
1410 split_ptr = (char *)d->spb;
1411 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
1412 split_left -= d->buf_size-offset;
1413 split_ptr += d->buf_size-offset;
1414 insert_dma_buffer(d, idx);
1415 idx = (idx+1) % d->num_desc;
1416 buf_ptr = d->buf_cpu[idx];
1417 dma_cache_wback_inv(buf_ptr, d->buf_size);
1418 offset=0;
1419
1420 while (split_left >= d->buf_size) {
1421 memcpy(split_ptr,buf_ptr,d->buf_size);
1422 split_ptr += d->buf_size;
1423 split_left -= d->buf_size;
1424 insert_dma_buffer(d, idx);
1425 idx = (idx+1) % d->num_desc;
1426 buf_ptr = d->buf_cpu[idx];
1427 dma_cache_wback_inv(buf_ptr, d->buf_size);
1428 }
1429
1430 if (split_left > 0) {
1431 memcpy(split_ptr, buf_ptr, split_left);
1432 offset = split_left;
1433 buf_ptr += offset/4;
1434 }
1435 } else {
1436 DBGMSG(ohci->id,"Single packet rcv'd");
1437 memcpy(d->spb, buf_ptr, length);
1438 offset += length;
1439 buf_ptr += length/4;
1440 if (offset==d->buf_size) {
1441 insert_dma_buffer(d, idx);
1442 idx = (idx+1) % d->num_desc;
1443 buf_ptr = d->buf_cpu[idx];
1444 offset=0;
1445 }
1446 }
1447
1448 /* We get one phy packet to the async descriptor for each
1449 * bus reset. We always ignore it. */
1450 if (tcode != OHCI1394_TCODE_PHY) {
1451 if (!ohci->payload_swap)
1452 packet_swab(d->spb, tcode, (length - 4) >> 2, 0);
1453
1454 DBGMSG(ohci->id, "Packet received from node"
1455 " %d ack=0x%02X spd=%d tcode=0x%X"
1456 " length=%d ctx=%d tlabel=%d",
1457 (d->spb[1]>>16)&0x3f,
1458 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>16)&0x1f,
1459 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>21)&0x3,
1460 tcode, length, d->ctx,
1461 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>10)&0x3f);
1462
1463 ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>16)&0x1f)
1464 == 0x11) ? 1 : 0;
1465
1466 hpsb_packet_received(ohci->host, d->spb,
1467 length-4, ack);
1468 }
1469 #ifdef OHCI1394_DEBUG
1470 else
1471 PRINT (KERN_DEBUG, ohci->id, "Got phy packet ctx=%d ... discarded",
1472 d->ctx);
1473 #endif
1474
1475 dma_cache_wback_inv(&(d->prg_cpu[idx]->status),
1476 sizeof(d->prg_cpu[idx]->status));
1477 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
1478
1479 bytes_left = d->buf_size - rescount - offset;
1480
1481 }
1482
1483 d->buf_ind = idx;
1484 d->buf_offset = offset;
1485
1486 spin_unlock_irqrestore(&d->lock, flags);
1487 }
1488
1489 /* Bottom half that processes sent packets */
1490 static void dma_trm_tasklet (unsigned long data)
1491 {
1492 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
1493 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1494 struct hpsb_packet *packet, *nextpacket;
1495 unsigned long flags;
1496 u32 ack;
1497 size_t datasize;
1498
1499 spin_lock_irqsave(&d->lock, flags);
1500
1501 if (d->fifo_first == NULL) {
1502 #if 0
1503 ohci1394_stop_context(ohci, d->ctrlClear,
1504 "Packet sent ack received but queue is empty");
1505 #endif
1506 spin_unlock_irqrestore(&d->lock, flags);
1507 return;
1508 }
1509
1510 while (d->fifo_first) {
1511 packet = d->fifo_first;
1512 datasize = d->fifo_first->data_size;
1513 if (datasize && packet->type != raw)
1514 ack = le32_to_cpu(
1515 d->prg_cpu[d->sent_ind]->end.status) >> 16;
1516 else
1517 ack = le32_to_cpu(
1518 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
1519
1520 if (ack == 0)
1521 /* this packet hasn't been sent yet*/
1522 break;
1523
1524 #ifdef OHCI1394_DEBUG
1525 if (datasize)
1526 DBGMSG(ohci->id,
1527 "Packet sent to node %d tcode=0x%X tLabel="
1528 "0x%02X ack=0x%X spd=%d dataLength=%d ctx=%d",
1529 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
1530 >>16)&0x3f,
1531 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1532 >>4)&0xf,
1533 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1534 >>10)&0x3f,
1535 ack&0x1f, (ack>>5)&0x3,
1536 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])
1537 >>16,
1538 d->ctx);
1539 else
1540 DBGMSG(ohci->id,
1541 "Packet sent to node %d tcode=0x%X tLabel="
1542 "0x%02X ack=0x%X spd=%d data=0x%08X ctx=%d",
1543 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
1544 >>16)&0x3f,
1545 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1546 >>4)&0xf,
1547 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1548 >>10)&0x3f,
1549 ack&0x1f, (ack>>5)&0x3,
1550 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
1551 d->ctx);
1552 #endif
1553
1554 nextpacket = packet->xnext;
1555 hpsb_packet_sent(ohci->host, packet, ack & 0xf);
1556
1557 if (datasize) {
1558 pci_unmap_single(ohci->dev,
1559 cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
1560 datasize, PCI_DMA_TODEVICE);
1561 OHCI_DMA_FREE("single Xmit data packet");
1562 }
1563
1564 d->sent_ind = (d->sent_ind+1)%d->num_desc;
1565 d->free_prgs++;
1566 d->fifo_first = nextpacket;
1567 }
1568 if (d->fifo_first == NULL)
1569 d->fifo_last = NULL;
1570
1571 dma_trm_flush(ohci, d);
1572
1573 spin_unlock_irqrestore(&d->lock, flags);
1574 }
1575
1576 static int free_dma_rcv_ctx(struct dma_rcv_ctx **d)
1577 {
1578 int i;
1579 struct ti_ohci *ohci;
1580
1581 if (*d==NULL) return -1;
1582
1583 ohci = (struct ti_ohci *)(*d)->ohci;
1584
1585 DBGMSG(ohci->id, "Freeing dma_rcv_ctx %d",(*d)->ctx);
1586
1587 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1588
1589 tasklet_kill(&(*d)->task);
1590
1591 if ((*d)->buf_cpu) {
1592 for (i=0; i<(*d)->num_desc; i++)
1593 if ((*d)->buf_cpu[i] && (*d)->buf_bus[i]) {
1594 pci_free_consistent(
1595 ohci->dev, (*d)->buf_size,
1596 (*d)->buf_cpu[i], (*d)->buf_bus[i]);
1597 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
1598 }
1599 kfree((*d)->buf_cpu);
1600 kfree((*d)->buf_bus);
1601 }
1602 if ((*d)->prg_cpu) {
1603 for (i=0; i<(*d)->num_desc; i++)
1604 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i]) {
1605 pci_free_consistent(
1606 ohci->dev, sizeof(struct dma_cmd),
1607 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1608 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
1609 }
1610 kfree((*d)->prg_cpu);
1611 kfree((*d)->prg_bus);
1612 }
1613 if ((*d)->spb) kfree((*d)->spb);
1614
1615 kfree(*d);
1616 *d = NULL;
1617
1618 return 0;
1619 }
1620
1621 static struct dma_rcv_ctx *
1622 alloc_dma_rcv_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1623 int buf_size, int split_buf_size,
1624 int ctrlSet, int ctrlClear, int cmdPtr)
1625 {
1626 struct dma_rcv_ctx *d=NULL;
1627 int i;
1628
1629 d = (struct dma_rcv_ctx *)kmalloc(sizeof(struct dma_rcv_ctx),
1630 GFP_KERNEL);
1631
1632 if (d == NULL) {
1633 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma_rcv_ctx");
1634 return NULL;
1635 }
1636
1637 memset (d, 0, sizeof (struct dma_rcv_ctx));
1638
1639 d->ohci = (void *)ohci;
1640 d->ctx = ctx;
1641
1642 d->num_desc = num_desc;
1643 d->buf_size = buf_size;
1644 d->split_buf_size = split_buf_size;
1645 d->ctrlSet = ctrlSet;
1646 d->ctrlClear = ctrlClear;
1647 d->cmdPtr = cmdPtr;
1648
1649 d->buf_cpu = NULL;
1650 d->buf_bus = NULL;
1651 d->prg_cpu = NULL;
1652 d->prg_bus = NULL;
1653 d->spb = NULL;
1654
1655 d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_KERNEL);
1656 d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1657
1658 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
1659 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma buffer");
1660 free_dma_rcv_ctx(&d);
1661 return NULL;
1662 }
1663 memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
1664 memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
1665
1666 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*),
1667 GFP_KERNEL);
1668 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1669
1670 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1671 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma prg");
1672 free_dma_rcv_ctx(&d);
1673 return NULL;
1674 }
1675 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
1676 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1677
1678 d->spb = kmalloc(d->split_buf_size, GFP_KERNEL);
1679
1680 if (d->spb == NULL) {
1681 PRINT(KERN_ERR, ohci->id, "Failed to allocate split buffer");
1682 free_dma_rcv_ctx(&d);
1683 return NULL;
1684 }
1685
1686 for (i=0; i<d->num_desc; i++) {
1687 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
1688 d->buf_size,
1689 d->buf_bus+i);
1690 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
1691
1692 if (d->buf_cpu[i] != NULL) {
1693 memset(d->buf_cpu[i], 0, d->buf_size);
1694 } else {
1695 PRINT(KERN_ERR, ohci->id,
1696 "Failed to allocate dma buffer");
1697 free_dma_rcv_ctx(&d);
1698 return NULL;
1699 }
1700
1701
1702 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1703 sizeof(struct dma_cmd),
1704 d->prg_bus+i);
1705 OHCI_DMA_ALLOC("consistent dma_rcv prg[%d]", i);
1706
1707 if (d->prg_cpu[i] != NULL) {
1708 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
1709 } else {
1710 PRINT(KERN_ERR, ohci->id,
1711 "Failed to allocate dma prg");
1712 free_dma_rcv_ctx(&d);
1713 return NULL;
1714 }
1715 }
1716
1717 spin_lock_init(&d->lock);
1718
1719 /* initialize tasklet */
1720 tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long)d);
1721
1722 return d;
1723 }
1724
1725 static int free_dma_trm_ctx(struct dma_trm_ctx **d)
1726 {
1727 struct ti_ohci *ohci;
1728 int i;
1729
1730 if (*d==NULL) return -1;
1731
1732 ohci = (struct ti_ohci *)(*d)->ohci;
1733
1734 DBGMSG(ohci->id, "Freeing dma_trm_ctx %d",(*d)->ctx);
1735
1736 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1737
1738 tasklet_kill(&(*d)->task);
1739
1740 if ((*d)->prg_cpu) {
1741 for (i=0; i<(*d)->num_desc; i++)
1742 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i]) {
1743 pci_free_consistent(
1744 ohci->dev, sizeof(struct at_dma_prg),
1745 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1746 OHCI_DMA_FREE("consistent dma_trm prg[%d]", i);
1747 }
1748 kfree((*d)->prg_cpu);
1749 kfree((*d)->prg_bus);
1750 }
1751
1752 kfree(*d);
1753 *d = NULL;
1754 return 0;
1755 }
1756
1757 static struct dma_trm_ctx *
1758 alloc_dma_trm_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1759 int ctrlSet, int ctrlClear, int cmdPtr)
1760 {
1761 struct dma_trm_ctx *d=NULL;
1762 int i;
1763
1764 d = (struct dma_trm_ctx *)kmalloc(sizeof(struct dma_trm_ctx),
1765 GFP_KERNEL);
1766
1767 if (d==NULL) {
1768 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma_trm_ctx");
1769 return NULL;
1770 }
1771
1772 memset (d, 0, sizeof (struct dma_trm_ctx));
1773
1774 d->ohci = (void *)ohci;
1775 d->ctx = ctx;
1776 d->num_desc = num_desc;
1777 d->ctrlSet = ctrlSet;
1778 d->ctrlClear = ctrlClear;
1779 d->cmdPtr = cmdPtr;
1780 d->prg_cpu = NULL;
1781 d->prg_bus = NULL;
1782
1783 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*),
1784 GFP_KERNEL);
1785 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1786
1787 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1788 PRINT(KERN_ERR, ohci->id, "Failed to allocate at dma prg");
1789 free_dma_trm_ctx(&d);
1790 return NULL;
1791 }
1792 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
1793 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1794
1795 for (i=0; i<d->num_desc; i++) {
1796 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1797 sizeof(struct at_dma_prg),
1798 d->prg_bus+i);
1799 OHCI_DMA_ALLOC("consistent dma_trm prg[%d]", i);
1800
1801 if (d->prg_cpu[i] != NULL) {
1802 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
1803 } else {
1804 PRINT(KERN_ERR, ohci->id,
1805 "Failed to allocate at dma prg");
1806 free_dma_trm_ctx(&d);
1807 return NULL;
1808 }
1809 }
1810
1811 spin_lock_init(&d->lock);
1812
1813 /* initialize bottom handler */
1814 tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
1815
1816 return d;
1817 }
1818
1819 static u16 ohci_crc16 (u32 *ptr, int length)
1820 {
1821 int shift;
1822 u32 crc, sum, data;
1823
1824 crc = 0;
1825 for (; length > 0; length--) {
1826 data = *ptr++;
1827 for (shift = 28; shift >= 0; shift -= 4) {
1828 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f;
1829 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum;
1830 }
1831 crc &= 0xffff;
1832 }
1833 return crc;
1834 }
1835
1836 /* Config ROM macro implementation influenced by NetBSD OHCI driver */
1837
1838 struct config_rom_unit {
1839 u32 *start;
1840 u32 *refer;
1841 int length;
1842 int refunit;
1843 };
1844
1845 struct config_rom_ptr {
1846 u32 *data;
1847 int unitnum;
1848 struct config_rom_unit unitdir[10];
1849 };
1850
1851 #define cf_put_1quad(cr, q) (((cr)->data++)[0] = cpu_to_be32(q))
1852
1853 #define cf_put_4bytes(cr, b1, b2, b3, b4) \
1854 (((cr)->data++)[0] = cpu_to_be32(((b1) << 24) | ((b2) << 16) | ((b3) << 8) | (b4)))
1855
1856 #define cf_put_keyval(cr, key, val) (((cr)->data++)[0] = cpu_to_be32(((key) << 24) | (val)))
1857
1858 static inline void cf_put_crc16(struct config_rom_ptr *cr, int unit)
1859 {
1860 *cr->unitdir[unit].start =
1861 cpu_to_be32((cr->unitdir[unit].length << 16) |
1862 ohci_crc16(cr->unitdir[unit].start + 1,
1863 cr->unitdir[unit].length));
1864 }
1865
1866 static inline void cf_unit_begin(struct config_rom_ptr *cr, int unit)
1867 {
1868 if (cr->unitdir[unit].refer != NULL) {
1869 *cr->unitdir[unit].refer |=
1870 cpu_to_be32 (cr->data - cr->unitdir[unit].refer);
1871 cf_put_crc16(cr, cr->unitdir[unit].refunit);
1872 }
1873 cr->unitnum = unit;
1874 cr->unitdir[unit].start = cr->data++;
1875 }
1876
1877 static inline void cf_put_refer(struct config_rom_ptr *cr, char key, int unit)
1878 {
1879 cr->unitdir[unit].refer = cr->data;
1880 cr->unitdir[unit].refunit = cr->unitnum;
1881 (cr->data++)[0] = cpu_to_be32(key << 24);
1882 }
1883
1884 static inline void cf_unit_end(struct config_rom_ptr *cr)
1885 {
1886 cr->unitdir[cr->unitnum].length = cr->data -
1887 (cr->unitdir[cr->unitnum].start + 1);
1888 cf_put_crc16(cr, cr->unitnum);
1889 }
1890
1891 /* End of NetBSD derived code. */
1892
1893 static void ohci_init_config_rom(struct ti_ohci *ohci)
1894 {
1895 struct config_rom_ptr cr;
1896
1897 memset(&cr, 0, sizeof(cr));
1898 memset(ohci->csr_config_rom_cpu, 0, sizeof (ohci->csr_config_rom_cpu));
1899
1900 cr.data = ohci->csr_config_rom_cpu;
1901
1902 /* Bus info block */
1903 cf_unit_begin(&cr, 0);
1904 cf_put_1quad(&cr, reg_read(ohci, OHCI1394_BusID));
1905 cf_put_1quad(&cr, reg_read(ohci, OHCI1394_BusOptions));
1906 cf_put_1quad(&cr, reg_read(ohci, OHCI1394_GUIDHi));
1907 cf_put_1quad(&cr, reg_read(ohci, OHCI1394_GUIDLo));
1908 cf_unit_end(&cr);
1909
1910 DBGMSG(ohci->id, "GUID: %08x:%08x", reg_read(ohci, OHCI1394_GUIDHi),
1911 reg_read(ohci, OHCI1394_GUIDLo));
1912
1913 /* IEEE P1212 suggests the initial ROM header CRC should only
1914 * cover the header itself (and not the entire ROM). Since we do
1915 * this, then we can make our bus_info_len the same as the CRC
1916 * length. */
1917 ohci->csr_config_rom_cpu[0] |= cpu_to_be32(
1918 (be32_to_cpu(ohci->csr_config_rom_cpu[0]) & 0x00ff0000) << 8);
1919 reg_write(ohci, OHCI1394_ConfigROMhdr,
1920 be32_to_cpu(ohci->csr_config_rom_cpu[0]));
1921
1922 /* Root directory */
1923 cf_unit_begin(&cr, 1);
1924 cf_put_keyval(&cr, 0x03, 0x00005e); /* Vendor ID */
1925 cf_put_refer(&cr, 0x81, 2); /* Textual description unit */
1926 cf_put_keyval(&cr, 0x0c, 0x0083c0); /* Node capabilities */
1927 cf_put_refer(&cr, 0xd1, 3); /* IPv4 unit directory */
1928 cf_put_refer(&cr, 0xd1, 4); /* IPv6 unit directory */
1929 /* NOTE: Add other unit referers here, and append at bottom */
1930 cf_unit_end(&cr);
1931
1932 /* Textual description - "Linux 1394" */
1933 cf_unit_begin(&cr, 2);
1934 cf_put_keyval(&cr, 0, 0);
1935 cf_put_1quad(&cr, 0);
1936 cf_put_4bytes(&cr, 'L', 'i', 'n', 'u');
1937 cf_put_4bytes(&cr, 'x', ' ', '1', '3');
1938 cf_put_4bytes(&cr, '9', '4', 0x0, 0x0);
1939 cf_unit_end(&cr);
1940
1941 /* IPv4 unit directory, RFC 2734 */
1942 cf_unit_begin(&cr, 3);
1943 cf_put_keyval(&cr, 0x12, 0x00005e); /* Unit spec ID */
1944 cf_put_refer(&cr, 0x81, 6); /* Textual description unit */
1945 cf_put_keyval(&cr, 0x13, 0x000001); /* Unit software version */
1946 cf_put_refer(&cr, 0x81, 7); /* Textual description unit */
1947 cf_unit_end(&cr);
1948
1949 cf_unit_begin(&cr, 6);
1950 cf_put_keyval(&cr, 0, 0);
1951 cf_put_1quad(&cr, 0);
1952 cf_put_4bytes(&cr, 'I', 'A', 'N', 'A');
1953 cf_unit_end(&cr);
1954
1955 cf_unit_begin(&cr, 7);
1956 cf_put_keyval(&cr, 0, 0);
1957 cf_put_1quad(&cr, 0);
1958 cf_put_4bytes(&cr, 'I', 'P', 'v', '4');
1959 cf_unit_end(&cr);
1960
1961 /* IPv6 unit directory, draft-ietf-ipngwg-1394-01.txt */
1962 cf_unit_begin(&cr, 4);
1963 cf_put_keyval(&cr, 0x12, 0x00005e); /* Unit spec ID */
1964 cf_put_refer(&cr, 0x81, 8); /* Textual description unit */
1965 cf_put_keyval(&cr, 0x13, 0x000002); /* (Proposed) Unit software version */
1966 cf_put_refer(&cr, 0x81, 9); /* Textual description unit */
1967 cf_unit_end(&cr);
1968
1969 cf_unit_begin(&cr, 8);
1970 cf_put_keyval(&cr, 0, 0);
1971 cf_put_1quad(&cr, 0);
1972 cf_put_4bytes(&cr, 'I', 'A', 'N', 'A');
1973 cf_unit_end(&cr);
1974
1975 cf_unit_begin(&cr, 9);
1976 cf_put_keyval(&cr, 0, 0);
1977 cf_put_1quad(&cr, 0);
1978 cf_put_4bytes(&cr, 'I', 'P', 'v', '6');
1979 cf_unit_end(&cr);
1980
1981 ohci->csr_config_rom_length = cr.data - ohci->csr_config_rom_cpu;
1982 }
1983
1984 static size_t ohci_get_rom(struct hpsb_host *host, const quadlet_t **ptr)
1985 {
1986 struct ti_ohci *ohci=host->hostdata;
1987
1988 DBGMSG(ohci->id, "request csr_rom address: %p",
1989 ohci->csr_config_rom_cpu);
1990
1991 *ptr = ohci->csr_config_rom_cpu;
1992
1993 return ohci->csr_config_rom_length * 4;
1994 }
1995
1996 int ohci_compare_swap(struct ti_ohci *ohci, quadlet_t *data,
1997 quadlet_t compare, int sel)
1998 {
1999 int i;
2000 reg_write(ohci, OHCI1394_CSRData, *data);
2001 reg_write(ohci, OHCI1394_CSRCompareData, compare);
2002 reg_write(ohci, OHCI1394_CSRControl, sel & 0x3);
2003
2004 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
2005 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
2006 break;
2007
2008 mdelay(1);
2009 }
2010
2011 *data = reg_read(ohci, OHCI1394_CSRData);
2012 return 0;
2013 }
2014
2015 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
2016 quadlet_t data, quadlet_t compare)
2017 {
2018 struct ti_ohci *ohci=host->hostdata;
2019
2020 ohci_compare_swap (ohci, &data, compare, reg);
2021
2022 return data;
2023 }
2024
2025 static struct hpsb_host_template ohci_template = {
2026 name: OHCI1394_DRIVER_NAME,
2027 initialize_host: ohci_initialize,
2028 release_host: ohci_remove,
2029 get_rom: ohci_get_rom,
2030 transmit_packet: ohci_transmit,
2031 devctl: ohci_devctl,
2032 hw_csr_reg: ohci_hw_csr_reg,
2033 };
2034
2035 static int __devinit ohci1394_add_one(struct pci_dev *dev, const struct pci_device_id *ent)
2036 {
2037 struct ti_ohci *ohci; /* shortcut to currently handled device */
2038 struct hpsb_host *host;
2039 unsigned long ohci_base, ohci_len;
2040 static int version_printed = 0;
2041
2042 if (version_printed++ == 0)
2043 PRINT_G(KERN_INFO, "%s", version);
2044
2045 if (pci_enable_device(dev)) {
2046 /* Skip ID's that fail */
2047 PRINT_G(KERN_NOTICE, "Failed to enable OHCI hardware %d",
2048 card_id_counter++);
2049 return -ENXIO;
2050 }
2051 pci_set_master(dev);
2052
2053 host = hpsb_get_host(&ohci_template, sizeof (struct ti_ohci));
2054 if (!host) {
2055 PRINT_G(KERN_ERR, "Out of memory trying to allocate host structure");
2056 return -ENOMEM;
2057 }
2058 ohci = host->hostdata;
2059 ohci->host = host;
2060 INIT_LIST_HEAD(&ohci->list);
2061 ohci->id = card_id_counter++;
2062 ohci->dev = dev;
2063 host->pdev = dev;
2064 ohci->host = host;
2065 pci_set_drvdata(dev, ohci);
2066
2067 /* We don't want hardware swapping */
2068 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2069
2070 /* Some oddball Apple controllers do not order the selfid
2071 * properly, so we make up for it here. */
2072 #ifndef __LITTLE_ENDIAN
2073 /* XXX: Need a better way to check this. I'm wondering if we can
2074 * read the values of the OHCI1394_PCI_HCI_Control and the
2075 * noByteSwapData registers to see if they were not cleared to
2076 * zero. Should this work? Obviously it's not defined what these
2077 * registers will read when they aren't supported. Bleh! */
2078 if (dev->vendor == PCI_VENDOR_ID_APPLE) {
2079 ohci->payload_swap = 1;
2080 if (dev->device != PCI_DEVICE_ID_APPLE_UNI_N_FW)
2081 ohci->selfid_swap = 1;
2082 } else
2083 ohci->selfid_swap = 1;
2084 #endif
2085
2086 /* csr_config rom allocation */
2087 ohci->csr_config_rom_cpu =
2088 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
2089 &ohci->csr_config_rom_bus);
2090 OHCI_DMA_ALLOC("consistent csr_config_rom");
2091 if (ohci->csr_config_rom_cpu == NULL)
2092 FAIL("Failed to allocate buffer config rom");
2093
2094 /*
2095 * self-id dma buffer allocation
2096 */
2097 ohci->selfid_buf_cpu =
2098 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
2099 &ohci->selfid_buf_bus);
2100 OHCI_DMA_ALLOC("consistent selfid_buf");
2101 if (ohci->selfid_buf_cpu == NULL)
2102 FAIL("Failed to allocate DMA buffer for self-id packets");
2103
2104 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
2105 PRINT(KERN_INFO, ohci->id, "SelfID buffer %p is not aligned on "
2106 "8Kb boundary... may cause problems on some CXD3222 chip",
2107 ohci->selfid_buf_cpu);
2108
2109 ohci->it_context =
2110 alloc_dma_trm_ctx(ohci, 2, IT_NUM_DESC,
2111 OHCI1394_IsoXmitContextControlSet,
2112 OHCI1394_IsoXmitContextControlClear,
2113 OHCI1394_IsoXmitCommandPtr);
2114
2115 if (ohci->it_context == NULL)
2116 FAIL("Failed to allocate IT context");
2117
2118 ohci_base = pci_resource_start(dev, 0);
2119 ohci_len = pci_resource_len(dev, 0);
2120
2121 if (!request_mem_region (ohci_base, ohci_len, host->template->name))
2122 FAIL("MMIO resource (0x%lx@0x%lx) unavailable, aborting.",
2123 ohci_base, ohci_len);
2124
2125 ohci->registers = ioremap(ohci_base, ohci_len);
2126
2127 if (ohci->registers == NULL)
2128 FAIL("Failed to remap registers - card not accessible");
2129
2130 DBGMSG(ohci->id, "Remapped memory spaces reg 0x%p",
2131 ohci->registers);
2132
2133 ohci->ar_req_context =
2134 alloc_dma_rcv_ctx(ohci, 0, AR_REQ_NUM_DESC,
2135 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
2136 OHCI1394_AsReqRcvContextControlSet,
2137 OHCI1394_AsReqRcvContextControlClear,
2138 OHCI1394_AsReqRcvCommandPtr);
2139
2140 if (ohci->ar_req_context == NULL)
2141 FAIL("Failed to allocate AR Req context");
2142
2143 ohci->ar_resp_context =
2144 alloc_dma_rcv_ctx(ohci, 1, AR_RESP_NUM_DESC,
2145 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
2146 OHCI1394_AsRspRcvContextControlSet,
2147 OHCI1394_AsRspRcvContextControlClear,
2148 OHCI1394_AsRspRcvCommandPtr);
2149
2150 if (ohci->ar_resp_context == NULL)
2151 FAIL("Failed to allocate AR Resp context");
2152
2153 ohci->at_req_context =
2154 alloc_dma_trm_ctx(ohci, 0, AT_REQ_NUM_DESC,
2155 OHCI1394_AsReqTrContextControlSet,
2156 OHCI1394_AsReqTrContextControlClear,
2157 OHCI1394_AsReqTrCommandPtr);
2158
2159 if (ohci->at_req_context == NULL)
2160 FAIL("Failed to allocate AT Req context");
2161
2162 ohci->at_resp_context =
2163 alloc_dma_trm_ctx(ohci, 1, AT_RESP_NUM_DESC,
2164 OHCI1394_AsRspTrContextControlSet,
2165 OHCI1394_AsRspTrContextControlClear,
2166 OHCI1394_AsRspTrCommandPtr);
2167
2168 if (ohci->at_resp_context == NULL)
2169 FAIL("Failed to allocate AT Resp context");
2170
2171 ohci->ir_context =
2172 alloc_dma_rcv_ctx(ohci, 2, IR_NUM_DESC,
2173 IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
2174 OHCI1394_IsoRcvContextControlSet,
2175 OHCI1394_IsoRcvContextControlClear,
2176 OHCI1394_IsoRcvCommandPtr);
2177
2178 if (ohci->ir_context == NULL)
2179 FAIL("Failed to allocate IR context");
2180
2181 ohci->ISO_channel_usage = 0;
2182 spin_lock_init(&ohci->IR_channel_lock);
2183
2184 if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
2185 OHCI1394_DRIVER_NAME, ohci))
2186 FAIL("Failed to allocate shared interrupt %d", dev->irq);
2187
2188 /* Tell the highlevel this host is ready */
2189 highlevel_add_one_host (host);
2190
2191 return 0;
2192 #undef FAIL
2193 }
2194
2195 static void remove_card(struct ti_ohci *ohci)
2196 {
2197 quadlet_t buf;
2198
2199 /* Soft reset before we start */
2200 ohci_soft_reset(ohci);
2201
2202 /* Free AR dma */
2203 free_dma_rcv_ctx(&ohci->ar_req_context);
2204 free_dma_rcv_ctx(&ohci->ar_resp_context);
2205
2206 /* Free AT dma */
2207 free_dma_trm_ctx(&ohci->at_req_context);
2208 free_dma_trm_ctx(&ohci->at_resp_context);
2209
2210 /* Free IR dma */
2211 free_dma_rcv_ctx(&ohci->ir_context);
2212
2213 /* Free IT dma */
2214 free_dma_trm_ctx(&ohci->it_context);
2215
2216 /* Disable all interrupts */
2217 reg_write(ohci, OHCI1394_IntMaskClear, 0x80000000);
2218 free_irq(ohci->dev->irq, ohci);
2219
2220 /* Free self-id buffer */
2221 if (ohci->selfid_buf_cpu) {
2222 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
2223 ohci->selfid_buf_cpu,
2224 ohci->selfid_buf_bus);
2225 OHCI_DMA_FREE("consistent selfid_buf");
2226 }
2227
2228 /* Free config rom */
2229 if (ohci->csr_config_rom_cpu) {
2230 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
2231 ohci->csr_config_rom_cpu,
2232 ohci->csr_config_rom_bus);
2233 OHCI_DMA_FREE("consistent csr_config_rom");
2234 }
2235
2236 /* Disable our bus options */
2237 buf = reg_read(ohci, OHCI1394_BusOptions);
2238 buf &= ~0xf8000000;
2239 buf |= 0x00ff0000;
2240 reg_write(ohci, OHCI1394_BusOptions, buf);
2241
2242 /* Clear LinkEnable and LPS */
2243 reg_write(ohci, OHCI1394_HCControlClear, 0x000a0000);
2244
2245 if (ohci->registers)
2246 iounmap(ohci->registers);
2247
2248 release_mem_region (pci_resource_start(ohci->dev, 0),
2249 pci_resource_len(ohci->dev, 0));
2250
2251 pci_set_drvdata(ohci->dev, NULL);
2252 }
2253
2254 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
2255 {
2256 int i=0;
2257
2258 /* stop the channel program if it's still running */
2259 reg_write(ohci, reg, 0x8000);
2260
2261 /* Wait until it effectively stops */
2262 while (reg_read(ohci, reg) & 0x400) {
2263 i++;
2264 if (i>5000) {
2265 PRINT(KERN_ERR, ohci->id,
2266 "Runaway loop while stopping context...");
2267 break;
2268 }
2269 }
2270 if (msg) PRINT(KERN_ERR, ohci->id, "%s: dma prg stopped", msg);
2271 }
2272
2273 int ohci1394_register_video(struct ti_ohci *ohci,
2274 struct video_template *tmpl)
2275 {
2276 if (ohci->video_tmpl)
2277 return -ENFILE;
2278 ohci->video_tmpl = tmpl;
2279 MOD_INC_USE_COUNT;
2280 return 0;
2281 }
2282
2283 void ohci1394_unregister_video(struct ti_ohci *ohci,
2284 struct video_template *tmpl)
2285 {
2286 if (ohci->video_tmpl != tmpl) {
2287 PRINT(KERN_ERR, ohci->id,
2288 "Trying to unregister wrong video device");
2289 } else {
2290 ohci->video_tmpl = NULL;
2291 MOD_DEC_USE_COUNT;
2292 }
2293 }
2294
2295 #ifndef __LITTLE_ENDIAN
2296
2297 /* Swap a series of quads inplace. */
2298 static __inline__ void block_swab32(quadlet_t *data, size_t size) {
2299 while (size--)
2300 data[size] = swab32(data[size]);
2301 }
2302
2303 /* Swap headers and sometimes data too */
2304 static void packet_swab(quadlet_t *data, char tcode, int len, int payload_swap)
2305 {
2306 if (payload_swap) {
2307 block_swab32(data, len);
2308 return;
2309 }
2310
2311 switch(tcode)
2312 {
2313 /* 4 quad header */
2314 case TCODE_READB_RESPONSE:
2315 case TCODE_LOCK_RESPONSE:
2316 case TCODE_LOCK_REQUEST:
2317 case TCODE_WRITEB:
2318 case TCODE_READB:
2319 block_swab32(data, 4);
2320 break;
2321
2322 /* 3 quad header, 1 quad payload */
2323 case TCODE_WRITEQ:
2324 case TCODE_READQ_RESPONSE:
2325 block_swab32(data, 3);
2326 break;
2327
2328 /* 3 quad header */
2329 case TCODE_WRITE_RESPONSE:
2330 case TCODE_READQ:
2331 block_swab32(data, 3);
2332 break;
2333
2334 /* 2 quad header */
2335 case TCODE_ISO_DATA:
2336 block_swab32(data, 2);
2337 break;
2338
2339 case OHCI1394_TCODE_PHY:
2340 break; /* should never happen anyway */
2341
2342 case TCODE_CYCLE_START:
2343 PRINT_G(KERN_ERR, "Unhandled tcode in packet_swab (0x%x)", tcode);
2344 /* Atleast swap one quad */
2345 block_swab32(data, 1);
2346 break;
2347 default:
2348 PRINT_G(KERN_ERR, "Invalid tcode in packet_swab (0x%x)", tcode);
2349 break;
2350 }
2351 return;
2352 }
2353
2354 #endif /* !LITTLE_ENDIAN */
2355
2356
2357 #if 0
2358 int ohci1394_request_channel(struct ti_ohci *ohci, int channel)
2359 {
2360 int csrSel;
2361 quadlet_t chan, data1=0, data2=0;
2362 int timeout = 32;
2363
2364 if (channel<32) {
2365 chan = 1<<channel;
2366 csrSel = 2;
2367 }
2368 else {
2369 chan = 1<<(channel-32);
2370 csrSel = 3;
2371 }
2372 if (ohci_compare_swap(ohci, &data1, 0, csrSel)<0) {
2373 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2374 return -1;
2375 }
2376 while (timeout--) {
2377 if (data1 & chan) {
2378 PRINT(KERN_INFO, ohci->id,
2379 "request channel %d failed", channel);
2380 return -1;
2381 }
2382 data2 = data1;
2383 data1 |= chan;
2384 if (ohci_compare_swap(ohci, &data1, data2, csrSel)<0) {
2385 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2386 return -1;
2387 }
2388 if (data1==data2) {
2389 PRINT(KERN_INFO, ohci->id,
2390 "request channel %d succeded", channel);
2391 return 0;
2392 }
2393 }
2394 PRINT(KERN_INFO, ohci->id, "request channel %d failed", channel);
2395 return -1;
2396 }
2397 #endif
2398
2399 EXPORT_SYMBOL(ohci1394_stop_context);
2400 EXPORT_SYMBOL(ohci1394_register_video);
2401 EXPORT_SYMBOL(ohci1394_unregister_video);
2402
2403 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
2404 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
2405
2406 static void __devexit ohci1394_remove_one(struct pci_dev *pdev)
2407 {
2408 struct ti_ohci *ohci = pci_get_drvdata(pdev);
2409
2410 if (ohci) {
2411 remove_card (ohci);
2412 pci_set_drvdata(pdev, NULL);
2413 }
2414 }
2415
2416 static struct pci_driver ohci1394_driver = {
2417 name: OHCI1394_DRIVER_NAME,
2418 id_table: ohci1394_pci_tbl,
2419 probe: ohci1394_add_one,
2420 remove: ohci1394_remove_one,
2421 };
2422
2423 static void __exit ohci1394_cleanup (void)
2424 {
2425 hpsb_unregister_lowlevel(&ohci_template);
2426 pci_unregister_driver(&ohci1394_driver);
2427 }
2428
2429 static int __init ohci1394_init(void)
2430 {
2431 int ret;
2432 if (hpsb_register_lowlevel(&ohci_template)) {
2433 PRINT_G(KERN_ERR, "Registering failed");
2434 return -ENXIO;
2435 }
2436 if ((ret = pci_module_init(&ohci1394_driver))) {
2437 PRINT_G(KERN_ERR, "PCI module init failed");
2438 hpsb_unregister_lowlevel(&ohci_template);
2439 return ret;
2440 }
2441 return ret;
2442 }
2443
2444 module_init(ohci1394_init);
2445 module_exit(ohci1394_cleanup);
2446