File: /usr/src/linux/drivers/ieee1394/pcilynx.h
1 #include <linux/config.h>
2
3 #define PCILYNX_DRIVER_NAME "pcilynx"
4 #define PCILYNX_MAJOR 177
5
6 #define PCILYNX_MINOR_AUX_START 0
7 #define PCILYNX_MINOR_ROM_START 16
8 #define PCILYNX_MINOR_RAM_START 32
9
10 #define PCILYNX_MAX_REGISTER 0xfff
11 #define PCILYNX_MAX_MEMORY 0xffff
12
13 #define PCI_DEVICE_ID_TI_PCILYNX 0x8000
14 #define MAX_PCILYNX_CARDS 4
15 #define LOCALRAM_SIZE 4096
16
17 #define NUM_ISORCV_PCL 4
18 #define MAX_ISORCV_SIZE 2048
19 #define ISORCV_PER_PAGE (PAGE_SIZE / MAX_ISORCV_SIZE)
20 #define ISORCV_PAGES (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
21
22 #define CHANNEL_LOCALBUS 0
23 #define CHANNEL_ASYNC_RCV 1
24 #define CHANNEL_ISO_RCV 2
25 #define CHANNEL_ASYNC_SEND 3
26 #define CHANNEL_ISO_SEND 4
27
28 typedef int pcl_t;
29
30 struct ti_lynx {
31 int id; /* sequential card number */
32
33 spinlock_t lock;
34
35 struct pci_dev *dev;
36
37 struct {
38 unsigned reg_1394a:1;
39 u32 vendor;
40 u32 product;
41 } phyic;
42
43 enum { clear, have_host_struct, have_intr, have_aux_buf, have_pcl_mem,
44 have_1394_buffers, have_iomappings } state;
45
46 /* remapped memory spaces */
47 void *registers;
48 void *local_rom;
49 void *local_ram;
50 void *aux_port;
51
52
53 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
54 atomic_t aux_intr_seen;
55 wait_queue_head_t aux_intr_wait;
56
57 void *mem_dma_buffer;
58 dma_addr_t mem_dma_buffer_dma;
59 struct semaphore mem_dma_mutex;
60 wait_queue_head_t mem_dma_intr_wait;
61 #endif
62
63 /*
64 * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
65 * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
66 * the following is an allocation bitmap
67 */
68 u8 pcl_bmap[LOCALRAM_SIZE / 1024];
69
70 #ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
71 /* point to PCLs memory area if needed */
72 void *pcl_mem;
73 dma_addr_t pcl_mem_dma;
74 #endif
75
76 /* PCLs for local mem / aux transfers */
77 pcl_t dmem_pcl;
78
79 /* IEEE-1394 part follows */
80 struct hpsb_host *host;
81
82 int phyid, isroot;
83 int selfid_size;
84 int phy_reg0;
85
86 spinlock_t phy_reg_lock;
87
88 pcl_t rcv_pcl_start, rcv_pcl;
89 void *rcv_page;
90 dma_addr_t rcv_page_dma;
91 int rcv_active;
92
93 struct lynx_send_data {
94 pcl_t pcl_start, pcl;
95 struct hpsb_packet *queue, *queue_last;
96 spinlock_t queue_lock;
97 dma_addr_t header_dma, data_dma;
98 int channel;
99 } async, iso_send;
100
101 struct {
102 pcl_t pcl[NUM_ISORCV_PCL];
103 u32 stat[NUM_ISORCV_PCL];
104 void *page[ISORCV_PAGES];
105 dma_addr_t page_dma[ISORCV_PAGES];
106 pcl_t pcl_start;
107 int chan_count;
108 int next, last, used, running;
109 struct tasklet_struct tq;
110 spinlock_t lock;
111 } iso_rcv;
112 };
113
114 /* the per-file data structure for mem space access */
115 struct memdata {
116 struct ti_lynx *lynx;
117 int cid;
118 atomic_t aux_intr_last_seen;
119 /* enum values are the same as LBUS_ADDR_SEL_* values below */
120 enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
121 };
122
123
124
125 /*
126 * Register read and write helper functions.
127 */
128 static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
129 {
130 writel(data, lynx->registers + offset);
131 }
132
133 static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
134 {
135 return readl(lynx->registers + offset);
136 }
137
138 static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
139 u32 mask)
140 {
141 reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
142 }
143
144 static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
145 u32 mask)
146 {
147 reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
148 }
149
150
151
152 /* chip register definitions follow */
153
154 #define PCI_LATENCY_CACHELINE 0x0c
155
156 #define MISC_CONTROL 0x40
157 #define MISC_CONTROL_SWRESET (1<<0)
158
159 #define PCI_INT_STATUS 0x48
160 #define PCI_INT_ENABLE 0x4c
161 /* status and enable have identical bit numbers */
162 #define PCI_INT_INT_PEND (1<<31)
163 #define PCI_INT_FORCED_INT (1<<30)
164 #define PCI_INT_SLV_ADR_PERR (1<<28)
165 #define PCI_INT_SLV_DAT_PERR (1<<27)
166 #define PCI_INT_MST_DAT_PERR (1<<26)
167 #define PCI_INT_MST_DEV_TIMEOUT (1<<25)
168 #define PCI_INT_INTERNAL_SLV_TIMEOUT (1<<23)
169 #define PCI_INT_AUX_TIMEOUT (1<<18)
170 #define PCI_INT_AUX_INT (1<<17)
171 #define PCI_INT_1394 (1<<16)
172 #define PCI_INT_DMA4_PCL (1<<9)
173 #define PCI_INT_DMA4_HLT (1<<8)
174 #define PCI_INT_DMA3_PCL (1<<7)
175 #define PCI_INT_DMA3_HLT (1<<6)
176 #define PCI_INT_DMA2_PCL (1<<5)
177 #define PCI_INT_DMA2_HLT (1<<4)
178 #define PCI_INT_DMA1_PCL (1<<3)
179 #define PCI_INT_DMA1_HLT (1<<2)
180 #define PCI_INT_DMA0_PCL (1<<1)
181 #define PCI_INT_DMA0_HLT (1<<0)
182 /* all DMA interrupts combined: */
183 #define PCI_INT_DMA_ALL 0x3ff
184
185 #define PCI_INT_DMA_HLT(chan) (1 << (chan * 2))
186 #define PCI_INT_DMA_PCL(chan) (1 << (chan * 2 + 1))
187
188 #define LBUS_ADDR 0xb4
189 #define LBUS_ADDR_SEL_RAM (0x0<<16)
190 #define LBUS_ADDR_SEL_ROM (0x1<<16)
191 #define LBUS_ADDR_SEL_AUX (0x2<<16)
192 #define LBUS_ADDR_SEL_ZV (0x3<<16)
193
194 #define GPIO_CTRL_A 0xb8
195 #define GPIO_CTRL_B 0xbc
196 #define GPIO_DATA_BASE 0xc0
197
198 #define DMA_BREG(base, chan) (base + chan * 0x20)
199 #define DMA_SREG(base, chan) (base + chan * 0x10)
200
201 #define DMA0_PREV_PCL 0x100
202 #define DMA1_PREV_PCL 0x120
203 #define DMA2_PREV_PCL 0x140
204 #define DMA3_PREV_PCL 0x160
205 #define DMA4_PREV_PCL 0x180
206 #define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan))
207
208 #define DMA0_CURRENT_PCL 0x104
209 #define DMA1_CURRENT_PCL 0x124
210 #define DMA2_CURRENT_PCL 0x144
211 #define DMA3_CURRENT_PCL 0x164
212 #define DMA4_CURRENT_PCL 0x184
213 #define DMA_CURRENT_PCL(chan) (DMA_BREG(DMA0_CURRENT_PCL, chan))
214
215 #define DMA0_CHAN_STAT 0x10c
216 #define DMA1_CHAN_STAT 0x12c
217 #define DMA2_CHAN_STAT 0x14c
218 #define DMA3_CHAN_STAT 0x16c
219 #define DMA4_CHAN_STAT 0x18c
220 #define DMA_CHAN_STAT(chan) (DMA_BREG(DMA0_CHAN_STAT, chan))
221 /* CHAN_STATUS registers share bits */
222 #define DMA_CHAN_STAT_SELFID (1<<31)
223 #define DMA_CHAN_STAT_ISOPKT (1<<30)
224 #define DMA_CHAN_STAT_PCIERR (1<<29)
225 #define DMA_CHAN_STAT_PKTERR (1<<28)
226 #define DMA_CHAN_STAT_PKTCMPL (1<<27)
227 #define DMA_CHAN_STAT_SPECIALACK (1<<14)
228
229
230 #define DMA0_CHAN_CTRL 0x110
231 #define DMA1_CHAN_CTRL 0x130
232 #define DMA2_CHAN_CTRL 0x150
233 #define DMA3_CHAN_CTRL 0x170
234 #define DMA4_CHAN_CTRL 0x190
235 #define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan))
236 /* CHAN_CTRL registers share bits */
237 #define DMA_CHAN_CTRL_ENABLE (1<<31)
238 #define DMA_CHAN_CTRL_BUSY (1<<30)
239 #define DMA_CHAN_CTRL_LINK (1<<29)
240
241 #define DMA0_READY 0x114
242 #define DMA1_READY 0x134
243 #define DMA2_READY 0x154
244 #define DMA3_READY 0x174
245 #define DMA4_READY 0x194
246 #define DMA_READY(chan) (DMA_BREG(DMA0_READY, chan))
247
248 #define DMA_GLOBAL_REGISTER 0x908
249
250 #define FIFO_SIZES 0xa00
251
252 #define FIFO_CONTROL 0xa10
253 #define FIFO_CONTROL_GRF_FLUSH (1<<4)
254 #define FIFO_CONTROL_ITF_FLUSH (1<<3)
255 #define FIFO_CONTROL_ATF_FLUSH (1<<2)
256
257 #define FIFO_XMIT_THRESHOLD 0xa14
258
259 #define DMA0_WORD0_CMP_VALUE 0xb00
260 #define DMA1_WORD0_CMP_VALUE 0xb10
261 #define DMA2_WORD0_CMP_VALUE 0xb20
262 #define DMA3_WORD0_CMP_VALUE 0xb30
263 #define DMA4_WORD0_CMP_VALUE 0xb40
264 #define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
265
266 #define DMA0_WORD0_CMP_ENABLE 0xb04
267 #define DMA1_WORD0_CMP_ENABLE 0xb14
268 #define DMA2_WORD0_CMP_ENABLE 0xb24
269 #define DMA3_WORD0_CMP_ENABLE 0xb34
270 #define DMA4_WORD0_CMP_ENABLE 0xb44
271 #define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
272
273 #define DMA0_WORD1_CMP_VALUE 0xb08
274 #define DMA1_WORD1_CMP_VALUE 0xb18
275 #define DMA2_WORD1_CMP_VALUE 0xb28
276 #define DMA3_WORD1_CMP_VALUE 0xb38
277 #define DMA4_WORD1_CMP_VALUE 0xb48
278 #define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
279
280 #define DMA0_WORD1_CMP_ENABLE 0xb0c
281 #define DMA1_WORD1_CMP_ENABLE 0xb1c
282 #define DMA2_WORD1_CMP_ENABLE 0xb2c
283 #define DMA3_WORD1_CMP_ENABLE 0xb3c
284 #define DMA4_WORD1_CMP_ENABLE 0xb4c
285 #define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
286 /* word 1 compare enable flags */
287 #define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15)
288 #define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14)
289 #define DMA_WORD1_CMP_MATCH_BUS_BCAST (1<<13)
290 #define DMA_WORD1_CMP_MATCH_LOCAL_NODE (1<<12)
291 #define DMA_WORD1_CMP_MATCH_EXACT (1<<11)
292 #define DMA_WORD1_CMP_ENABLE_SELF_ID (1<<10)
293 #define DMA_WORD1_CMP_ENABLE_MASTER (1<<8)
294
295 #define LINK_ID 0xf00
296 #define LINK_ID_BUS(id) (id<<22)
297 #define LINK_ID_NODE(id) (id<<16)
298
299 #define LINK_CONTROL 0xf04
300 #define LINK_CONTROL_BUSY (1<<29)
301 #define LINK_CONTROL_TX_ISO_EN (1<<26)
302 #define LINK_CONTROL_RX_ISO_EN (1<<25)
303 #define LINK_CONTROL_TX_ASYNC_EN (1<<24)
304 #define LINK_CONTROL_RX_ASYNC_EN (1<<23)
305 #define LINK_CONTROL_RESET_TX (1<<21)
306 #define LINK_CONTROL_RESET_RX (1<<20)
307 #define LINK_CONTROL_CYCMASTER (1<<11)
308 #define LINK_CONTROL_CYCSOURCE (1<<10)
309 #define LINK_CONTROL_CYCTIMEREN (1<<9)
310 #define LINK_CONTROL_RCV_CMP_VALID (1<<7)
311 #define LINK_CONTROL_SNOOP_ENABLE (1<<6)
312
313 #define CYCLE_TIMER 0xf08
314
315 #define LINK_PHY 0xf0c
316 #define LINK_PHY_READ (1<<31)
317 #define LINK_PHY_WRITE (1<<30)
318 #define LINK_PHY_ADDR(addr) (addr<<24)
319 #define LINK_PHY_WDATA(data) (data<<16)
320 #define LINK_PHY_RADDR(addr) (addr<<8)
321
322
323 #define LINK_INT_STATUS 0xf14
324 #define LINK_INT_ENABLE 0xf18
325 /* status and enable have identical bit numbers */
326 #define LINK_INT_LINK_INT (1<<31)
327 #define LINK_INT_PHY_TIMEOUT (1<<30)
328 #define LINK_INT_PHY_REG_RCVD (1<<29)
329 #define LINK_INT_PHY_BUSRESET (1<<28)
330 #define LINK_INT_TX_RDY (1<<26)
331 #define LINK_INT_RX_DATA_RDY (1<<25)
332 #define LINK_INT_ISO_STUCK (1<<20)
333 #define LINK_INT_ASYNC_STUCK (1<<19)
334 #define LINK_INT_SENT_REJECT (1<<17)
335 #define LINK_INT_HDR_ERR (1<<16)
336 #define LINK_INT_TX_INVALID_TC (1<<15)
337 #define LINK_INT_CYC_SECOND (1<<11)
338 #define LINK_INT_CYC_START (1<<10)
339 #define LINK_INT_CYC_DONE (1<<9)
340 #define LINK_INT_CYC_PENDING (1<<8)
341 #define LINK_INT_CYC_LOST (1<<7)
342 #define LINK_INT_CYC_ARB_FAILED (1<<6)
343 #define LINK_INT_GRF_OVERFLOW (1<<5)
344 #define LINK_INT_ITF_UNDERFLOW (1<<4)
345 #define LINK_INT_ATF_UNDERFLOW (1<<3)
346 #define LINK_INT_ISOARB_FAILED (1<<0)
347
348 /* PHY specifics */
349 #define PHY_VENDORID_TI 0x800028
350 #define PHY_PRODUCTID_TSB41LV03 0x000000
351
352
353 /* this is the physical layout of a PCL, its size is 128 bytes */
354 struct ti_pcl {
355 u32 next;
356 u32 async_error_next;
357 u32 user_data;
358 u32 pcl_status;
359 u32 remaining_transfer_count;
360 u32 next_data_buffer;
361 struct {
362 u32 control;
363 u32 pointer;
364 } buffer[13] __attribute__ ((packed));
365 } __attribute__ ((packed));
366
367 #include <linux/stddef.h>
368 #define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
369
370
371 #ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
372
373 static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
374 const struct ti_pcl *pcl)
375 {
376 int i;
377 u32 *in = (u32 *)pcl;
378 u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
379
380 for (i = 0; i < 32; i++, out++, in++) {
381 writel(*in, out);
382 }
383 }
384
385 static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
386 struct ti_pcl *pcl)
387 {
388 int i;
389 u32 *out = (u32 *)pcl;
390 u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
391
392 for (i = 0; i < 32; i++, out++, in++) {
393 *out = readl(in);
394 }
395 }
396
397 static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
398 {
399 return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
400 }
401
402 #else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
403
404 static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
405 const struct ti_pcl *pcl)
406 {
407 memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
408 (u32 *)pcl, sizeof(struct ti_pcl));
409 }
410
411 static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
412 struct ti_pcl *pcl)
413 {
414 memcpy_le32((u32 *)pcl,
415 (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
416 sizeof(struct ti_pcl));
417 }
418
419 static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
420 {
421 return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
422 }
423
424 #endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
425
426
427 #if defined (CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined (__BIG_ENDIAN)
428 typedef struct ti_pcl pcltmp_t;
429
430 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
431 pcltmp_t *tmp)
432 {
433 get_pcl(lynx, pclid, tmp);
434 return tmp;
435 }
436
437 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
438 pcltmp_t *tmp)
439 {
440 put_pcl(lynx, pclid, tmp);
441 }
442
443 #else
444 typedef int pcltmp_t; /* just a dummy */
445
446 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
447 pcltmp_t *tmp)
448 {
449 return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
450 }
451
452 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
453 pcltmp_t *tmp)
454 {
455 }
456 #endif
457
458
459 static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
460 int dmachan)
461 {
462 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
463 pcl_bus(lynx, pclid) + idx * 4);
464 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
465 DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
466 }
467
468 static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
469 {
470 run_sub_pcl(lynx, pclid, 0, dmachan);
471 }
472
473 #define PCL_NEXT_INVALID (1<<0)
474
475 /* transfer commands */
476 #define PCL_CMD_RCV (0x1<<24)
477 #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
478 #define PCL_CMD_XMT (0x2<<24)
479 #define PCL_CMD_UNFXMT (0xc<<24)
480 #define PCL_CMD_PCI_TO_LBUS (0x8<<24)
481 #define PCL_CMD_LBUS_TO_PCI (0x9<<24)
482
483 /* aux commands */
484 #define PCL_CMD_NOP (0x0<<24)
485 #define PCL_CMD_LOAD (0x3<<24)
486 #define PCL_CMD_STOREQ (0x4<<24)
487 #define PCL_CMD_STORED (0xb<<24)
488 #define PCL_CMD_STORE0 (0x5<<24)
489 #define PCL_CMD_STORE1 (0x6<<24)
490 #define PCL_CMD_COMPARE (0xe<<24)
491 #define PCL_CMD_SWAP_COMPARE (0xf<<24)
492 #define PCL_CMD_ADD (0xd<<24)
493 #define PCL_CMD_BRANCH (0x7<<24)
494
495 /* BRANCH condition codes */
496 #define PCL_COND_DMARDY_SET (0x1<<20)
497 #define PCL_COND_DMARDY_CLEAR (0x2<<20)
498
499 #define PCL_GEN_INTR (1<<19)
500 #define PCL_LAST_BUFF (1<<18)
501 #define PCL_LAST_CMD (PCL_LAST_BUFF)
502 #define PCL_WAITSTAT (1<<17)
503 #define PCL_BIGENDIAN (1<<16)
504 #define PCL_ISOMODE (1<<12)
505
506
507 #define _(x) (__constant_cpu_to_be32(x))
508
509 static quadlet_t lynx_csr_rom[] = {
510 /* bus info block offset (hex) */
511 _(0x04040000), /* info/CRC length, CRC 400 */
512 _(0x31333934), /* 1394 magic number 404 */
513 _(0xf064a000), /* misc. settings 408 */
514 _(0x08002850), /* vendor ID, chip ID high 40c */
515 _(0x0000ffff), /* chip ID low 410 */
516 /* root directory */
517 _(0x00090000), /* directory length, CRC 414 */
518 _(0x03080028), /* vendor ID (Texas Instr.) 418 */
519 _(0x81000008), /* offset to textual ID 41c */
520 _(0x0c000200), /* node capabilities 420 */
521 _(0x8d00000e), /* offset to unique ID 424 */
522 _(0xc7000010), /* offset to module independent info 428 */
523 _(0x04000000), /* module hardware version 42c */
524 _(0x81000014), /* offset to textual ID 430 */
525 _(0x09000000), /* node hardware version 434 */
526 _(0x81000018), /* offset to textual ID 438 */
527 /* module vendor ID textual */
528 _(0x00070000), /* CRC length, CRC 43c */
529 _(0x00000000), /* 440 */
530 _(0x00000000), /* 444 */
531 _(0x54455841), /* "Texas Instruments" 448 */
532 _(0x5320494e), /* 44c */
533 _(0x53545255), /* 450 */
534 _(0x4d454e54), /* 454 */
535 _(0x53000000), /* 458 */
536 /* node unique ID leaf */
537 _(0x00020000), /* CRC length, CRC 45c */
538 _(0x08002850), /* vendor ID, chip ID high 460 */
539 _(0x0000ffff), /* chip ID low 464 */
540 /* module dependent info */
541 _(0x00050000), /* CRC length, CRC 468 */
542 _(0x81000012), /* offset to module textual ID 46c */
543 _(0x81000017), /* textual descriptor 470 */
544 _(0x39010000), /* SRAM size 474 */
545 _(0x3a010000), /* AUXRAM size 478 */
546 _(0x3b000000), /* AUX device 47c */
547 /* module textual ID */
548 _(0x00050000), /* CRC length, CRC 480 */
549 _(0x00000000), /* 484 */
550 _(0x00000000), /* 488 */
551 _(0x54534231), /* "TSB12LV21" 48c */
552 _(0x324c5632), /* 490 */
553 _(0x31000000), /* 494 */
554 /* part number */
555 _(0x00060000), /* CRC length, CRC 498 */
556 _(0x00000000), /* 49c */
557 _(0x00000000), /* 4a0 */
558 _(0x39383036), /* "9806000-0001" 4a4 */
559 _(0x3030302d), /* 4a8 */
560 _(0x30303031), /* 4ac */
561 _(0x20000001), /* 4b0 */
562 /* module hardware version textual */
563 _(0x00050000), /* CRC length, CRC 4b4 */
564 _(0x00000000), /* 4b8 */
565 _(0x00000000), /* 4bc */
566 _(0x5453424b), /* "TSBKPCITST" 4c0 */
567 _(0x50434954), /* 4c4 */
568 _(0x53540000), /* 4c8 */
569 /* node hardware version textual */
570 _(0x00050000), /* CRC length, CRC 4d0 */
571 _(0x00000000), /* 4d4 */
572 _(0x00000000), /* 4d8 */
573 _(0x54534232), /* "TSB21LV03" 4dc */
574 _(0x314c5630), /* 4e0 */
575 _(0x33000000) /* 4e4 */
576 };
577
578 #undef _
579