File: /usr/src/linux/drivers/isdn/avmb1/avmcard.h
1 /*
2 * $Id: avmcard.h,v 1.8.6.3 2001/05/17 21:15:33 kai Exp $
3 *
4 * Copyright 1999 by Carsten Paeth (calle@calle.in-berlin.de)
5 *
6 */
7
8 #ifndef _AVMCARD_H_
9 #define _AVMCARD_H_
10
11 #define AVMB1_PORTLEN 0x1f
12 #define AVM_MAXVERSION 8
13 #define AVM_NCCI_PER_CHANNEL 4
14
15 /*
16 * Versions
17 */
18
19 #define VER_DRIVER 0
20 #define VER_CARDTYPE 1
21 #define VER_HWID 2
22 #define VER_SERIAL 3
23 #define VER_OPTION 4
24 #define VER_PROTO 5
25 #define VER_PROFILE 6
26 #define VER_CAPI 7
27
28 enum avmcardtype {
29 avm_b1isa,
30 avm_b1pci,
31 avm_b1pcmcia,
32 avm_m1,
33 avm_m2,
34 avm_t1isa,
35 avm_t1pci,
36 avm_c4,
37 avm_c2
38 };
39
40 typedef struct avmcard_dmainfo {
41 __u32 recvlen;
42 __u8 recvbuf[128+2048];
43 struct sk_buff_head send_queue;
44 __u8 sendbuf[128+2048];
45 } avmcard_dmainfo;
46
47
48 typedef struct avmcard {
49 char name[32];
50 unsigned int port;
51 unsigned irq;
52 unsigned long membase;
53 enum avmcardtype cardtype;
54 unsigned char revision;
55 unsigned char class;
56 int cardnr; /* for t1isa */
57
58 char msgbuf[128]; /* capimsg msg part */
59 char databuf[2048]; /* capimsg data part */
60
61 int interrupt;
62
63 void *mbase;
64 volatile __u32 csr;
65 avmcard_dmainfo *dma;
66
67 struct avmctrl_info {
68 char cardname[32];
69
70 int versionlen;
71 char versionbuf[1024];
72 char *version[AVM_MAXVERSION];
73
74 char infobuf[128]; /* for function procinfo */
75
76 struct avmcard *card;
77 struct capi_ctr *capi_ctrl;
78
79 } *ctrlinfo;
80
81 int nlogcontr;
82 } avmcard;
83
84 typedef struct avmctrl_info avmctrl_info;
85
86 extern int b1_irq_table[16];
87
88 /*
89 * LLI Messages to the ISDN-ControllerISDN Controller
90 */
91
92 #define SEND_POLL 0x72 /*
93 * after load <- RECEIVE_POLL
94 */
95 #define SEND_INIT 0x11 /*
96 * first message <- RECEIVE_INIT
97 * int32 NumApplications int32
98 * NumNCCIs int32 BoardNumber
99 */
100 #define SEND_REGISTER 0x12 /*
101 * register an application int32
102 * ApplIDId int32 NumMessages
103 * int32 NumB3Connections int32
104 * NumB3Blocks int32 B3Size
105 *
106 * AnzB3Connection != 0 &&
107 * AnzB3Blocks >= 1 && B3Size >= 1
108 */
109 #define SEND_RELEASE 0x14 /*
110 * deregister an application int32
111 * ApplID
112 */
113 #define SEND_MESSAGE 0x15 /*
114 * send capi-message int32 length
115 * capi-data ...
116 */
117 #define SEND_DATA_B3_REQ 0x13 /*
118 * send capi-data-message int32
119 * MsgLength capi-data ... int32
120 * B3Length data ....
121 */
122
123 #define SEND_CONFIG 0x21 /*
124 */
125
126 #define SEND_POLLACK 0x73 /* T1 Watchdog */
127
128 /*
129 * LLI Messages from the ISDN-ControllerISDN Controller
130 */
131
132 #define RECEIVE_POLL 0x32 /*
133 * <- after SEND_POLL
134 */
135 #define RECEIVE_INIT 0x27 /*
136 * <- after SEND_INIT int32 length
137 * byte total length b1struct board
138 * driver revision b1struct card
139 * type b1struct reserved b1struct
140 * serial number b1struct driver
141 * capability b1struct d-channel
142 * protocol b1struct CAPI-2.0
143 * profile b1struct capi version
144 */
145 #define RECEIVE_MESSAGE 0x21 /*
146 * <- after SEND_MESSAGE int32
147 * AppllID int32 Length capi-data
148 * ....
149 */
150 #define RECEIVE_DATA_B3_IND 0x22 /*
151 * received data int32 AppllID
152 * int32 Length capi-data ...
153 * int32 B3Length data ...
154 */
155 #define RECEIVE_START 0x23 /*
156 * Handshake
157 */
158 #define RECEIVE_STOP 0x24 /*
159 * Handshake
160 */
161 #define RECEIVE_NEW_NCCI 0x25 /*
162 * int32 AppllID int32 NCCI int32
163 * WindowSize
164 */
165 #define RECEIVE_FREE_NCCI 0x26 /*
166 * int32 AppllID int32 NCCI
167 */
168 #define RECEIVE_RELEASE 0x26 /*
169 * int32 AppllID int32 0xffffffff
170 */
171 #define RECEIVE_TASK_READY 0x31 /*
172 * int32 tasknr
173 * int32 Length Taskname ...
174 */
175 #define RECEIVE_DEBUGMSG 0x71 /*
176 * int32 Length message
177 *
178 */
179 #define RECEIVE_POLLDWORD 0x75 /* t1pci in dword mode */
180
181 #define WRITE_REGISTER 0x00
182 #define READ_REGISTER 0x01
183
184 /*
185 * port offsets
186 */
187
188 #define B1_READ 0x00
189 #define B1_WRITE 0x01
190 #define B1_INSTAT 0x02
191 #define B1_OUTSTAT 0x03
192 #define B1_ANALYSE 0x04
193 #define B1_REVISION 0x05
194 #define B1_RESET 0x10
195
196
197 #define B1_STAT0(cardtype) ((cardtype) == avm_m1 ? 0x81200000l : 0x80A00000l)
198 #define B1_STAT1(cardtype) (0x80E00000l)
199
200 /* ---------------------------------------------------------------- */
201
202 static inline unsigned char b1outp(unsigned int base,
203 unsigned short offset,
204 unsigned char value)
205 {
206 outb(value, base + offset);
207 return inb(base + B1_ANALYSE);
208 }
209
210
211 static inline int b1_rx_full(unsigned int base)
212 {
213 return inb(base + B1_INSTAT) & 0x1;
214 }
215
216 static inline unsigned char b1_get_byte(unsigned int base)
217 {
218 unsigned long stop = jiffies + 1 * HZ; /* maximum wait time 1 sec */
219 while (!b1_rx_full(base) && time_before(jiffies, stop));
220 if (b1_rx_full(base))
221 return inb(base + B1_READ);
222 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base);
223 return 0;
224 }
225
226 static inline unsigned int b1_get_word(unsigned int base)
227 {
228 unsigned int val = 0;
229 val |= b1_get_byte(base);
230 val |= (b1_get_byte(base) << 8);
231 val |= (b1_get_byte(base) << 16);
232 val |= (b1_get_byte(base) << 24);
233 return val;
234 }
235
236 static inline int b1_tx_empty(unsigned int base)
237 {
238 return inb(base + B1_OUTSTAT) & 0x1;
239 }
240
241 static inline void b1_put_byte(unsigned int base, unsigned char val)
242 {
243 while (!b1_tx_empty(base));
244 b1outp(base, B1_WRITE, val);
245 }
246
247 static inline int b1_save_put_byte(unsigned int base, unsigned char val)
248 {
249 unsigned long stop = jiffies + 2 * HZ;
250 while (!b1_tx_empty(base) && time_before(jiffies,stop));
251 if (!b1_tx_empty(base)) return -1;
252 b1outp(base, B1_WRITE, val);
253 return 0;
254 }
255
256 static inline void b1_put_word(unsigned int base, unsigned int val)
257 {
258 b1_put_byte(base, val & 0xff);
259 b1_put_byte(base, (val >> 8) & 0xff);
260 b1_put_byte(base, (val >> 16) & 0xff);
261 b1_put_byte(base, (val >> 24) & 0xff);
262 }
263
264 static inline unsigned int b1_get_slice(unsigned int base,
265 unsigned char *dp)
266 {
267 unsigned int len, i;
268
269 len = i = b1_get_word(base);
270 while (i-- > 0) *dp++ = b1_get_byte(base);
271 return len;
272 }
273
274 static inline void b1_put_slice(unsigned int base,
275 unsigned char *dp, unsigned int len)
276 {
277 unsigned i = len;
278 b1_put_word(base, i);
279 while (i-- > 0)
280 b1_put_byte(base, *dp++);
281 }
282
283 static void b1_wr_reg(unsigned int base,
284 unsigned int reg,
285 unsigned int value)
286 {
287 b1_put_byte(base, WRITE_REGISTER);
288 b1_put_word(base, reg);
289 b1_put_word(base, value);
290 }
291
292 static inline unsigned int b1_rd_reg(unsigned int base,
293 unsigned int reg)
294 {
295 b1_put_byte(base, READ_REGISTER);
296 b1_put_word(base, reg);
297 return b1_get_word(base);
298
299 }
300
301 static inline void b1_reset(unsigned int base)
302 {
303 b1outp(base, B1_RESET, 0);
304 mdelay(55 * 2); /* 2 TIC's */
305
306 b1outp(base, B1_RESET, 1);
307 mdelay(55 * 2); /* 2 TIC's */
308
309 b1outp(base, B1_RESET, 0);
310 mdelay(55 * 2); /* 2 TIC's */
311 }
312
313 static inline unsigned char b1_disable_irq(unsigned int base)
314 {
315 return b1outp(base, B1_INSTAT, 0x00);
316 }
317
318 /* ---------------------------------------------------------------- */
319
320 static inline void b1_set_test_bit(unsigned int base,
321 enum avmcardtype cardtype,
322 int onoff)
323 {
324 b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20);
325 }
326
327 static inline int b1_get_test_bit(unsigned int base,
328 enum avmcardtype cardtype)
329 {
330 return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0;
331 }
332
333 /* ---------------------------------------------------------------- */
334
335 #define T1_FASTLINK 0x00
336 #define T1_SLOWLINK 0x08
337
338 #define T1_READ B1_READ
339 #define T1_WRITE B1_WRITE
340 #define T1_INSTAT B1_INSTAT
341 #define T1_OUTSTAT B1_OUTSTAT
342 #define T1_IRQENABLE 0x05
343 #define T1_FIFOSTAT 0x06
344 #define T1_RESETLINK 0x10
345 #define T1_ANALYSE 0x11
346 #define T1_IRQMASTER 0x12
347 #define T1_IDENT 0x17
348 #define T1_RESETBOARD 0x1f
349
350 #define T1F_IREADY 0x01
351 #define T1F_IHALF 0x02
352 #define T1F_IFULL 0x04
353 #define T1F_IEMPTY 0x08
354 #define T1F_IFLAGS 0xF0
355
356 #define T1F_OREADY 0x10
357 #define T1F_OHALF 0x20
358 #define T1F_OEMPTY 0x40
359 #define T1F_OFULL 0x80
360 #define T1F_OFLAGS 0xF0
361
362 /* there are HEMA cards with 1k and 4k FIFO out */
363 #define FIFO_OUTBSIZE 256
364 #define FIFO_INPBSIZE 512
365
366 #define HEMA_VERSION_ID 0
367 #define HEMA_PAL_ID 0
368
369 static inline void t1outp(unsigned int base,
370 unsigned short offset,
371 unsigned char value)
372 {
373 outb(value, base + offset);
374 }
375
376 static inline unsigned char t1inp(unsigned int base,
377 unsigned short offset)
378 {
379 return inb(base + offset);
380 }
381
382 static inline int t1_isfastlink(unsigned int base)
383 {
384 return (inb(base + T1_IDENT) & ~0x82) == 1;
385 }
386
387 static inline unsigned char t1_fifostatus(unsigned int base)
388 {
389 return inb(base + T1_FIFOSTAT);
390 }
391
392 static inline unsigned int t1_get_slice(unsigned int base,
393 unsigned char *dp)
394 {
395 unsigned int len, i;
396 #ifdef FASTLINK_DEBUG
397 unsigned wcnt = 0, bcnt = 0;
398 #endif
399
400 len = i = b1_get_word(base);
401 if (t1_isfastlink(base)) {
402 int status;
403 while (i > 0) {
404 status = t1_fifostatus(base) & (T1F_IREADY|T1F_IHALF);
405 if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
406
407 switch (status) {
408 case T1F_IREADY|T1F_IHALF|T1F_IFULL:
409 insb(base+B1_READ, dp, FIFO_INPBSIZE);
410 dp += FIFO_INPBSIZE;
411 i -= FIFO_INPBSIZE;
412 #ifdef FASTLINK_DEBUG
413 wcnt += FIFO_INPBSIZE;
414 #endif
415 break;
416 case T1F_IREADY|T1F_IHALF:
417 insb(base+B1_READ,dp, i);
418 #ifdef FASTLINK_DEBUG
419 wcnt += i;
420 #endif
421 dp += i;
422 i = 0;
423 if (i == 0)
424 break;
425 /* fall through */
426 default:
427 *dp++ = b1_get_byte(base);
428 i--;
429 #ifdef FASTLINK_DEBUG
430 bcnt++;
431 #endif
432 break;
433 }
434 }
435 #ifdef FASTLINK_DEBUG
436 if (wcnt)
437 printk(KERN_DEBUG "b1lli(0x%x): get_slice l=%d w=%d b=%d\n",
438 base, len, wcnt, bcnt);
439 #endif
440 } else {
441 while (i-- > 0)
442 *dp++ = b1_get_byte(base);
443 }
444 return len;
445 }
446
447 static inline void t1_put_slice(unsigned int base,
448 unsigned char *dp, unsigned int len)
449 {
450 unsigned i = len;
451 b1_put_word(base, i);
452 if (t1_isfastlink(base)) {
453 int status;
454 while (i > 0) {
455 status = t1_fifostatus(base) & (T1F_OREADY|T1F_OHALF);
456 if (i >= FIFO_OUTBSIZE) status |= T1F_OEMPTY;
457 switch (status) {
458 case T1F_OREADY|T1F_OHALF|T1F_OEMPTY:
459 outsb(base+B1_WRITE, dp, FIFO_OUTBSIZE);
460 dp += FIFO_OUTBSIZE;
461 i -= FIFO_OUTBSIZE;
462 break;
463 case T1F_OREADY|T1F_OHALF:
464 outsb(base+B1_WRITE, dp, i);
465 dp += i;
466 i = 0;
467 break;
468 default:
469 b1_put_byte(base, *dp++);
470 i--;
471 break;
472 }
473 }
474 } else {
475 while (i-- > 0)
476 b1_put_byte(base, *dp++);
477 }
478 }
479
480 static inline void t1_disable_irq(unsigned int base)
481 {
482 t1outp(base, T1_IRQMASTER, 0x00);
483 }
484
485 static inline void t1_reset(unsigned int base)
486 {
487 /* reset T1 Controller */
488 b1_reset(base);
489 /* disable irq on HEMA */
490 t1outp(base, B1_INSTAT, 0x00);
491 t1outp(base, B1_OUTSTAT, 0x00);
492 t1outp(base, T1_IRQMASTER, 0x00);
493 /* reset HEMA board configuration */
494 t1outp(base, T1_RESETBOARD, 0xf);
495 }
496
497 static inline void b1_setinterrupt(unsigned int base, unsigned irq,
498 enum avmcardtype cardtype)
499 {
500 switch (cardtype) {
501 case avm_t1isa:
502 t1outp(base, B1_INSTAT, 0x00);
503 t1outp(base, B1_INSTAT, 0x02);
504 t1outp(base, T1_IRQMASTER, 0x08);
505 break;
506 case avm_b1isa:
507 b1outp(base, B1_INSTAT, 0x00);
508 b1outp(base, B1_RESET, b1_irq_table[irq]);
509 b1outp(base, B1_INSTAT, 0x02);
510 break;
511 default:
512 case avm_m1:
513 case avm_m2:
514 case avm_b1pci:
515 b1outp(base, B1_INSTAT, 0x00);
516 b1outp(base, B1_RESET, 0xf0);
517 b1outp(base, B1_INSTAT, 0x02);
518 break;
519 case avm_c4:
520 case avm_t1pci:
521 b1outp(base, B1_RESET, 0xf0);
522 break;
523 }
524 }
525
526 /* b1.c */
527 int b1_detect(unsigned int base, enum avmcardtype cardtype);
528 void b1_getrevision(avmcard *card);
529 int b1_load_t4file(avmcard *card, capiloaddatapart * t4file);
530 int b1_load_config(avmcard *card, capiloaddatapart * config);
531 int b1_loaded(avmcard *card);
532
533 int b1_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
534 void b1_reset_ctr(struct capi_ctr *ctrl);
535 void b1_register_appl(struct capi_ctr *ctrl, __u16 appl,
536 capi_register_params *rp);
537 void b1_release_appl(struct capi_ctr *ctrl, __u16 appl);
538 void b1_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
539 void b1_parse_version(avmctrl_info *card);
540 void b1_handle_interrupt(avmcard * card);
541
542 int b1ctl_read_proc(char *page, char **start, off_t off,
543 int count, int *eof, struct capi_ctr *ctrl);
544
545 /* b1dma.c */
546 int b1pciv4_detect(avmcard *card);
547 int t1pci_detect(avmcard *card);
548 void b1dma_reset(avmcard *card);
549 void b1dma_interrupt(int interrupt, void *devptr, struct pt_regs *regs);
550
551 int b1dma_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
552 void b1dma_reset_ctr(struct capi_ctr *ctrl);
553 void b1dma_remove_ctr(struct capi_ctr *ctrl);
554 void b1dma_register_appl(struct capi_ctr *ctrl,
555 __u16 appl,
556 capi_register_params *rp);
557 void b1dma_release_appl(struct capi_ctr *ctrl, __u16 appl);
558 void b1dma_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
559 int b1dmactl_read_proc(char *page, char **start, off_t off,
560 int count, int *eof, struct capi_ctr *ctrl);
561
562 #endif /* _AVMCARD_H_ */
563