File: /usr/src/linux/drivers/isdn/hisax/amd7930.c
1 /* $Id: amd7930.c,v 1.5.6.3 2001/06/11 22:08:37 kai Exp $
2 *
3 * HiSax ISDN driver - chip specific routines for AMD 7930
4 *
5 * Author Brent Baccala (baccala@FreeSoft.org)
6 *
7 * - Existing ISDN HiSax driver provides all the smarts
8 * - it compiles, runs, talks to an isolated phone switch, connects
9 * to a Cisco, pings go through
10 * - AMD 7930 support only (no DBRI yet)
11 * - no US NI-1 support (may not work on US phone system - untested)
12 * - periodic packet loss, apparently due to lost interrupts
13 * - ISDN sometimes freezes, requiring reboot before it will work again
14 *
15 * The code is unreliable enough to be consider alpha
16 *
17 * This file is (c) under GNU General Public License
18 *
19 * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
20 * SparcStation 1+. The chip provides microphone and speaker interfaces
21 * which provide mono-channel audio at 8K samples per second via either
22 * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an
23 * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
24 * which performs basic D channel LAPD processing and provides raw
25 * B channel data. The digital audio channel, the two ISDN B channels,
26 * and two 64 Kbps channels to the microprocessor are all interconnected
27 * via a multiplexer.
28 *
29 * This driver interfaces to the Linux HiSax ISDN driver, which performs
30 * all high-level Q.921 and Q.931 ISDN functions. The file is not
31 * itself a hardware driver; rather it uses functions exported by
32 * the AMD7930 driver in the sparcaudio subsystem (drivers/sbus/audio),
33 * allowing the chip to be simultaneously used for both audio and ISDN data.
34 * The hardware driver does _no_ buffering, but provides several callbacks
35 * which are called during interrupt service and should therefore run quickly.
36 *
37 * D channel transmission is performed by passing the hardware driver the
38 * address and size of an skb's data area, then waiting for a callback
39 * to signal successful transmission of the packet. A task is then
40 * queued to notify the HiSax driver that another packet may be transmitted.
41 *
42 * D channel reception is quite simple, mainly because of:
43 * 1) the slow speed of the D channel - 16 kbps, and
44 * 2) the presence of an 8- or 32-byte (depending on chip version) FIFO
45 * to buffer the D channel data on the chip
46 * Worst case scenario of back-to-back packets with the 8 byte buffer
47 * at 16 kbps yields an service time of 4 ms - long enough to preclude
48 * the need for fancy buffering. We queue a background task that copies
49 * data out of the receive buffer into an skb, and the hardware driver
50 * simply does nothing until we're done with the receive buffer and
51 * reset it for a new packet.
52 *
53 * B channel processing is more complex, because of:
54 * 1) the faster speed - 64 kbps,
55 * 2) the lack of any on-chip buffering (it interrupts for every byte), and
56 * 3) the lack of any chip support for HDLC encapsulation
57 *
58 * The HiSax driver can put each B channel into one of three modes -
59 * L1_MODE_NULL (channel disabled), L1_MODE_TRANS (transparent data relay),
60 * and L1_MODE_HDLC (HDLC encapsulation by low-level driver).
61 * L1_MODE_HDLC is the most common, used for almost all "pure" digital
62 * data sessions. L1_MODE_TRANS is used for ISDN audio.
63 *
64 * HDLC B channel transmission is performed via a large buffer into
65 * which the skb is copied while performing HDLC bit-stuffing. A CRC
66 * is computed and attached to the end of the buffer, which is then
67 * passed to the low-level routines for raw transmission. Once
68 * transmission is complete, the hardware driver is set to enter HDLC
69 * idle by successive transmission of mark (all 1) bytes, waiting for
70 * the ISDN driver to prepare another packet for transmission and
71 * deliver it.
72 *
73 * HDLC B channel reception is performed via an X-byte ring buffer
74 * divided into N sections of X/N bytes each. Defaults: X=256 bytes, N=4.
75 * As the hardware driver notifies us that each section is full, we
76 * hand it the next section and schedule a background task to peruse
77 * the received section, bit-by-bit, with an HDLC decoder. As
78 * packets are detected, they are copied into a large buffer while
79 * decoding HDLC bit-stuffing. The ending CRC is verified, and if
80 * it is correct, we alloc a new skb of the correct length (which we
81 * now know), copy the packet into it, and hand it to the upper layers.
82 * Optimization: for large packets, we hand the buffer (which also
83 * happens to be an skb) directly to the upper layer after an skb_trim,
84 * and alloc a new large buffer for future packets, thus avoiding a copy.
85 * Then we return to HDLC processing; state is saved between calls.
86 *
87 */
88
89 #define __NO_VERSION__
90 #include "hisax.h"
91 #include "../../sbus/audio/amd7930.h"
92 #include "isac.h"
93 #include "isdnl1.h"
94 #include "rawhdlc.h"
95 #include <linux/interrupt.h>
96
97 static const char *amd7930_revision = "$Revision: 1.5.6.3 $";
98
99 #define RCV_BUFSIZE 1024 /* Size of raw receive buffer in bytes */
100 #define RCV_BUFBLKS 4 /* Number of blocks to divide buffer into
101 * (must divide RCV_BUFSIZE) */
102
103 static void Bchan_fill_fifo(struct BCState *, struct sk_buff *);
104
105 static void
106 Bchan_xmt_bh(struct BCState *bcs)
107 {
108 struct sk_buff *skb;
109
110 if (bcs->hw.amd7930.tx_skb != NULL) {
111 dev_kfree_skb(bcs->hw.amd7930.tx_skb);
112 bcs->hw.amd7930.tx_skb = NULL;
113 }
114
115 if ((skb = skb_dequeue(&bcs->squeue))) {
116 Bchan_fill_fifo(bcs, skb);
117 } else {
118 clear_bit(BC_FLG_BUSY, &bcs->Flag);
119 bcs->event |= 1 << B_XMTBUFREADY;
120 queue_task(&bcs->tqueue, &tq_immediate);
121 mark_bh(IMMEDIATE_BH);
122 }
123 }
124
125 static void
126 Bchan_xmit_callback(struct BCState *bcs)
127 {
128 queue_task(&bcs->hw.amd7930.tq_xmt, &tq_immediate);
129 mark_bh(IMMEDIATE_BH);
130 }
131
132 /* B channel transmission: two modes (three, if you count L1_MODE_NULL)
133 *
134 * L1_MODE_HDLC - We need to do HDLC encapsulation before transmiting
135 * the packet (i.e. make_raw_hdlc_data). Since this can be a
136 * time-consuming operation, our completion callback just schedules
137 * a bottom half to do encapsulation for the next packet. In between,
138 * the link will just idle
139 *
140 * L1_MODE_TRANS - Data goes through, well, transparent. No HDLC encap,
141 * and we can't just let the link idle, so the "bottom half" actually
142 * gets called during the top half (it's our callback routine in this case),
143 * but it's a lot faster now since we don't call make_raw_hdlc_data
144 */
145
146 static void
147 Bchan_fill_fifo(struct BCState *bcs, struct sk_buff *skb)
148 {
149 struct IsdnCardState *cs = bcs->cs;
150 int len;
151
152 if ((cs->debug & L1_DEB_HSCX) || (cs->debug & L1_DEB_HSCX_FIFO)) {
153 char tmp[1024];
154 char *t = tmp;
155
156 t += sprintf(t, "amd7930_fill_fifo %c cnt %d",
157 bcs->channel ? 'B' : 'A', skb->len);
158 if (cs->debug & L1_DEB_HSCX_FIFO)
159 QuickHex(t, skb->data, skb->len);
160 debugl1(cs, tmp);
161 }
162
163 if (bcs->mode == L1_MODE_HDLC) {
164 len = make_raw_hdlc_data(skb->data, skb->len,
165 bcs->hw.amd7930.tx_buff, RAW_BUFMAX);
166 if (len > 0)
167 amd7930_bxmit(0, bcs->channel,
168 bcs->hw.amd7930.tx_buff, len,
169 (void *) &Bchan_xmit_callback,
170 (void *) bcs);
171 dev_kfree_skb(skb);
172 } else if (bcs->mode == L1_MODE_TRANS) {
173 amd7930_bxmit(0, bcs->channel,
174 bcs->hw.amd7930.tx_buff, skb->len,
175 (void *) &Bchan_xmt_bh,
176 (void *) bcs);
177 bcs->hw.amd7930.tx_skb = skb;
178 } else {
179 dev_kfree_skb(skb);
180 }
181 }
182
183 static void
184 Bchan_mode(struct BCState *bcs, int mode, int bc)
185 {
186 struct IsdnCardState *cs = bcs->cs;
187
188 if (cs->debug & L1_DEB_HSCX) {
189 char tmp[40];
190 sprintf(tmp, "AMD 7930 mode %d bchan %d/%d",
191 mode, bc, bcs->channel);
192 debugl1(cs, tmp);
193 }
194 bcs->mode = mode;
195 }
196
197 /* Bchan_l2l1 is the entry point for upper layer routines that want to
198 * transmit on the B channel. PH_DATA_REQ is a normal packet that
199 * we either start transmitting (if idle) or queue (if busy).
200 * PH_PULL_REQ can be called to request a callback message (PH_PULL_CNF)
201 * once the link is idle. After a "pull" callback, the upper layer
202 * routines can use PH_PULL_IND to send data.
203 */
204
205 static void
206 Bchan_l2l1(struct PStack *st, int pr, void *arg)
207 {
208 struct sk_buff *skb = arg;
209
210 switch (pr) {
211 case (PH_DATA_REQ):
212 if (test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
213 skb_queue_tail(&st->l1.bcs->squeue, skb);
214 } else {
215 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
216 Bchan_fill_fifo(st->l1.bcs, skb);
217 }
218 break;
219 case (PH_PULL_IND):
220 if (test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
221 printk(KERN_WARNING "amd7930: this shouldn't happen\n");
222 break;
223 }
224 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
225 Bchan_fill_fifo(st->l1.bcs, skb);
226 break;
227 case (PH_PULL_REQ):
228 if (!test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
229 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
230 st->l1.l1l2(st, PH_PULL_CNF, NULL);
231 } else
232 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
233 break;
234 }
235 }
236
237 /* Receiver callback and bottom half - decodes HDLC at leisure (if
238 * L1_MODE_HDLC) and passes newly received skb on via bcs->rqueue. If
239 * a large packet is received, stick rv_skb (the buffer that the
240 * packet has been decoded into) on the receive queue and alloc a new
241 * (large) skb to act as buffer for future receives. If a small
242 * packet is received, leave rv_skb alone, alloc a new skb of the
243 * correct size, and copy the packet into it
244 */
245
246 static void
247 Bchan_recv_callback(struct BCState *bcs)
248 {
249 struct amd7930_hw *hw = &bcs->hw.amd7930;
250
251 hw->rv_buff_in += RCV_BUFSIZE/RCV_BUFBLKS;
252 hw->rv_buff_in %= RCV_BUFSIZE;
253
254 if (hw->rv_buff_in != hw->rv_buff_out) {
255 amd7930_brecv(0, bcs->channel,
256 hw->rv_buff + hw->rv_buff_in,
257 RCV_BUFSIZE/RCV_BUFBLKS,
258 (void *) &Bchan_recv_callback, (void *) bcs);
259 }
260
261 queue_task(&hw->tq_rcv, &tq_immediate);
262 mark_bh(IMMEDIATE_BH);
263 }
264
265 static void
266 Bchan_rcv_bh(struct BCState *bcs)
267 {
268 struct IsdnCardState *cs = bcs->cs;
269 struct amd7930_hw *hw = &bcs->hw.amd7930;
270 struct sk_buff *skb;
271 int len;
272
273 if (cs->debug & L1_DEB_HSCX) {
274 char tmp[1024];
275
276 sprintf(tmp, "amd7930_Bchan_rcv (%d/%d)",
277 hw->rv_buff_in, hw->rv_buff_out);
278 debugl1(cs, tmp);
279 QuickHex(tmp, hw->rv_buff + hw->rv_buff_out,
280 RCV_BUFSIZE/RCV_BUFBLKS);
281 debugl1(cs, tmp);
282 }
283
284 do {
285 if (bcs->mode == L1_MODE_HDLC) {
286 while ((len = read_raw_hdlc_data(hw->hdlc_state,
287 hw->rv_buff + hw->rv_buff_out, RCV_BUFSIZE/RCV_BUFBLKS,
288 hw->rv_skb->tail, HSCX_BUFMAX))) {
289 if (len > 0 && (cs->debug & L1_DEB_HSCX_FIFO)) {
290 char tmp[1024];
291 char *t = tmp;
292
293 t += sprintf(t, "amd7930_Bchan_rcv %c cnt %d", bcs->channel ? 'B' : 'A', len);
294 QuickHex(t, hw->rv_skb->tail, len);
295 debugl1(cs, tmp);
296 }
297
298 if (len > HSCX_BUFMAX/2) {
299 /* Large packet received */
300
301 if (!(skb = dev_alloc_skb(HSCX_BUFMAX))) {
302 printk(KERN_WARNING "amd7930: receive out of memory");
303 } else {
304 skb_put(hw->rv_skb, len);
305 skb_queue_tail(&bcs->rqueue, hw->rv_skb);
306 hw->rv_skb = skb;
307 bcs->event |= 1 << B_RCVBUFREADY;
308 queue_task(&bcs->tqueue, &tq_immediate);
309 }
310 } else if (len > 0) {
311 /* Small packet received */
312
313 if (!(skb = dev_alloc_skb(len))) {
314 printk(KERN_WARNING "amd7930: receive out of memory\n");
315 } else {
316 memcpy(skb_put(skb, len), hw->rv_skb->tail, len);
317 skb_queue_tail(&bcs->rqueue, skb);
318 bcs->event |= 1 << B_RCVBUFREADY;
319 queue_task(&bcs->tqueue, &tq_immediate);
320 mark_bh(IMMEDIATE_BH);
321 }
322 } else {
323 /* Reception Error */
324 /* printk("amd7930: B channel receive error\n"); */
325 }
326 }
327 } else if (bcs->mode == L1_MODE_TRANS) {
328 if (!(skb = dev_alloc_skb(RCV_BUFSIZE/RCV_BUFBLKS))) {
329 printk(KERN_WARNING "amd7930: receive out of memory\n");
330 } else {
331 memcpy(skb_put(skb, RCV_BUFSIZE/RCV_BUFBLKS),
332 hw->rv_buff + hw->rv_buff_out,
333 RCV_BUFSIZE/RCV_BUFBLKS);
334 skb_queue_tail(&bcs->rqueue, skb);
335 bcs->event |= 1 << B_RCVBUFREADY;
336 queue_task(&bcs->tqueue, &tq_immediate);
337 mark_bh(IMMEDIATE_BH);
338 }
339 }
340
341 if (hw->rv_buff_in == hw->rv_buff_out) {
342 /* Buffer was filled up - need to restart receiver */
343 amd7930_brecv(0, bcs->channel,
344 hw->rv_buff + hw->rv_buff_in,
345 RCV_BUFSIZE/RCV_BUFBLKS,
346 (void *) &Bchan_recv_callback,
347 (void *) bcs);
348 }
349
350 hw->rv_buff_out += RCV_BUFSIZE/RCV_BUFBLKS;
351 hw->rv_buff_out %= RCV_BUFSIZE;
352
353 } while (hw->rv_buff_in != hw->rv_buff_out);
354 }
355
356 static void
357 Bchan_close(struct BCState *bcs)
358 {
359 struct sk_buff *skb;
360
361 Bchan_mode(bcs, 0, 0);
362 amd7930_bclose(0, bcs->channel);
363
364 if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
365 skb_queue_purge(&bcs->rqueue);
366 skb_queue_purge(&bcs->squeue);
367 }
368 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
369 }
370
371 static int
372 Bchan_open(struct BCState *bcs)
373 {
374 struct amd7930_hw *hw = &bcs->hw.amd7930;
375
376 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
377 skb_queue_head_init(&bcs->rqueue);
378 skb_queue_head_init(&bcs->squeue);
379 }
380 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
381
382 amd7930_bopen(0, bcs->channel, 0xff);
383 hw->rv_buff_in = 0;
384 hw->rv_buff_out = 0;
385 hw->tx_skb = NULL;
386 init_hdlc_state(hw->hdlc_state, 0);
387 amd7930_brecv(0, bcs->channel,
388 hw->rv_buff + hw->rv_buff_in, RCV_BUFSIZE/RCV_BUFBLKS,
389 (void *) &Bchan_recv_callback, (void *) bcs);
390
391 bcs->event = 0;
392 bcs->tx_cnt = 0;
393 return (0);
394 }
395
396 static void
397 Bchan_init(struct BCState *bcs)
398 {
399 if (!(bcs->hw.amd7930.tx_buff = kmalloc(RAW_BUFMAX, GFP_ATOMIC))) {
400 printk(KERN_WARNING
401 "HiSax: No memory for amd7930.tx_buff\n");
402 return;
403 }
404 if (!(bcs->hw.amd7930.rv_buff = kmalloc(RCV_BUFSIZE, GFP_ATOMIC))) {
405 printk(KERN_WARNING
406 "HiSax: No memory for amd7930.rv_buff\n");
407 return;
408 }
409 if (!(bcs->hw.amd7930.rv_skb = dev_alloc_skb(HSCX_BUFMAX))) {
410 printk(KERN_WARNING
411 "HiSax: No memory for amd7930.rv_skb\n");
412 return;
413 }
414 if (!(bcs->hw.amd7930.hdlc_state = kmalloc(sizeof(struct hdlc_state),
415 GFP_ATOMIC))) {
416 printk(KERN_WARNING
417 "HiSax: No memory for amd7930.hdlc_state\n");
418 return;
419 }
420
421 bcs->hw.amd7930.tq_rcv.sync = 0;
422 bcs->hw.amd7930.tq_rcv.routine = (void (*)(void *)) &Bchan_rcv_bh;
423 bcs->hw.amd7930.tq_rcv.data = (void *) bcs;
424
425 bcs->hw.amd7930.tq_xmt.sync = 0;
426 bcs->hw.amd7930.tq_xmt.routine = (void (*)(void *)) &Bchan_xmt_bh;
427 bcs->hw.amd7930.tq_xmt.data = (void *) bcs;
428 }
429
430 static void
431 Bchan_manl1(struct PStack *st, int pr,
432 void *arg)
433 {
434 switch (pr) {
435 case (PH_ACTIVATE_REQ):
436 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
437 Bchan_mode(st->l1.bcs, st->l1.mode, st->l1.bc);
438 st->l1.l1man(st, PH_ACTIVATE_CNF, NULL);
439 break;
440 case (PH_DEACTIVATE_REQ):
441 if (!test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag))
442 Bchan_mode(st->l1.bcs, 0, 0);
443 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
444 break;
445 }
446 }
447
448 int
449 setstack_amd7930(struct PStack *st, struct BCState *bcs)
450 {
451 if (Bchan_open(bcs))
452 return (-1);
453 st->l1.bcs = bcs;
454 st->l2.l2l1 = Bchan_l2l1;
455 st->ma.manl1 = Bchan_manl1;
456 setstack_manager(st);
457 bcs->st = st;
458 return (0);
459 }
460
461
462 static void
463 amd7930_drecv_callback(void *arg, int error, unsigned int count)
464 {
465 struct IsdnCardState *cs = (struct IsdnCardState *) arg;
466 static struct tq_struct task;
467 struct sk_buff *skb;
468
469 /* NOTE: This function is called directly from an interrupt handler */
470
471 if (1) {
472 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
473 printk(KERN_WARNING "HiSax: D receive out of memory\n");
474 else {
475 memcpy(skb_put(skb, count), cs->rcvbuf, count);
476 skb_queue_tail(&cs->rq, skb);
477 }
478
479 task.routine = (void *) DChannel_proc_rcv;
480 task.data = (void *) cs;
481 queue_task(&task, &tq_immediate);
482 mark_bh(IMMEDIATE_BH);
483 }
484
485 if (cs->debug & L1_DEB_ISAC_FIFO) {
486 char tmp[128];
487 char *t = tmp;
488
489 t += sprintf(t, "amd7930 Drecv cnt %d", count);
490 if (error) t += sprintf(t, " ERR %x", error);
491 QuickHex(t, cs->rcvbuf, count);
492 debugl1(cs, tmp);
493 }
494
495 amd7930_drecv(0, cs->rcvbuf, MAX_DFRAME_LEN,
496 &amd7930_drecv_callback, cs);
497 }
498
499 static void
500 amd7930_dxmit_callback(void *arg, int error)
501 {
502 struct IsdnCardState *cs = (struct IsdnCardState *) arg;
503 static struct tq_struct task;
504
505 /* NOTE: This function is called directly from an interrupt handler */
506
507 /* may wish to do retransmission here, if error indicates collision */
508
509 if (cs->debug & L1_DEB_ISAC_FIFO) {
510 char tmp[128];
511 char *t = tmp;
512
513 t += sprintf(t, "amd7930 Dxmit cnt %d", cs->tx_skb->len);
514 if (error) t += sprintf(t, " ERR %x", error);
515 QuickHex(t, cs->tx_skb->data, cs->tx_skb->len);
516 debugl1(cs, tmp);
517 }
518
519 cs->tx_skb = NULL;
520
521 task.routine = (void *) DChannel_proc_xmt;
522 task.data = (void *) cs;
523 queue_task(&task, &tq_immediate);
524 mark_bh(IMMEDIATE_BH);
525 }
526
527 static void
528 amd7930_Dchan_l2l1(struct PStack *st, int pr, void *arg)
529 {
530 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
531 struct sk_buff *skb = arg;
532 char str[64];
533
534 switch (pr) {
535 case (PH_DATA_REQ):
536 if (cs->tx_skb) {
537 skb_queue_tail(&cs->sq, skb);
538 #ifdef L2FRAME_DEBUG /* psa */
539 if (cs->debug & L1_DEB_LAPD)
540 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
541 #endif
542 } else {
543 if ((cs->dlogflag) && (!(skb->data[2] & 1))) {
544 /* I-FRAME */
545 LogFrame(cs, skb->data, skb->len);
546 sprintf(str, "Q.931 frame user->network tei %d", st->l2.tei);
547 dlogframe(cs, skb->data+4, skb->len-4,
548 str);
549 }
550 cs->tx_skb = skb;
551 cs->tx_cnt = 0;
552 #ifdef L2FRAME_DEBUG /* psa */
553 if (cs->debug & L1_DEB_LAPD)
554 Logl2Frame(cs, skb, "PH_DATA", 0);
555 #endif
556 amd7930_dxmit(0, skb->data, skb->len,
557 &amd7930_dxmit_callback, cs);
558 }
559 break;
560 case (PH_PULL_IND):
561 if (cs->tx_skb) {
562 if (cs->debug & L1_DEB_WARN)
563 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
564 skb_queue_tail(&cs->sq, skb);
565 break;
566 }
567 if ((cs->dlogflag) && (!(skb->data[2] & 1))) { /* I-FRAME */
568 LogFrame(cs, skb->data, skb->len);
569 sprintf(str, "Q.931 frame user->network tei %d", st->l2.tei);
570 dlogframe(cs, skb->data + 4, skb->len - 4,
571 str);
572 }
573 cs->tx_skb = skb;
574 cs->tx_cnt = 0;
575 #ifdef L2FRAME_DEBUG /* psa */
576 if (cs->debug & L1_DEB_LAPD)
577 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
578 #endif
579 amd7930_dxmit(0, cs->tx_skb->data, cs->tx_skb->len,
580 &amd7930_dxmit_callback, cs);
581 break;
582 case (PH_PULL_REQ):
583 #ifdef L2FRAME_DEBUG /* psa */
584 if (cs->debug & L1_DEB_LAPD)
585 debugl1(cs, "-> PH_REQUEST_PULL");
586 #endif
587 if (!cs->tx_skb) {
588 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
589 st->l1.l1l2(st, PH_PULL_CNF, NULL);
590 } else
591 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
592 break;
593 }
594 }
595
596 int
597 setDstack_amd7930(struct PStack *st, struct IsdnCardState *cs)
598 {
599 st->l2.l2l1 = amd7930_Dchan_l2l1;
600 if (! cs->rcvbuf) {
601 printk("setDstack_amd7930: No cs->rcvbuf!\n");
602 } else {
603 amd7930_drecv(0, cs->rcvbuf, MAX_DFRAME_LEN,
604 &amd7930_drecv_callback, cs);
605 }
606 return (0);
607 }
608
609 static void
610 manl1_msg(struct IsdnCardState *cs, int msg, void *arg) {
611 struct PStack *st;
612
613 st = cs->stlist;
614 while (st) {
615 st->ma.manl1(st, msg, arg);
616 st = st->next;
617 }
618 }
619
620 static void
621 amd7930_new_ph(struct IsdnCardState *cs)
622 {
623 switch (amd7930_get_liu_state(0)) {
624 case 3:
625 manl1_msg(cs, PH_POWERUP_CNF, NULL);
626 break;
627
628 case 7:
629 manl1_msg(cs, PH_I4_P8_IND, NULL);
630 break;
631
632 case 8:
633 manl1_msg(cs, PH_RSYNC_IND, NULL);
634 break;
635 }
636 }
637
638 /* amd7930 LIU state change callback */
639
640 static void
641 amd7930_liu_callback(struct IsdnCardState *cs)
642 {
643 static struct tq_struct task;
644
645 if (!cs)
646 return;
647
648 if (cs->debug & L1_DEB_ISAC) {
649 char tmp[32];
650 sprintf(tmp, "amd7930_liu state %d", amd7930_get_liu_state(0));
651 debugl1(cs, tmp);
652 }
653
654 task.sync = 0;
655 task.routine = (void *) &amd7930_new_ph;
656 task.data = (void *) cs;
657 queue_task(&task, &tq_immediate);
658 mark_bh(IMMEDIATE_BH);
659 }
660
661 void
662 amd7930_l1cmd(struct IsdnCardState *cs, int msg, void *arg)
663 {
664 u_char val;
665 char tmp[32];
666
667 if (cs->debug & L1_DEB_ISAC) {
668 char tmp[32];
669 sprintf(tmp, "amd7930_l1cmd msg %x", msg);
670 debugl1(cs, tmp);
671 }
672
673 switch(msg) {
674 case PH_RESET_REQ:
675 if (amd7930_get_liu_state(0) <= 3)
676 amd7930_liu_activate(0,0);
677 else
678 amd7930_liu_deactivate(0);
679 break;
680 case PH_ENABLE_REQ:
681 break;
682 case PH_INFO3_REQ:
683 amd7930_liu_activate(0,0);
684 break;
685 case PH_TESTLOOP_REQ:
686 break;
687 default:
688 if (cs->debug & L1_DEB_WARN) {
689 sprintf(tmp, "amd7930_l1cmd unknown %4x", msg);
690 debugl1(cs, tmp);
691 }
692 break;
693 }
694 }
695
696 static void init_amd7930(struct IsdnCardState *cs)
697 {
698 Bchan_init(&cs->bcs[0]);
699 Bchan_init(&cs->bcs[1]);
700 cs->bcs[0].BC_SetStack = setstack_amd7930;
701 cs->bcs[1].BC_SetStack = setstack_amd7930;
702 cs->bcs[0].BC_Close = Bchan_close;
703 cs->bcs[1].BC_Close = Bchan_close;
704 Bchan_mode(cs->bcs, 0, 0);
705 Bchan_mode(cs->bcs + 1, 0, 0);
706 }
707
708 void
709 release_amd7930(struct IsdnCardState *cs)
710 {
711 }
712
713 static int
714 amd7930_card_msg(struct IsdnCardState *cs, int mt, void *arg)
715 {
716 switch (mt) {
717 case CARD_RESET:
718 return(0);
719 case CARD_RELEASE:
720 release_amd7930(cs);
721 return(0);
722 case CARD_INIT:
723 cs->l1cmd = amd7930_l1cmd;
724 amd7930_liu_init(0, &amd7930_liu_callback, (void *)cs);
725 init_amd7930(cs);
726 return(0);
727 case CARD_TEST:
728 return(0);
729 }
730 return(0);
731 }
732
733 int __init
734 setup_amd7930(struct IsdnCard *card)
735 {
736 struct IsdnCardState *cs = card->cs;
737 char tmp[64];
738
739 strcpy(tmp, amd7930_revision);
740 printk(KERN_INFO "HiSax: AMD7930 driver Rev. %s\n", HiSax_getrev(tmp));
741 if (cs->typ != ISDN_CTYPE_AMD7930)
742 return (0);
743
744 cs->irq = amd7930_get_irqnum(0);
745 if (cs->irq == 0)
746 return (0);
747
748 cs->cardmsg = &amd7930_card_msg;
749
750 return (1);
751 }
752