File: /usr/src/linux/drivers/isdn/hisax/jade.h

1     /* $Id: jade.h,v 1.3.6.1 2001/02/16 16:43:27 kai Exp $
2      * jade.h   JADE specific defines
3      *
4      * Author   Roland Klabunde (R.Klabunde@Berkom.de)
5      *
6      * This file is (c) under GNU General Public License
7      *
8      */
9     
10     /* All Registers original Siemens Spec  */
11     #ifndef	__JADE_H__
12     #define	__JADE_H__
13     
14     /* Special registers for access to indirect accessible JADE regs */
15     #define	DIRECT_IO_JADE	0x0000	/* Jade direct io access area */
16     #define	COMM_JADE	0x0040	/* Jade communication area */	   	
17     
18     /********************************************************************/
19     /* JADE-HDLC registers         									    */
20     /********************************************************************/
21     #define jade_HDLC_RFIFO	   				0x00				   /* R */
22     #define jade_HDLC_XFIFO	   				0x00				   /* W */
23     
24     #define	jade_HDLC_STAR	   				0x20				   /* R */
25     	#define	jadeSTAR_XDOV				0x80
26     	#define	jadeSTAR_XFW 				0x40 /* Does not work*/
27     	#define	jadeSTAR_XCEC 				0x20
28     	#define	jadeSTAR_RCEC				0x10
29     	#define	jadeSTAR_BSY 				0x08
30     	#define	jadeSTAR_RNA 				0x04
31     	#define	jadeSTAR_STR 				0x02
32     	#define	jadeSTAR_STX				0x01
33     
34     #define	jade_HDLC_XCMD	   				0x20				   /* W */
35     	#define	jadeXCMD_XF				0x80
36     	#define	jadeXCMD_XME				0x40
37     	#define	jadeXCMD_XRES				0x20
38     	#define	jadeXCMD_STX				0x01
39     
40     #define	jade_HDLC_RSTA	   				0x21				   /* R */
41         #define	jadeRSTA_VFR				0x80
42         #define	jadeRSTA_RDO				0x40
43         #define	jadeRSTA_CRC				0x20
44         #define	jadeRSTA_RAB				0x10
45         #define	jadeRSTA_MASK			   	0xF0
46     
47     #define	jade_HDLC_MODE					0x22				   /* RW*/
48         #define	jadeMODE_TMO				0x80
49         #define	jadeMODE_RAC				0x40
50         #define	jadeMODE_XAC				0x20
51         #define	jadeMODE_TLP				0x10
52         #define	jadeMODE_ERFS				0x02
53         #define	jadeMODE_ETFS				0x01
54     
55     #define	jade_HDLC_RBCH					0x24				   /* R */
56     
57     #define	jade_HDLC_RBCL	 				0x25				   /* R */
58     #define	jade_HDLC_RCMD	 				0x25				   /* W */
59     	#define	jadeRCMD_RMC 				0x80
60     	#define	jadeRCMD_RRES				0x40
61     	#define	jadeRCMD_RMD				0x20
62     	#define	jadeRCMD_STR				0x02
63     
64     #define	jade_HDLC_CCR0					0x26				   /* RW*/
65     	#define	jadeCCR0_PU  				0x80
66     	#define	jadeCCR0_ITF				0x40
67     	#define	jadeCCR0_C32				0x20
68     	#define	jadeCCR0_CRL				0x10
69     	#define	jadeCCR0_RCRC				0x08
70     	#define	jadeCCR0_XCRC				0x04
71     	#define	jadeCCR0_RMSB				0x02
72     	#define	jadeCCR0_XMSB				0x01
73     
74     #define	jade_HDLC_CCR1					0x27				   /* RW*/
75         #define	jadeCCR1_RCS0				0x80
76         #define	jadeCCR1_RCONT				0x40
77         #define	jadeCCR1_RFDIS				0x20
78         #define	jadeCCR1_XCS0				0x10
79         #define	jadeCCR1_XCONT				0x08
80         #define	jadeCCR1_XFDIS				0x04
81     
82     #define	jade_HDLC_TSAR					0x28				   /* RW*/
83     #define	jade_HDLC_TSAX					0x29				   /* RW*/
84     #define	jade_HDLC_RCCR					0x2A				   /* RW*/
85     #define	jade_HDLC_XCCR					0x2B				   /* RW*/
86     
87     #define	jade_HDLC_ISR 					0x2C				   /* R */
88     #define	jade_HDLC_IMR 					0x2C				   /* W */
89     	#define	jadeISR_RME					0x80
90     	#define	jadeISR_RPF					0x40
91     	#define	jadeISR_RFO					0x20
92     	#define	jadeISR_XPR					0x10
93     	#define	jadeISR_XDU					0x08
94     	#define	jadeISR_ALLS				0x04
95     
96     #define jade_INT            			0x75
97         #define jadeINT_HDLC1   			0x02
98         #define jadeINT_HDLC2   			0x01
99         #define jadeINT_DSP				0x04
100     #define jade_INTR            			0x70
101     
102     /********************************************************************/
103     /* Indirect accessible JADE registers of common interest		   	*/
104     /********************************************************************/
105     #define	jade_CHIPVERSIONNR				0x00 /* Does not work*/
106     
107     #define	jade_HDLCCNTRACCESS				0x10		
108     	#define	jadeINDIRECT_HAH1			0x02
109     	#define	jadeINDIRECT_HAH2			0x01
110     
111     #define	jade_HDLC1SERRXPATH				0x1D
112     #define	jade_HDLC1SERTXPATH				0x1E
113     #define	jade_HDLC2SERRXPATH				0x1F
114     #define	jade_HDLC2SERTXPATH				0x20
115     	#define	jadeINDIRECT_SLIN1			0x10
116     	#define	jadeINDIRECT_SLIN0			0x08
117     	#define	jadeINDIRECT_LMOD1			0x04
118     	#define	jadeINDIRECT_LMOD0			0x02
119     	#define	jadeINDIRECT_HHR			0x01
120     	#define	jadeINDIRECT_HHX			0x01
121     
122     #define	jade_RXAUDIOCH1CFG				0x11
123     #define	jade_RXAUDIOCH2CFG				0x14
124     #define	jade_TXAUDIOCH1CFG				0x17
125     #define	jade_TXAUDIOCH2CFG				0x1A
126     
127     extern int JadeVersion(struct IsdnCardState *cs, char *s);
128     extern void jade_sched_event(struct BCState *bcs, int event);
129     extern void modejade(struct BCState *bcs, int mode, int bc);
130     extern void clear_pending_jade_ints(struct IsdnCardState *cs);
131     extern void initjade(struct IsdnCardState *cs);
132     
133     #endif	/* __JADE_H__ */
134